projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
powerpc: Move altivec_unavailable
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / powerpc / kernel / head_32.S
CommitLineData
14cf11af
PM		 1/*
2 * PowerPC version
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 *
5 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
6 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
7 * Adapted for Power Macintosh by Paul Mackerras.
8 * Low-level exception handlers and MMU support
9 * rewritten by Paul Mackerras.
10 * Copyright (C) 1996 Paul Mackerras.
11 * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
14cf11af
PM		 12 *
13 * This file contains the low-level support and setup for the
14 * PowerPC platform, including trap and interrupt dispatch.
15 * (The PPC 8xx embedded CPUs use head_8xx.S instead.)
16 *
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License
19 * as published by the Free Software Foundation; either version
20 * 2 of the License, or (at your option) any later version.
21 *
22 */
23
b3b8dc6c 24#include <asm/reg.h>
14cf11af
PM		 25#include <asm/page.h>
26#include <asm/mmu.h>
27#include <asm/pgtable.h>
28#include <asm/cputable.h>
29#include <asm/cache.h>
30#include <asm/thread_info.h>
31#include <asm/ppc_asm.h>
32#include <asm/asm-offsets.h>
ec2b36b9 33#include <asm/ptrace.h>
14cf11af 34
14cf11af
PM		 35/* 601 only have IBAT; cr0.eq is set on 601 when using this macro */
36#define LOAD_BAT(n, reg, RA, RB) \
37 /* see the comment for clear_bats() -- Cort */ \
38 li RA,0; \
39 mtspr SPRN_IBAT##n##U,RA; \
40 mtspr SPRN_DBAT##n##U,RA; \
41 lwz RA,(n*16)+0(reg); \
42 lwz RB,(n*16)+4(reg); \
43 mtspr SPRN_IBAT##n##U,RA; \
44 mtspr SPRN_IBAT##n##L,RB; \
45 beq 1f; \
46 lwz RA,(n*16)+8(reg); \
47 lwz RB,(n*16)+12(reg); \
48 mtspr SPRN_DBAT##n##U,RA; \
49 mtspr SPRN_DBAT##n##L,RB; \
501:
14cf11af 51
748a7683 52 .section .text.head, "ax"
b3b8dc6c
PM		 53 .stabs "arch/powerpc/kernel/",N_SO,0,0,0f
54 .stabs "head_32.S",N_SO,0,0,0f
14cf11af 550:
748a7683 56_ENTRY(_stext);
14cf11af
PM		 57
58/*
59 * _start is defined this way because the XCOFF loader in the OpenFirmware
60 * on the powermac expects the entry point to be a procedure descriptor.
61 */
748a7683 62_ENTRY(_start);
14cf11af
PM		 63 /*
64 * These are here for legacy reasons, the kernel used to
65 * need to look like a coff function entry for the pmac
66 * but we're always started by some kind of bootloader now.
67 * -- Cort
68 */
69 nop /* used by __secondary_hold on prep (mtx) and chrp smp */
70 nop /* used by __secondary_hold on prep (mtx) and chrp smp */
71 nop
72
73/* PMAC
74 * Enter here with the kernel text, data and bss loaded starting at
75 * 0, running with virtual == physical mapping.
76 * r5 points to the prom entry point (the client interface handler
77 * address). Address translation is turned on, with the prom
78 * managing the hash table. Interrupts are disabled. The stack
79 * pointer (r1) points to just below the end of the half-meg region
80 * from 0x380000 - 0x400000, which is mapped in already.
81 *
82 * If we are booted from MacOS via BootX, we enter with the kernel
83 * image loaded somewhere, and the following values in registers:
84 * r3: 'BooX' (0x426f6f58)
85 * r4: virtual address of boot_infos_t
86 * r5: 0
87 *
14cf11af
PM		 88 * PREP
89 * This is jumped to on prep systems right after the kernel is relocated
90 * to its proper place in memory by the boot loader. The expected layout
91 * of the regs is:
92 * r3: ptr to residual data
93 * r4: initrd_start or if no initrd then 0
94 * r5: initrd_end - unused if r4 is 0
95 * r6: Start of command line string
96 * r7: End of command line string
97 *
98 * This just gets a minimal mmu environment setup so we can call
99 * start_here() to do the real work.
100 * -- Cort
101 */
102
103 .globl __start
104__start:
105/*
106 * We have to do any OF calls before we map ourselves to KERNELBASE,
107 * because OF may have I/O devices mapped into that area
108 * (particularly on CHRP).
109 */
0a498d96 110#ifdef CONFIG_PPC_MULTIPLATFORM
9b6b563c
PM		 111 cmpwi 0,r5,0
112 beq 1f
113 bl prom_init
114 trap
0a498d96 115#endif
9b6b563c 116
d7f39454
BH		 117/*
118 * Check for BootX signature when supporting PowerMac and branch to
119 * appropriate trampoline if it's present
120 */
121#ifdef CONFIG_PPC_PMAC
1221: lis r31,0x426f
123 ori r31,r31,0x6f58
124 cmpw 0,r3,r31
125 bne 1f
126 bl bootx_init
127 trap
128#endif /* CONFIG_PPC_PMAC */
129
9b6b563c 1301: mr r31,r3 /* save parameters */
14cf11af 131 mr r30,r4
14cf11af
PM		 132 li r24,0 /* cpu # */
133
134/*
135 * early_init() does the early machine identification and does
136 * the necessary low-level setup and clears the BSS
137 * -- Cort <cort@fsmlabs.com>
138 */
139 bl early_init
140
14cf11af
PM		 141/* Switch MMU off, clear BATs and flush TLB. At this point, r3 contains
142 * the physical address we are running at, returned by early_init()
143 */
144 bl mmu_off
145__after_mmu_off:
14cf11af
PM		 146 bl clear_bats
147 bl flush_tlbs
148
149 bl initial_bats
f21f49ea 150#if defined(CONFIG_BOOTX_TEXT)
51d3082f
BH		 151 bl setup_disp_bat
152#endif
c374e00e
SW		 153#ifdef CONFIG_PPC_EARLY_DEBUG_CPM
154 bl setup_cpm_bat
155#endif
14cf11af
PM		 156
157/*
158 * Call setup_cpu for CPU 0 and initialize 6xx Idle
159 */
160 bl reloc_offset
161 li r24,0 /* cpu# */
162 bl call_setup_cpu /* Call setup_cpu for this CPU */
163#ifdef CONFIG_6xx
164 bl reloc_offset
165 bl init_idle_6xx
166#endif /* CONFIG_6xx */
14cf11af
PM		 167
168
14cf11af
PM		 169/*
170 * We need to run with _start at physical address 0.
171 * On CHRP, we are loaded at 0x10000 since OF on CHRP uses
172 * the exception vectors at 0 (and therefore this copy
173 * overwrites OF's exception vectors with our own).
9b6b563c 174 * The MMU is off at this point.
14cf11af
PM		 175 */
176 bl reloc_offset
177 mr r26,r3
178 addis r4,r3,KERNELBASE@h /* current address of _start */
179 cmpwi 0,r4,0 /* are we already running at 0? */
180 bne relocate_kernel
14cf11af
PM		 181/*
182 * we now have the 1st 16M of ram mapped with the bats.
183 * prep needs the mmu to be turned on here, but pmac already has it on.
184 * this shouldn't bother the pmac since it just gets turned on again
185 * as we jump to our code at KERNELBASE. -- Cort
186 * Actually no, pmac doesn't have it on any more. BootX enters with MMU
187 * off, and in other cases, we now turn it off before changing BATs above.
188 */
189turn_on_mmu:
190 mfmsr r0
191 ori r0,r0,MSR_DR|MSR_IR
192 mtspr SPRN_SRR1,r0
193 lis r0,start_here@h
194 ori r0,r0,start_here@l
195 mtspr SPRN_SRR0,r0
196 SYNC
197 RFI /* enables MMU */
198
199/*
200 * We need __secondary_hold as a place to hold the other cpus on
201 * an SMP machine, even when we are running a UP kernel.
202 */
203 . = 0xc0 /* for prep bootloader */
204 li r3,1 /* MTX only has 1 cpu */
205 .globl __secondary_hold
206__secondary_hold:
207 /* tell the master we're here */
bbd0abda 208 stw r3,__secondary_hold_acknowledge@l(0)
14cf11af
PM		 209#ifdef CONFIG_SMP
210100: lwz r4,0(0)
211 /* wait until we're told to start */
212 cmpw 0,r4,r3
213 bne 100b
214 /* our cpu # was at addr 0 - go */
215 mr r24,r3 /* cpu # */
216 b __secondary_start
217#else
218 b .
219#endif /* CONFIG_SMP */
220
bbd0abda
PM		 221 .globl __secondary_hold_spinloop
222__secondary_hold_spinloop:
223 .long 0
224 .globl __secondary_hold_acknowledge
225__secondary_hold_acknowledge:
226 .long -1
227
14cf11af
PM		 228/*
229 * Exception entry code. This code runs with address translation
230 * turned off, i.e. using physical addresses.
231 * We assume sprg3 has the physical address of the current
232 * task's thread_struct.
233 */
234#define EXCEPTION_PROLOG \
235 mtspr SPRN_SPRG0,r10; \
236 mtspr SPRN_SPRG1,r11; \
237 mfcr r10; \
238 EXCEPTION_PROLOG_1; \
239 EXCEPTION_PROLOG_2
240
241#define EXCEPTION_PROLOG_1 \
242 mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \
243 andi. r11,r11,MSR_PR; \
244 tophys(r11,r1); /* use tophys(r1) if kernel */ \
245 beq 1f; \
246 mfspr r11,SPRN_SPRG3; \
247 lwz r11,THREAD_INFO-THREAD(r11); \
248 addi r11,r11,THREAD_SIZE; \
249 tophys(r11,r11); \
2501: subi r11,r11,INT_FRAME_SIZE /* alloc exc. frame */
251
252
253#define EXCEPTION_PROLOG_2 \
254 CLR_TOP32(r11); \
255 stw r10,_CCR(r11); /* save registers */ \
256 stw r12,GPR12(r11); \
257 stw r9,GPR9(r11); \
258 mfspr r10,SPRN_SPRG0; \
259 stw r10,GPR10(r11); \
260 mfspr r12,SPRN_SPRG1; \
261 stw r12,GPR11(r11); \
262 mflr r10; \
263 stw r10,_LINK(r11); \
264 mfspr r12,SPRN_SRR0; \
265 mfspr r9,SPRN_SRR1; \
266 stw r1,GPR1(r11); \
267 stw r1,0(r11); \
268 tovirt(r1,r11); /* set new kernel sp */ \
269 li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \
270 MTMSRD(r10); /* (except for mach check in rtas) */ \
271 stw r0,GPR0(r11); \
ec2b36b9
BH		 272 lis r10,STACK_FRAME_REGS_MARKER@ha; /* exception frame marker */ \
273 addi r10,r10,STACK_FRAME_REGS_MARKER@l; \
f78541dc 274 stw r10,8(r11); \
14cf11af
PM		 275 SAVE_4GPRS(3, r11); \
276 SAVE_2GPRS(7, r11)
277
278/*
279 * Note: code which follows this uses cr0.eq (set if from kernel),
280 * r11, r12 (SRR0), and r9 (SRR1).
281 *
282 * Note2: once we have set r1 we are in a position to take exceptions
283 * again, and we could thus set MSR:RI at that point.
284 */
285
286/*
287 * Exception vectors.
288 */
289#define EXCEPTION(n, label, hdlr, xfer) \
290 . = n; \
291label: \
292 EXCEPTION_PROLOG; \
293 addi r3,r1,STACK_FRAME_OVERHEAD; \
294 xfer(n, hdlr)
295
296#define EXC_XFER_TEMPLATE(n, hdlr, trap, copyee, tfer, ret) \
297 li r10,trap; \
d73e0c99 298 stw r10,_TRAP(r11); \
14cf11af
PM		 299 li r10,MSR_KERNEL; \
300 copyee(r10, r9); \
301 bl tfer; \
302i##n: \
303 .long hdlr; \
304 .long ret
305
306#define COPY_EE(d, s) rlwimi d,s,0,16,16
307#define NOCOPY(d, s)
308
309#define EXC_XFER_STD(n, hdlr) \
310 EXC_XFER_TEMPLATE(n, hdlr, n, NOCOPY, transfer_to_handler_full, \
311 ret_from_except_full)
312
313#define EXC_XFER_LITE(n, hdlr) \
314 EXC_XFER_TEMPLATE(n, hdlr, n+1, NOCOPY, transfer_to_handler, \
315 ret_from_except)
316
317#define EXC_XFER_EE(n, hdlr) \
318 EXC_XFER_TEMPLATE(n, hdlr, n, COPY_EE, transfer_to_handler_full, \
319 ret_from_except_full)
320
321#define EXC_XFER_EE_LITE(n, hdlr) \
322 EXC_XFER_TEMPLATE(n, hdlr, n+1, COPY_EE, transfer_to_handler, \
323 ret_from_except)
324
325/* System reset */
326/* core99 pmac starts the seconary here by changing the vector, and
dc1c1ca3 327 putting it back to what it was (unknown_exception) when done. */
dc1c1ca3 328 EXCEPTION(0x100, Reset, unknown_exception, EXC_XFER_STD)
14cf11af
PM		 329
330/* Machine check */
331/*
332 * On CHRP, this is complicated by the fact that we could get a
333 * machine check inside RTAS, and we have no guarantee that certain
334 * critical registers will have the values we expect. The set of
335 * registers that might have bad values includes all the GPRs
336 * and all the BATs. We indicate that we are in RTAS by putting
337 * a non-zero value, the address of the exception frame to use,
338 * in SPRG2. The machine check handler checks SPRG2 and uses its
339 * value if it is non-zero. If we ever needed to free up SPRG2,
340 * we could use a field in the thread_info or thread_struct instead.
341 * (Other exception handlers assume that r1 is a valid kernel stack
342 * pointer when we take an exception from supervisor mode.)
343 * -- paulus.
344 */
345 . = 0x200
346 mtspr SPRN_SPRG0,r10
347 mtspr SPRN_SPRG1,r11
348 mfcr r10
349#ifdef CONFIG_PPC_CHRP
350 mfspr r11,SPRN_SPRG2
351 cmpwi 0,r11,0
352 bne 7f
353#endif /* CONFIG_PPC_CHRP */
354 EXCEPTION_PROLOG_1
3557: EXCEPTION_PROLOG_2
356 addi r3,r1,STACK_FRAME_OVERHEAD
357#ifdef CONFIG_PPC_CHRP
358 mfspr r4,SPRN_SPRG2
359 cmpwi cr1,r4,0
360 bne cr1,1f
361#endif
dc1c1ca3 362 EXC_XFER_STD(0x200, machine_check_exception)
14cf11af
PM		 363#ifdef CONFIG_PPC_CHRP
3641: b machine_check_in_rtas
365#endif
366
367/* Data access exception. */
368 . = 0x300
14cf11af
PM		 369DataAccess:
370 EXCEPTION_PROLOG
14cf11af
PM		 371 mfspr r10,SPRN_DSISR
372 andis. r0,r10,0xa470 /* weird error? */
373 bne 1f /* if not, try to put a PTE */
374 mfspr r4,SPRN_DAR /* into the hash table */
375 rlwinm r3,r10,32-15,21,21 /* DSISR_STORE -> _PAGE_RW */
376 bl hash_page
3771: stw r10,_DSISR(r11)
378 mr r5,r10
379 mfspr r4,SPRN_DAR
380 EXC_XFER_EE_LITE(0x300, handle_page_fault)
381
14cf11af
PM		 382
383/* Instruction access exception. */
384 . = 0x400
14cf11af
PM		 385InstructionAccess:
386 EXCEPTION_PROLOG
14cf11af
PM		 387 andis. r0,r9,0x4000 /* no pte found? */
388 beq 1f /* if so, try to put a PTE */
389 li r3,0 /* into the hash table */
390 mr r4,r12 /* SRR0 is fault address */
391 bl hash_page
3921: mr r4,r12
393 mr r5,r9
394 EXC_XFER_EE_LITE(0x400, handle_page_fault)
395
14cf11af
PM		 396/* External interrupt */
397 EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE)
398
399/* Alignment exception */
400 . = 0x600
401Alignment:
402 EXCEPTION_PROLOG
403 mfspr r4,SPRN_DAR
404 stw r4,_DAR(r11)
405 mfspr r5,SPRN_DSISR
406 stw r5,_DSISR(r11)
407 addi r3,r1,STACK_FRAME_OVERHEAD
dc1c1ca3 408 EXC_XFER_EE(0x600, alignment_exception)
14cf11af
PM		 409
410/* Program check exception */
dc1c1ca3 411 EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD)
14cf11af
PM		 412
413/* Floating-point unavailable */
414 . = 0x800
415FPUnavailable:
aa42c69c
KP		 416BEGIN_FTR_SECTION
417/*
418 * Certain Freescale cores don't have a FPU and treat fp instructions
419 * as a FP Unavailable exception. Redirect to illegal/emulation handling.
420 */
421 b ProgramCheck
422END_FTR_SECTION_IFSET(CPU_FTR_FPU_UNAVAILABLE)
14cf11af
PM		 423 EXCEPTION_PROLOG
424 bne load_up_fpu /* if from user, just load it up */
425 addi r3,r1,STACK_FRAME_OVERHEAD
8dad3f92 426 EXC_XFER_EE_LITE(0x800, kernel_fp_unavailable_exception)
14cf11af
PM		 427
428/* Decrementer */
429 EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE)
430
dc1c1ca3
SR		 431 EXCEPTION(0xa00, Trap_0a, unknown_exception, EXC_XFER_EE)
432 EXCEPTION(0xb00, Trap_0b, unknown_exception, EXC_XFER_EE)
14cf11af
PM		 433
434/* System call */
435 . = 0xc00
436SystemCall:
437 EXCEPTION_PROLOG
438 EXC_XFER_EE_LITE(0xc00, DoSyscall)
439
440/* Single step - not used on 601 */
dc1c1ca3
SR		 441 EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD)
442 EXCEPTION(0xe00, Trap_0e, unknown_exception, EXC_XFER_EE)
14cf11af
PM		 443
444/*
445 * The Altivec unavailable trap is at 0x0f20. Foo.
446 * We effectively remap it to 0x3000.
447 * We include an altivec unavailable exception vector even if
448 * not configured for Altivec, so that you can't panic a
449 * non-altivec kernel running on a machine with altivec just
450 * by executing an altivec instruction.
451 */
452 . = 0xf00
555d97ac 453 b PerformanceMonitor
14cf11af
PM		 454
455 . = 0xf20
456 b AltiVecUnavailable
457
14cf11af
PM		 458/*
459 * Handle TLB miss for instruction on 603/603e.
460 * Note: we get an alternate set of r0 - r3 to use automatically.
461 */
462 . = 0x1000
463InstructionTLBMiss:
464/*
465 * r0: stored ctr
466 * r1: linux style pte ( later becomes ppc hardware pte )
467 * r2: ptr to linux-style pte
468 * r3: scratch
469 */
470 mfctr r0
471 /* Get PTE (linux-style) and check access */
472 mfspr r3,SPRN_IMISS
8a13c4f9
KG		 473 lis r1,PAGE_OFFSET@h /* check if kernel address */
474 cmplw 0,r1,r3
14cf11af
PM		 475 mfspr r2,SPRN_SPRG3
476 li r1,_PAGE_USER|_PAGE_PRESENT /* low addresses tested as user */
477 lwz r2,PGDIR(r2)
8a13c4f9 478 bge- 112f
bde6c6e1
SW		 479 mfspr r2,SPRN_SRR1 /* and MSR_PR bit from SRR1 */
480 rlwimi r1,r2,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */
14cf11af
PM		 481 lis r2,swapper_pg_dir@ha /* if kernel address, use */
482 addi r2,r2,swapper_pg_dir@l /* kernel page table */
14cf11af
PM		 483112: tophys(r2,r2)
484 rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
485 lwz r2,0(r2) /* get pmd entry */
486 rlwinm. r2,r2,0,0,19 /* extract address of pte page */
487 beq- InstructionAddressInvalid /* return if no mapping */
488 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
489 lwz r3,0(r2) /* get linux-style pte */
490 andc. r1,r1,r3 /* check access & ~permission */
491 bne- InstructionAddressInvalid /* return if access not permitted */
492 ori r3,r3,_PAGE_ACCESSED /* set _PAGE_ACCESSED in pte */
493 /*
494 * NOTE! We are assuming this is not an SMP system, otherwise
495 * we would need to update the pte atomically with lwarx/stwcx.
496 */
497 stw r3,0(r2) /* update PTE (accessed bit) */
498 /* Convert linux-style PTE to low word of PPC-style PTE */
499 rlwinm r1,r3,32-10,31,31 /* _PAGE_RW -> PP lsb */
500 rlwinm r2,r3,32-7,31,31 /* _PAGE_DIRTY -> PP lsb */
501 and r1,r1,r2 /* writable if _RW and _DIRTY */
502 rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */
503 rlwimi r3,r3,32-1,31,31 /* _PAGE_USER -> PP lsb */
504 ori r1,r1,0xe14 /* clear out reserved bits and M */
505 andc r1,r3,r1 /* PP = user? (rw&dirty? 2: 3): 0 */
506 mtspr SPRN_RPA,r1
507 mfspr r3,SPRN_IMISS
508 tlbli r3
509 mfspr r3,SPRN_SRR1 /* Need to restore CR0 */
510 mtcrf 0x80,r3
511 rfi
512InstructionAddressInvalid:
513 mfspr r3,SPRN_SRR1
514 rlwinm r1,r3,9,6,6 /* Get load/store bit */
515
516 addis r1,r1,0x2000
517 mtspr SPRN_DSISR,r1 /* (shouldn't be needed) */
518 mtctr r0 /* Restore CTR */
519 andi. r2,r3,0xFFFF /* Clear upper bits of SRR1 */
520 or r2,r2,r1
521 mtspr SPRN_SRR1,r2
522 mfspr r1,SPRN_IMISS /* Get failing address */
523 rlwinm. r2,r2,0,31,31 /* Check for little endian access */
524 rlwimi r2,r2,1,30,30 /* change 1 -> 3 */
525 xor r1,r1,r2
526 mtspr SPRN_DAR,r1 /* Set fault address */
527 mfmsr r0 /* Restore "normal" registers */
528 xoris r0,r0,MSR_TGPR>>16
529 mtcrf 0x80,r3 /* Restore CR0 */
530 mtmsr r0
531 b InstructionAccess
532
533/*
534 * Handle TLB miss for DATA Load operation on 603/603e
535 */
536 . = 0x1100
537DataLoadTLBMiss:
538/*
539 * r0: stored ctr
540 * r1: linux style pte ( later becomes ppc hardware pte )
541 * r2: ptr to linux-style pte
542 * r3: scratch
543 */
544 mfctr r0
545 /* Get PTE (linux-style) and check access */
546 mfspr r3,SPRN_DMISS
8a13c4f9
KG		 547 lis r1,PAGE_OFFSET@h /* check if kernel address */
548 cmplw 0,r1,r3
14cf11af
PM		 549 mfspr r2,SPRN_SPRG3
550 li r1,_PAGE_USER|_PAGE_PRESENT /* low addresses tested as user */
551 lwz r2,PGDIR(r2)
8a13c4f9 552 bge- 112f
bde6c6e1
SW		 553 mfspr r2,SPRN_SRR1 /* and MSR_PR bit from SRR1 */
554 rlwimi r1,r2,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */
14cf11af
PM		 555 lis r2,swapper_pg_dir@ha /* if kernel address, use */
556 addi r2,r2,swapper_pg_dir@l /* kernel page table */
14cf11af
PM		 557112: tophys(r2,r2)
558 rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
559 lwz r2,0(r2) /* get pmd entry */
560 rlwinm. r2,r2,0,0,19 /* extract address of pte page */
561 beq- DataAddressInvalid /* return if no mapping */
562 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
563 lwz r3,0(r2) /* get linux-style pte */
564 andc. r1,r1,r3 /* check access & ~permission */
565 bne- DataAddressInvalid /* return if access not permitted */
566 ori r3,r3,_PAGE_ACCESSED /* set _PAGE_ACCESSED in pte */
567 /*
568 * NOTE! We are assuming this is not an SMP system, otherwise
569 * we would need to update the pte atomically with lwarx/stwcx.
570 */
571 stw r3,0(r2) /* update PTE (accessed bit) */
572 /* Convert linux-style PTE to low word of PPC-style PTE */
573 rlwinm r1,r3,32-10,31,31 /* _PAGE_RW -> PP lsb */
574 rlwinm r2,r3,32-7,31,31 /* _PAGE_DIRTY -> PP lsb */
575 and r1,r1,r2 /* writable if _RW and _DIRTY */
576 rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */
577 rlwimi r3,r3,32-1,31,31 /* _PAGE_USER -> PP lsb */
578 ori r1,r1,0xe14 /* clear out reserved bits and M */
579 andc r1,r3,r1 /* PP = user? (rw&dirty? 2: 3): 0 */
580 mtspr SPRN_RPA,r1
581 mfspr r3,SPRN_DMISS
582 tlbld r3
583 mfspr r3,SPRN_SRR1 /* Need to restore CR0 */
584 mtcrf 0x80,r3
585 rfi
586DataAddressInvalid:
587 mfspr r3,SPRN_SRR1
588 rlwinm r1,r3,9,6,6 /* Get load/store bit */
589 addis r1,r1,0x2000
590 mtspr SPRN_DSISR,r1
591 mtctr r0 /* Restore CTR */
592 andi. r2,r3,0xFFFF /* Clear upper bits of SRR1 */
593 mtspr SPRN_SRR1,r2
594 mfspr r1,SPRN_DMISS /* Get failing address */
595 rlwinm. r2,r2,0,31,31 /* Check for little endian access */
596 beq 20f /* Jump if big endian */
597 xori r1,r1,3
59820: mtspr SPRN_DAR,r1 /* Set fault address */
599 mfmsr r0 /* Restore "normal" registers */
600 xoris r0,r0,MSR_TGPR>>16
601 mtcrf 0x80,r3 /* Restore CR0 */
602 mtmsr r0
603 b DataAccess
604
605/*
606 * Handle TLB miss for DATA Store on 603/603e
607 */
608 . = 0x1200
609DataStoreTLBMiss:
610/*
611 * r0: stored ctr
612 * r1: linux style pte ( later becomes ppc hardware pte )
613 * r2: ptr to linux-style pte
614 * r3: scratch
615 */
616 mfctr r0
617 /* Get PTE (linux-style) and check access */
618 mfspr r3,SPRN_DMISS
8a13c4f9
KG		 619 lis r1,PAGE_OFFSET@h /* check if kernel address */
620 cmplw 0,r1,r3
14cf11af
PM		 621 mfspr r2,SPRN_SPRG3
622 li r1,_PAGE_RW|_PAGE_USER|_PAGE_PRESENT /* access flags */
623 lwz r2,PGDIR(r2)
8a13c4f9 624 bge- 112f
bde6c6e1
SW		 625 mfspr r2,SPRN_SRR1 /* and MSR_PR bit from SRR1 */
626 rlwimi r1,r2,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */
14cf11af
PM		 627 lis r2,swapper_pg_dir@ha /* if kernel address, use */
628 addi r2,r2,swapper_pg_dir@l /* kernel page table */
14cf11af
PM		 629112: tophys(r2,r2)
630 rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
631 lwz r2,0(r2) /* get pmd entry */
632 rlwinm. r2,r2,0,0,19 /* extract address of pte page */
633 beq- DataAddressInvalid /* return if no mapping */
634 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
635 lwz r3,0(r2) /* get linux-style pte */
636 andc. r1,r1,r3 /* check access & ~permission */
637 bne- DataAddressInvalid /* return if access not permitted */
638 ori r3,r3,_PAGE_ACCESSED|_PAGE_DIRTY
639 /*
640 * NOTE! We are assuming this is not an SMP system, otherwise
641 * we would need to update the pte atomically with lwarx/stwcx.
642 */
643 stw r3,0(r2) /* update PTE (accessed/dirty bits) */
644 /* Convert linux-style PTE to low word of PPC-style PTE */
645 rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */
646 li r1,0xe15 /* clear out reserved bits and M */
647 andc r1,r3,r1 /* PP = user? 2: 0 */
648 mtspr SPRN_RPA,r1
649 mfspr r3,SPRN_DMISS
650 tlbld r3
651 mfspr r3,SPRN_SRR1 /* Need to restore CR0 */
652 mtcrf 0x80,r3
653 rfi
654
655#ifndef CONFIG_ALTIVEC
dc1c1ca3 656#define altivec_assist_exception unknown_exception
14cf11af
PM		 657#endif
658
dc1c1ca3 659 EXCEPTION(0x1300, Trap_13, instruction_breakpoint_exception, EXC_XFER_EE)
14cf11af 660 EXCEPTION(0x1400, SMI, SMIException, EXC_XFER_EE)
dc1c1ca3 661 EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE)
dc1c1ca3 662 EXCEPTION(0x1600, Trap_16, altivec_assist_exception, EXC_XFER_EE)
14cf11af 663 EXCEPTION(0x1700, Trap_17, TAUException, EXC_XFER_STD)
dc1c1ca3 664 EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE)
dc1c1ca3
SR		 665 EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE)
666 EXCEPTION(0x1a00, Trap_1a, unknown_exception, EXC_XFER_EE)
667 EXCEPTION(0x1b00, Trap_1b, unknown_exception, EXC_XFER_EE)
668 EXCEPTION(0x1c00, Trap_1c, unknown_exception, EXC_XFER_EE)
669 EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_EE)
670 EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_EE)
671 EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_EE)
14cf11af 672 EXCEPTION(0x2000, RunMode, RunModeException, EXC_XFER_EE)
dc1c1ca3
SR		 673 EXCEPTION(0x2100, Trap_21, unknown_exception, EXC_XFER_EE)
674 EXCEPTION(0x2200, Trap_22, unknown_exception, EXC_XFER_EE)
675 EXCEPTION(0x2300, Trap_23, unknown_exception, EXC_XFER_EE)
676 EXCEPTION(0x2400, Trap_24, unknown_exception, EXC_XFER_EE)
677 EXCEPTION(0x2500, Trap_25, unknown_exception, EXC_XFER_EE)
678 EXCEPTION(0x2600, Trap_26, unknown_exception, EXC_XFER_EE)
679 EXCEPTION(0x2700, Trap_27, unknown_exception, EXC_XFER_EE)
680 EXCEPTION(0x2800, Trap_28, unknown_exception, EXC_XFER_EE)
681 EXCEPTION(0x2900, Trap_29, unknown_exception, EXC_XFER_EE)
682 EXCEPTION(0x2a00, Trap_2a, unknown_exception, EXC_XFER_EE)
683 EXCEPTION(0x2b00, Trap_2b, unknown_exception, EXC_XFER_EE)
684 EXCEPTION(0x2c00, Trap_2c, unknown_exception, EXC_XFER_EE)
685 EXCEPTION(0x2d00, Trap_2d, unknown_exception, EXC_XFER_EE)
686 EXCEPTION(0x2e00, Trap_2e, unknown_exception, EXC_XFER_EE)
687 EXCEPTION(0x2f00, MOLTrampoline, unknown_exception, EXC_XFER_EE_LITE)
14cf11af
PM		 688
689 .globl mol_trampoline
690 .set mol_trampoline, i0x2f00
691
692 . = 0x3000
693
694AltiVecUnavailable:
695 EXCEPTION_PROLOG
696#ifdef CONFIG_ALTIVEC
697 bne load_up_altivec /* if from user, just load it up */
698#endif /* CONFIG_ALTIVEC */
f1434a48 699 addi r3,r1,STACK_FRAME_OVERHEAD
dc1c1ca3 700 EXC_XFER_EE_LITE(0xf20, altivec_unavailable_exception)
14cf11af 701
555d97ac
AF		 702PerformanceMonitor:
703 EXCEPTION_PROLOG
704 addi r3,r1,STACK_FRAME_OVERHEAD
705 EXC_XFER_STD(0xf00, performance_monitor_exception)
706
14cf11af
PM		 707#ifdef CONFIG_ALTIVEC
708/* Note that the AltiVec support is closely modeled after the FP
709 * support. Changes to one are likely to be applicable to the
710 * other! */
711load_up_altivec:
712/*
713 * Disable AltiVec for the task which had AltiVec previously,
714 * and save its AltiVec registers in its thread_struct.
715 * Enables AltiVec for use in the kernel on return.
716 * On SMP we know the AltiVec units are free, since we give it up every
717 * switch. -- Kumar
718 */
719 mfmsr r5
720 oris r5,r5,MSR_VEC@h
721 MTMSRD(r5) /* enable use of AltiVec now */
722 isync
723/*
724 * For SMP, we don't do lazy AltiVec switching because it just gets too
725 * horrendously complex, especially when a task switches from one CPU
726 * to another. Instead we call giveup_altivec in switch_to.
727 */
728#ifndef CONFIG_SMP
729 tophys(r6,0)
730 addis r3,r6,last_task_used_altivec@ha
731 lwz r4,last_task_used_altivec@l(r3)
732 cmpwi 0,r4,0
733 beq 1f
734 add r4,r4,r6
735 addi r4,r4,THREAD /* want THREAD of last_task_used_altivec */
736 SAVE_32VRS(0,r10,r4)
737 mfvscr vr0
738 li r10,THREAD_VSCR
739 stvx vr0,r10,r4
740 lwz r5,PT_REGS(r4)
741 add r5,r5,r6
742 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
743 lis r10,MSR_VEC@h
744 andc r4,r4,r10 /* disable altivec for previous task */
745 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
7461:
747#endif /* CONFIG_SMP */
748 /* enable use of AltiVec after return */
749 oris r9,r9,MSR_VEC@h
750 mfspr r5,SPRN_SPRG3 /* current task's THREAD (phys) */
751 li r4,1
752 li r10,THREAD_VSCR
753 stw r4,THREAD_USED_VR(r5)
754 lvx vr0,r10,r5
755 mtvscr vr0
756 REST_32VRS(0,r10,r5)
757#ifndef CONFIG_SMP
758 subi r4,r5,THREAD
759 sub r4,r4,r6
760 stw r4,last_task_used_altivec@l(r3)
761#endif /* CONFIG_SMP */
762 /* restore registers and return */
763 /* we haven't used ctr or xer or lr */
764 b fast_exception_return
765
14cf11af
PM		 766/*
767 * giveup_altivec(tsk)
768 * Disable AltiVec for the task given as the argument,
769 * and save the AltiVec registers in its thread_struct.
770 * Enables AltiVec for use in the kernel on return.
771 */
772
773 .globl giveup_altivec
774giveup_altivec:
775 mfmsr r5
776 oris r5,r5,MSR_VEC@h
777 SYNC
778 MTMSRD(r5) /* enable use of AltiVec now */
779 isync
780 cmpwi 0,r3,0
781 beqlr- /* if no previous owner, done */
782 addi r3,r3,THREAD /* want THREAD of task */
783 lwz r5,PT_REGS(r3)
784 cmpwi 0,r5,0
785 SAVE_32VRS(0, r4, r3)
786 mfvscr vr0
787 li r4,THREAD_VSCR
788 stvx vr0,r4,r3
789 beq 1f
790 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
791 lis r3,MSR_VEC@h
792 andc r4,r4,r3 /* disable AltiVec for previous task */
793 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
7941:
795#ifndef CONFIG_SMP
796 li r5,0
797 lis r4,last_task_used_altivec@ha
798 stw r5,last_task_used_altivec@l(r4)
799#endif /* CONFIG_SMP */
800 blr
801#endif /* CONFIG_ALTIVEC */
802
803/*
804 * This code is jumped to from the startup code to copy
805 * the kernel image to physical address 0.
806 */
807relocate_kernel:
808 addis r9,r26,klimit@ha /* fetch klimit */
809 lwz r25,klimit@l(r9)
810 addis r25,r25,-KERNELBASE@h
811 li r3,0 /* Destination base address */
812 li r6,0 /* Destination offset */
813 li r5,0x4000 /* # bytes of memory to copy */
814 bl copy_and_flush /* copy the first 0x4000 bytes */
815 addi r0,r3,4f@l /* jump to the address of 4f */
816 mtctr r0 /* in copy and do the rest. */
817 bctr /* jump to the copy */
8184: mr r5,r25
819 bl copy_and_flush /* copy the rest */
820 b turn_on_mmu
821
822/*
823 * Copy routine used to copy the kernel to start at physical address 0
824 * and flush and invalidate the caches as needed.
825 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
826 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
827 */
748a7683 828_ENTRY(copy_and_flush)
14cf11af
PM		 829 addi r5,r5,-4
830 addi r6,r6,-4
7dffb720 8314: li r0,L1_CACHE_BYTES/4
14cf11af
PM		 832 mtctr r0
8333: addi r6,r6,4 /* copy a cache line */
834 lwzx r0,r6,r4
835 stwx r0,r6,r3
836 bdnz 3b
837 dcbst r6,r3 /* write it to memory */
838 sync
839 icbi r6,r3 /* flush the icache line */
840 cmplw 0,r6,r5
841 blt 4b
842 sync /* additional sync needed on g4 */
843 isync
844 addi r5,r5,4
845 addi r6,r6,4
846 blr
847
14cf11af
PM		 848#ifdef CONFIG_SMP
849#ifdef CONFIG_GEMINI
850 .globl __secondary_start_gemini
851__secondary_start_gemini:
852 mfspr r4,SPRN_HID0
853 ori r4,r4,HID0_ICFI
854 li r3,0
855 ori r3,r3,HID0_ICE
856 andc r4,r4,r3
857 mtspr SPRN_HID0,r4
858 sync
859 b __secondary_start
860#endif /* CONFIG_GEMINI */
861
ee0339f2
JL		 862 .globl __secondary_start_mpc86xx
863__secondary_start_mpc86xx:
864 mfspr r3, SPRN_PIR
865 stw r3, __secondary_hold_acknowledge@l(0)
866 mr r24, r3 /* cpu # */
867 b __secondary_start
868
14cf11af
PM		 869 .globl __secondary_start_pmac_0
870__secondary_start_pmac_0:
871 /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */
872 li r24,0
873 b 1f
874 li r24,1
875 b 1f
876 li r24,2
877 b 1f
878 li r24,3
8791:
880 /* on powersurge, we come in here with IR=0 and DR=1, and DBAT 0
881 set to map the 0xf0000000 - 0xffffffff region */
882 mfmsr r0
883 rlwinm r0,r0,0,28,26 /* clear DR (0x10) */
884 SYNC
885 mtmsr r0
886 isync
887
888 .globl __secondary_start
889__secondary_start:
14cf11af
PM		 890 /* Copy some CPU settings from CPU 0 */
891 bl __restore_cpu_setup
892
893 lis r3,-KERNELBASE@h
894 mr r4,r24
14cf11af
PM		 895 bl call_setup_cpu /* Call setup_cpu for this CPU */
896#ifdef CONFIG_6xx
897 lis r3,-KERNELBASE@h
898 bl init_idle_6xx
899#endif /* CONFIG_6xx */
14cf11af
PM		 900
901 /* get current_thread_info and current */
902 lis r1,secondary_ti@ha
903 tophys(r1,r1)
904 lwz r1,secondary_ti@l(r1)
905 tophys(r2,r1)
906 lwz r2,TI_TASK(r2)
907
908 /* stack */
909 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
910 li r0,0
911 tophys(r3,r1)
912 stw r0,0(r3)
913
914 /* load up the MMU */
915 bl load_up_mmu
916
917 /* ptr to phys current thread */
918 tophys(r4,r2)
919 addi r4,r4,THREAD /* phys address of our thread_struct */
920 CLR_TOP32(r4)
921 mtspr SPRN_SPRG3,r4
922 li r3,0
923 mtspr SPRN_SPRG2,r3 /* 0 => not in RTAS */
924
925 /* enable MMU and jump to start_secondary */
926 li r4,MSR_KERNEL
927 FIX_SRR1(r4,r5)
928 lis r3,start_secondary@h
929 ori r3,r3,start_secondary@l
930 mtspr SPRN_SRR0,r3
931 mtspr SPRN_SRR1,r4
932 SYNC
933 RFI
934#endif /* CONFIG_SMP */
935
936/*
937 * Those generic dummy functions are kept for CPUs not
938 * included in CONFIG_6xx
939 */
187a0067 940#if !defined(CONFIG_6xx)
748a7683 941_ENTRY(__save_cpu_setup)
14cf11af 942 blr
748a7683 943_ENTRY(__restore_cpu_setup)
14cf11af 944 blr
187a0067 945#endif /* !defined(CONFIG_6xx) */
14cf11af
PM		 946
947
948/*
949 * Load stuff into the MMU. Intended to be called with
950 * IR=0 and DR=0.
951 */
952load_up_mmu:
953 sync /* Force all PTE updates to finish */
954 isync
955 tlbia /* Clear all TLB entries */
956 sync /* wait for tlbia/tlbie to finish */
957 TLBSYNC /* ... on all CPUs */
958 /* Load the SDR1 register (hash table base & size) */
959 lis r6,_SDR1@ha
960 tophys(r6,r6)
961 lwz r6,_SDR1@l(r6)
962 mtspr SPRN_SDR1,r6
14cf11af
PM		 963 li r0,16 /* load up segment register values */
964 mtctr r0 /* for context 0 */
965 lis r3,0x2000 /* Ku = 1, VSID = 0 */
966 li r4,0
9673: mtsrin r3,r4
968 addi r3,r3,0x111 /* increment VSID */
969 addis r4,r4,0x1000 /* address of next segment */
970 bdnz 3b
187a0067 971
14cf11af
PM		 972/* Load the BAT registers with the values set up by MMU_init.
973 MMU_init takes care of whether we're on a 601 or not. */
974 mfpvr r3
975 srwi r3,r3,16
976 cmpwi r3,1
977 lis r3,BATS@ha
978 addi r3,r3,BATS@l
979 tophys(r3,r3)
980 LOAD_BAT(0,r3,r4,r5)
981 LOAD_BAT(1,r3,r4,r5)
982 LOAD_BAT(2,r3,r4,r5)
983 LOAD_BAT(3,r3,r4,r5)
ee0339f2
JL		 984BEGIN_FTR_SECTION
985 LOAD_BAT(4,r3,r4,r5)
986 LOAD_BAT(5,r3,r4,r5)
987 LOAD_BAT(6,r3,r4,r5)
988 LOAD_BAT(7,r3,r4,r5)
989END_FTR_SECTION_IFSET(CPU_FTR_HAS_HIGH_BATS)
14cf11af
PM		 990 blr
991
992/*
993 * This is where the main kernel code starts.
994 */
995start_here:
996 /* ptr to current */
997 lis r2,init_task@h
998 ori r2,r2,init_task@l
999 /* Set up for using our exception vectors */
1000 /* ptr to phys current thread */
1001 tophys(r4,r2)
1002 addi r4,r4,THREAD /* init task's THREAD */
1003 CLR_TOP32(r4)
1004 mtspr SPRN_SPRG3,r4
1005 li r3,0
1006 mtspr SPRN_SPRG2,r3 /* 0 => not in RTAS */
1007
1008 /* stack */
1009 lis r1,init_thread_union@ha
1010 addi r1,r1,init_thread_union@l
1011 li r0,0
1012 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
1013/*
187a0067 1014 * Do early platform-specific initialization,
14cf11af
PM		 1015 * and set up the MMU.
1016 */
1017 mr r3,r31
1018 mr r4,r30
14cf11af 1019 bl machine_init
22c841c9 1020 bl __save_cpu_setup
14cf11af
PM		 1021 bl MMU_init
1022
14cf11af
PM		 1023/*
1024 * Go back to running unmapped so we can load up new values
1025 * for SDR1 (hash table pointer) and the segment registers
1026 * and change to using our exception vectors.
1027 */
1028 lis r4,2f@h
1029 ori r4,r4,2f@l
1030 tophys(r4,r4)
1031 li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR)
1032 FIX_SRR1(r3,r5)
1033 mtspr SPRN_SRR0,r4
1034 mtspr SPRN_SRR1,r3
1035 SYNC
1036 RFI
1037/* Load up the kernel context */
10382: bl load_up_mmu
1039
1040#ifdef CONFIG_BDI_SWITCH
1041 /* Add helper information for the Abatron bdiGDB debugger.
1042 * We do this here because we know the mmu is disabled, and
1043 * will be enabled for real in just a few instructions.
1044 */
1045 lis r5, abatron_pteptrs@h
1046 ori r5, r5, abatron_pteptrs@l
1047 stw r5, 0xf0(r0) /* This much match your Abatron config */
1048 lis r6, swapper_pg_dir@h
1049 ori r6, r6, swapper_pg_dir@l
1050 tophys(r5, r5)
1051 stw r6, 0(r5)
1052#endif /* CONFIG_BDI_SWITCH */
1053
1054/* Now turn on the MMU for real! */
1055 li r4,MSR_KERNEL
1056 FIX_SRR1(r4,r5)
1057 lis r3,start_kernel@h
1058 ori r3,r3,start_kernel@l
1059 mtspr SPRN_SRR0,r3
1060 mtspr SPRN_SRR1,r4
1061 SYNC
1062 RFI
1063
1064/*
1065 * Set up the segment registers for a new context.
1066 */
748a7683 1067_ENTRY(set_context)
14cf11af
PM		 1068 mulli r3,r3,897 /* multiply context by skew factor */
1069 rlwinm r3,r3,4,8,27 /* VSID = (context & 0xfffff) << 4 */
1070 addis r3,r3,0x6000 /* Set Ks, Ku bits */
1071 li r0,NUM_USER_SEGMENTS
1072 mtctr r0
1073
1074#ifdef CONFIG_BDI_SWITCH
1075 /* Context switch the PTE pointer for the Abatron BDI2000.
1076 * The PGDIR is passed as second argument.
1077 */
1078 lis r5, KERNELBASE@h
1079 lwz r5, 0xf0(r5)
1080 stw r4, 0x4(r5)
1081#endif
1082 li r4,0
1083 isync
10843:
14cf11af
PM		 1085 mtsrin r3,r4
1086 addi r3,r3,0x111 /* next VSID */
1087 rlwinm r3,r3,0,8,3 /* clear out any overflow from VSID field */
1088 addis r4,r4,0x1000 /* address of next segment */
1089 bdnz 3b
1090 sync
1091 isync
1092 blr
1093
1094/*
1095 * An undocumented "feature" of 604e requires that the v bit
1096 * be cleared before changing BAT values.
1097 *
1098 * Also, newer IBM firmware does not clear bat3 and 4 so
1099 * this makes sure it's done.
1100 * -- Cort
1101 */
1102clear_bats:
1103 li r10,0
1104 mfspr r9,SPRN_PVR
1105 rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */
1106 cmpwi r9, 1
1107 beq 1f
1108
1109 mtspr SPRN_DBAT0U,r10
1110 mtspr SPRN_DBAT0L,r10
1111 mtspr SPRN_DBAT1U,r10
1112 mtspr SPRN_DBAT1L,r10
1113 mtspr SPRN_DBAT2U,r10
1114 mtspr SPRN_DBAT2L,r10
1115 mtspr SPRN_DBAT3U,r10
1116 mtspr SPRN_DBAT3L,r10
11171:
1118 mtspr SPRN_IBAT0U,r10
1119 mtspr SPRN_IBAT0L,r10
1120 mtspr SPRN_IBAT1U,r10
1121 mtspr SPRN_IBAT1L,r10
1122 mtspr SPRN_IBAT2U,r10
1123 mtspr SPRN_IBAT2L,r10
1124 mtspr SPRN_IBAT3U,r10
1125 mtspr SPRN_IBAT3L,r10
1126BEGIN_FTR_SECTION
1127 /* Here's a tweak: at this point, CPU setup have
1128 * not been called yet, so HIGH_BAT_EN may not be
1129 * set in HID0 for the 745x processors. However, it
1130 * seems that doesn't affect our ability to actually
1131 * write to these SPRs.
1132 */
1133 mtspr SPRN_DBAT4U,r10
1134 mtspr SPRN_DBAT4L,r10
1135 mtspr SPRN_DBAT5U,r10
1136 mtspr SPRN_DBAT5L,r10
1137 mtspr SPRN_DBAT6U,r10
1138 mtspr SPRN_DBAT6L,r10
1139 mtspr SPRN_DBAT7U,r10
1140 mtspr SPRN_DBAT7L,r10
1141 mtspr SPRN_IBAT4U,r10
1142 mtspr SPRN_IBAT4L,r10
1143 mtspr SPRN_IBAT5U,r10
1144 mtspr SPRN_IBAT5L,r10
1145 mtspr SPRN_IBAT6U,r10
1146 mtspr SPRN_IBAT6L,r10
1147 mtspr SPRN_IBAT7U,r10
1148 mtspr SPRN_IBAT7L,r10
1149END_FTR_SECTION_IFSET(CPU_FTR_HAS_HIGH_BATS)
1150 blr
1151
1152flush_tlbs:
1153 lis r10, 0x40
11541: addic. r10, r10, -0x1000
1155 tlbie r10
1156 blt 1b
1157 sync
1158 blr
1159
1160mmu_off:
1161 addi r4, r3, __after_mmu_off - _start
1162 mfmsr r3
1163 andi. r0,r3,MSR_DR|MSR_IR /* MMU enabled? */
1164 beqlr
1165 andc r3,r3,r0
1166 mtspr SPRN_SRR0,r4
1167 mtspr SPRN_SRR1,r3
1168 sync
1169 RFI
1170
14cf11af
PM		 1171/*
1172 * Use the first pair of BAT registers to map the 1st 16MB
1173 * of RAM to KERNELBASE. From this point on we can't safely
1174 * call OF any more.
1175 */
1176initial_bats:
1177 lis r11,KERNELBASE@h
14cf11af
PM		 1178 mfspr r9,SPRN_PVR
1179 rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */
1180 cmpwi 0,r9,1
1181 bne 4f
1182 ori r11,r11,4 /* set up BAT registers for 601 */
1183 li r8,0x7f /* valid, block length = 8MB */
1184 oris r9,r11,0x800000@h /* set up BAT reg for 2nd 8M */
1185 oris r10,r8,0x800000@h /* set up BAT reg for 2nd 8M */
1186 mtspr SPRN_IBAT0U,r11 /* N.B. 601 has valid bit in */
1187 mtspr SPRN_IBAT0L,r8 /* lower BAT register */
1188 mtspr SPRN_IBAT1U,r9
1189 mtspr SPRN_IBAT1L,r10
1190 isync
1191 blr
14cf11af
PM		 1192
11934: tophys(r8,r11)
1194#ifdef CONFIG_SMP
1195 ori r8,r8,0x12 /* R/W access, M=1 */
1196#else
1197 ori r8,r8,2 /* R/W access */
1198#endif /* CONFIG_SMP */
14cf11af 1199 ori r11,r11,BL_256M<<2|0x2 /* set up BAT registers for 604 */
14cf11af 1200
14cf11af
PM		 1201 mtspr SPRN_DBAT0L,r8 /* N.B. 6xx (not 601) have valid */
1202 mtspr SPRN_DBAT0U,r11 /* bit in upper BAT register */
1203 mtspr SPRN_IBAT0L,r8
1204 mtspr SPRN_IBAT0U,r11
1205 isync
1206 blr
1207
14cf11af 1208
f21f49ea 1209#ifdef CONFIG_BOOTX_TEXT
51d3082f
BH		 1210setup_disp_bat:
1211 /*
1212 * setup the display bat prepared for us in prom.c
1213 */
1214 mflr r8
1215 bl reloc_offset
1216 mtlr r8
1217 addis r8,r3,disp_BAT@ha
1218 addi r8,r8,disp_BAT@l
1219 cmpwi cr0,r8,0
1220 beqlr
1221 lwz r11,0(r8)
1222 lwz r8,4(r8)
1223 mfspr r9,SPRN_PVR
1224 rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */
1225 cmpwi 0,r9,1
1226 beq 1f
1227 mtspr SPRN_DBAT3L,r8
1228 mtspr SPRN_DBAT3U,r11
1229 blr
12301: mtspr SPRN_IBAT3L,r8
1231 mtspr SPRN_IBAT3U,r11
1232 blr
f21f49ea 1233#endif /* CONFIG_BOOTX_TEXT */
51d3082f 1234
c374e00e
SW		 1235#ifdef CONFIG_PPC_EARLY_DEBUG_CPM
1236setup_cpm_bat:
1237 lis r8, 0xf000
1238 ori r8, r8, 0x002a
1239 mtspr SPRN_DBAT1L, r8
1240
1241 lis r11, 0xf000
1242 ori r11, r11, (BL_1M << 2) | 2
1243 mtspr SPRN_DBAT1U, r11
1244
1245 blr
1246#endif
1247
14cf11af
PM		 1248#ifdef CONFIG_8260
1249/* Jump into the system reset for the rom.
1250 * We first disable the MMU, and then jump to the ROM reset address.
1251 *
1252 * r3 is the board info structure, r4 is the location for starting.
1253 * I use this for building a small kernel that can load other kernels,
1254 * rather than trying to write or rely on a rom monitor that can tftp load.
1255 */
1256 .globl m8260_gorom
1257m8260_gorom:
1258 mfmsr r0
1259 rlwinm r0,r0,0,17,15 /* clear MSR_EE in r0 */
1260 sync
1261 mtmsr r0
1262 sync
1263 mfspr r11, SPRN_HID0
1264 lis r10, 0
1265 ori r10,r10,HID0_ICE|HID0_DCE
1266 andc r11, r11, r10
1267 mtspr SPRN_HID0, r11
1268 isync
1269 li r5, MSR_ME|MSR_RI
1270 lis r6,2f@h
1271 addis r6,r6,-KERNELBASE@h
1272 ori r6,r6,2f@l
1273 mtspr SPRN_SRR0,r6
1274 mtspr SPRN_SRR1,r5
1275 isync
1276 sync
1277 rfi
12782:
1279 mtlr r4
1280 blr
1281#endif
1282
1283
1284/*
1285 * We put a few things here that have to be page-aligned.
1286 * This stuff goes at the beginning of the data segment,
1287 * which is page-aligned.
1288 */
1289 .data
1290 .globl sdata
1291sdata:
1292 .globl empty_zero_page
1293empty_zero_page:
1294 .space 4096
1295
1296 .globl swapper_pg_dir
1297swapper_pg_dir:
bee86f14 1298 .space PGD_TABLE_SIZE
14cf11af 1299
14cf11af
PM		 1300 .globl intercept_table
1301intercept_table:
1302 .long 0, 0, i0x200, i0x300, i0x400, 0, i0x600, i0x700
1303 .long i0x800, 0, 0, 0, 0, i0xd00, 0, 0
1304 .long 0, 0, 0, i0x1300, 0, 0, 0, 0
1305 .long 0, 0, 0, 0, 0, 0, 0, 0
1306 .long 0, 0, 0, 0, 0, 0, 0, 0
1307 .long 0, 0, 0, 0, 0, 0, 0, 0
1308
1309/* Room for two PTE pointers, usually the kernel and current user pointers
1310 * to their respective root page table.
1311 */
1312abatron_pteptrs:
1313 .space 8
kernel source for telekom puls (alcatel/mediatek)