projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
| Commit | Line | Data |
|---|---|---|
| 24cc67de BH |
1 | /* |
| 2 | * This file contains low level CPU setup functions. | |
| 3 | * Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org) | |
| 4 | * | |
| 5 | * This program is free software; you can redistribute it and/or | |
| 6 | * modify it under the terms of the GNU General Public License | |
| 7 | * as published by the Free Software Foundation; either version | |
| 8 | * 2 of the License, or (at your option) any later version. | |
| 9 | * | |
| 10 | */ | |
| 11 | ||
| 12 | #include <asm/processor.h> | |
| 13 | #include <asm/page.h> | |
| 14 | #include <asm/cputable.h> | |
| 15 | #include <asm/ppc_asm.h> | |
| 16 | #include <asm/asm-offsets.h> | |
| 17 | #include <asm/cache.h> | |
| 18 | ||
| 19 | /* Entry: r3 = crap, r4 = ptr to cputable entry | |
| 20 | * | |
| 21 | * Note that we can be called twice for pseudo-PVRs | |
| 22 | */ | |
| 23 | _GLOBAL(__setup_cpu_power7) | |
| 24 | mflr r11 | |
| 25 | bl __init_hvmode_206 | |
| 26 | mtlr r11 | |
| 27 | beqlr | |
| b144871c BH |
28 | li r0,0 |
| 29 | mtspr SPRN_LPID,r0 | |
| f7c32c24 | 30 | mfspr r3,SPRN_LPCR |
| 24cc67de | 31 | bl __init_LPCR |
| b144871c | 32 | bl __init_TLB |
| 24cc67de BH |
33 | mtlr r11 |
| 34 | blr | |
| 35 | ||
| 36 | _GLOBAL(__restore_cpu_power7) | |
| 37 | mflr r11 | |
| 38 | mfmsr r3 | |
| 39 | rldicl. r0,r3,4,63 | |
| 40 | beqlr | |
| b144871c BH |
41 | li r0,0 |
| 42 | mtspr SPRN_LPID,r0 | |
| f7c32c24 | 43 | mfspr r3,SPRN_LPCR |
| 24cc67de | 44 | bl __init_LPCR |
| aec937b1 MN |
45 | bl __init_TLB |
| 46 | mtlr r11 | |
| 47 | blr | |
| 48 | ||
| 49 | _GLOBAL(__setup_cpu_power8) | |
| 50 | mflr r11 | |
| 57d23167 | 51 | bl __init_FSCR |
| 240686c1 | 52 | bl __init_PMU |
| aec937b1 MN |
53 | bl __init_hvmode_206 |
| 54 | mtlr r11 | |
| 55 | beqlr | |
| 56 | li r0,0 | |
| 57 | mtspr SPRN_LPID,r0 | |
| f7c32c24 | 58 | mfspr r3,SPRN_LPCR |
| b0302722 | 59 | oris r3, r3, LPCR_AIL_3@h |
| aec937b1 | 60 | bl __init_LPCR |
| 2a3563b0 | 61 | bl __init_HFSCR |
| aec937b1 | 62 | bl __init_TLB |
| 240686c1 | 63 | bl __init_PMU_HV |
| aec937b1 MN |
64 | mtlr r11 |
| 65 | blr | |
| 66 | ||
| 67 | _GLOBAL(__restore_cpu_power8) | |
| 68 | mflr r11 | |
| 57d23167 | 69 | bl __init_FSCR |
| 240686c1 | 70 | bl __init_PMU |
| aec937b1 MN |
71 | mfmsr r3 |
| 72 | rldicl. r0,r3,4,63 | |
| 8c2a3817 | 73 | mtlr r11 |
| aec937b1 MN |
74 | beqlr |
| 75 | li r0,0 | |
| 76 | mtspr SPRN_LPID,r0 | |
| f7c32c24 | 77 | mfspr r3,SPRN_LPCR |
| b0302722 | 78 | oris r3, r3, LPCR_AIL_3@h |
| aec937b1 | 79 | bl __init_LPCR |
| 2a3563b0 | 80 | bl __init_HFSCR |
| b144871c | 81 | bl __init_TLB |
| 240686c1 | 82 | bl __init_PMU_HV |
| 24cc67de BH |
83 | mtlr r11 |
| 84 | blr | |
| 85 | ||
| 86 | __init_hvmode_206: | |
| 969391c5 | 87 | /* Disable CPU_FTR_HVMODE and exit if MSR:HV is not set */ |
| 24cc67de BH |
88 | mfmsr r3 |
| 89 | rldicl. r0,r3,4,63 | |
| 90 | bnelr | |
| 91 | ld r5,CPU_SPEC_FEATURES(r4) | |
| 969391c5 | 92 | LOAD_REG_IMMEDIATE(r6,CPU_FTR_HVMODE) |
| 24cc67de BH |
93 | xor r5,r5,r6 |
| 94 | std r5,CPU_SPEC_FEATURES(r4) | |
| 95 | blr | |
| 96 | ||
| 97 | __init_LPCR: | |
| 98 | /* Setup a sane LPCR: | |
| f7c32c24 | 99 | * Called with initial LPCR in R3 |
| 24cc67de | 100 | * |
| a5d4f3ad | 101 | * LPES = 0b01 (HSRR0/1 used for 0x500) |
| 24cc67de | 102 | * PECE = 0b111 |
| 895796a8 | 103 | * DPFD = 4 |
| 923c53ca PM |
104 | * HDICE = 0 |
| 105 | * VC = 0b100 (VPM0=1, VPM1=0, ISL=0) | |
| 106 | * VRMASD = 0b10000 (L=1, LP=00) | |
| 24cc67de BH |
107 | * |
| 108 | * Other bits untouched for now | |
| 109 | */ | |
| 923c53ca PM |
110 | li r5,1 |
| 111 | rldimi r3,r5, LPCR_LPES_SH, 64-LPCR_LPES_SH-2 | |
| 24cc67de | 112 | ori r3,r3,(LPCR_PECE0|LPCR_PECE1|LPCR_PECE2) |
| 895796a8 | 113 | li r5,4 |
| 923c53ca PM |
114 | rldimi r3,r5, LPCR_DPFD_SH, 64-LPCR_DPFD_SH-3 |
| 115 | clrrdi r3,r3,1 /* clear HDICE */ | |
| 116 | li r5,4 | |
| 117 | rldimi r3,r5, LPCR_VC_SH, 0 | |
| 118 | li r5,0x10 | |
| 119 | rldimi r3,r5, LPCR_VRMASD_SH, 64-LPCR_VRMASD_SH-5 | |
| 24cc67de BH |
120 | mtspr SPRN_LPCR,r3 |
| 121 | isync | |
| 122 | blr | |
| b144871c | 123 | |
| 2468dcf6 IM |
124 | __init_FSCR: |
| 125 | mfspr r3,SPRN_FSCR | |
| 1ddf499e | 126 | ori r3,r3,FSCR_TAR|FSCR_DSCR|FSCR_EBB |
| 2468dcf6 IM |
127 | mtspr SPRN_FSCR,r3 |
| 128 | blr | |
| 129 | ||
| 2a3563b0 MN |
130 | __init_HFSCR: |
| 131 | mfspr r3,SPRN_HFSCR | |
| 53b56ca0 | 132 | ori r3,r3,HFSCR_TAR|HFSCR_TM|HFSCR_BHRB|HFSCR_PM|\ |
| 1ddf499e | 133 | HFSCR_DSCR|HFSCR_VECVSX|HFSCR_FP|HFSCR_EBB |
| 2a3563b0 MN |
134 | mtspr SPRN_HFSCR,r3 |
| 135 | blr | |
| 136 | ||
| b144871c | 137 | __init_TLB: |
| 8fc1f5d7 BH |
138 | /* |
| 139 | * Clear the TLB using the "IS 3" form of tlbiel instruction | |
| 140 | * (invalidate by congruence class). P7 has 128 CCs, P8 has 512 | |
| 141 | * so we just always do 512 | |
| 142 | */ | |
| 143 | li r6,512 | |
| b144871c BH |
144 | mtctr r6 |
| 145 | li r7,0xc00 /* IS field = 0b11 */ | |
| 146 | ptesync | |
| 147 | 2: tlbiel r7 | |
| 148 | addi r7,r7,0x1000 | |
| 149 | bdnz 2b | |
| 150 | ptesync | |
| 151 | 1: blr | |
| 240686c1 ME |
152 | |
| 153 | __init_PMU_HV: | |
| 154 | li r5,0 | |
| 155 | mtspr SPRN_MMCRC,r5 | |
| 156 | mtspr SPRN_MMCRH,r5 | |
| 157 | blr | |
| 158 | ||
| 159 | __init_PMU: | |
| 160 | li r5,0 | |
| 161 | mtspr SPRN_MMCRS,r5 | |
| 162 | mtspr SPRN_MMCRA,r5 | |
| 163 | mtspr SPRN_MMCR0,r5 | |
| 164 | mtspr SPRN_MMCR1,r5 | |
| 165 | mtspr SPRN_MMCR2,r5 | |
| 166 | blr |