[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / powerpc / include / asm / pgtable-ppc32.h

#ifndef _ASM_POWERPC_PGTABLE_PPC32_H
#define _ASM_POWERPC_PGTABLE_PPC32_H

#include <asm-generic/pgtable-nopmd.h>

#ifndef __ASSEMBLY__
#include <linux/sched.h>
#include <linux/threads.h>
#include <asm/io.h>			/* For sub-arch specific PPC_PIN_SIZE */

extern unsigned long va_to_phys(unsigned long address);
extern pte_t *va_to_pte(unsigned long address);
extern unsigned long ioremap_bot;

#ifdef CONFIG_44x
extern int icache_44x_need_flush;
#endif

#endif /* __ASSEMBLY__ */

/*
 * The normal case is that PTEs are 32-bits and we have a 1-page
 * 1024-entry pgdir pointing to 1-page 1024-entry PTE pages.  -- paulus
 *
 * For any >32-bit physical address platform, we can use the following
 * two level page table layout where the pgdir is 8KB and the MS 13 bits
 * are an index to the second level table.  The combined pgdir/pmd first
 * level has 2048 entries and the second level has 512 64-bit PTE entries.
 * -Matt
 */
/* PGDIR_SHIFT determines what a top-level page table entry can map */
#define PGDIR_SHIFT	(PAGE_SHIFT + PTE_SHIFT)
#define PGDIR_SIZE	(1UL << PGDIR_SHIFT)
#define PGDIR_MASK	(~(PGDIR_SIZE-1))

/*
 * entries per page directory level: our page-table tree is two-level, so
 * we don't really have any PMD directory.
 */
#ifndef __ASSEMBLY__
#define PTE_TABLE_SIZE	(sizeof(pte_t) << PTE_SHIFT)
#define PGD_TABLE_SIZE	(sizeof(pgd_t) << (32 - PGDIR_SHIFT))
#endif	/* __ASSEMBLY__ */

#define PTRS_PER_PTE	(1 << PTE_SHIFT)
#define PTRS_PER_PMD	1
#define PTRS_PER_PGD	(1 << (32 - PGDIR_SHIFT))

#define USER_PTRS_PER_PGD	(TASK_SIZE / PGDIR_SIZE)
#define FIRST_USER_ADDRESS	0

#define pte_ERROR(e) \
	printk("%s:%d: bad pte %llx.\n", __FILE__, __LINE__, \
		(unsigned long long)pte_val(e))
#define pgd_ERROR(e) \
	printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))

/*
 * This is the bottom of the PKMAP area with HIGHMEM or an arbitrary
 * value (for now) on others, from where we can start layout kernel
 * virtual space that goes below PKMAP and FIXMAP
 */
#ifdef CONFIG_HIGHMEM
#define KVIRT_TOP	PKMAP_BASE
#else
#define KVIRT_TOP	(0xfe000000UL)	/* for now, could be FIXMAP_BASE ? */
#endif

/*
 * ioremap_bot starts at that address. Early ioremaps move down from there,
 * until mem_init() at which point this becomes the top of the vmalloc
 * and ioremap space
 */
#ifdef CONFIG_NOT_COHERENT_CACHE
#define IOREMAP_TOP	((KVIRT_TOP - CONFIG_CONSISTENT_SIZE) & PAGE_MASK)
#else
#define IOREMAP_TOP	KVIRT_TOP
#endif

/*
 * Just any arbitrary offset to the start of the vmalloc VM area: the
 * current 16MB value just means that there will be a 64MB "hole" after the
 * physical memory until the kernel virtual memory starts.  That means that
 * any out-of-bounds memory accesses will hopefully be caught.
 * The vmalloc() routines leaves a hole of 4kB between each vmalloced
 * area for the same reason. ;)
 *
 * We no longer map larger than phys RAM with the BATs so we don't have
 * to worry about the VMALLOC_OFFSET causing problems.  We do have to worry
 * about clashes between our early calls to ioremap() that start growing down
 * from ioremap_base being run into the VM area allocations (growing upwards
 * from VMALLOC_START).  For this reason we have ioremap_bot to check when
 * we actually run into our mappings setup in the early boot with the VM
 * system.  This really does become a problem for machines with good amounts
 * of RAM.  -- Cort
 */
#define VMALLOC_OFFSET (0x1000000) /* 16M */
#ifdef PPC_PIN_SIZE
#define VMALLOC_START (((_ALIGN((long)high_memory, PPC_PIN_SIZE) + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
#else
#define VMALLOC_START ((((long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
#endif
#define VMALLOC_END	ioremap_bot

/*
 * Bits in a linux-style PTE.  These match the bits in the
 * (hardware-defined) PowerPC PTE as closely as possible.
 */

#if defined(CONFIG_40x)
#include <asm/pte-40x.h>
#elif defined(CONFIG_44x)
#include <asm/pte-44x.h>
#elif defined(CONFIG_FSL_BOOKE) && defined(CONFIG_PTE_64BIT)
#include <asm/pte-book3e.h>
#elif defined(CONFIG_FSL_BOOKE)
#include <asm/pte-fsl-booke.h>
#elif defined(CONFIG_8xx)
#include <asm/pte-8xx.h>
#else /* CONFIG_6xx */
#include <asm/pte-hash32.h>
#endif

/* And here we include common definitions */
#include <asm/pte-common.h>

#ifndef __ASSEMBLY__

#define pte_clear(mm, addr, ptep) \
	do { pte_update(ptep, ~_PAGE_HASHPTE, 0); } while (0)

#define pmd_none(pmd)		(!pmd_val(pmd))
#define	pmd_bad(pmd)		(pmd_val(pmd) & _PMD_BAD)
#define	pmd_present(pmd)	(pmd_val(pmd) & _PMD_PRESENT_MASK)
#define	pmd_clear(pmdp)		do { pmd_val(*(pmdp)) = 0; } while (0)

/*
 * When flushing the tlb entry for a page, we also need to flush the hash
 * table entry.  flush_hash_pages is assembler (for speed) in hashtable.S.
 */
extern int flush_hash_pages(unsigned context, unsigned long va,
			    unsigned long pmdval, int count);

/* Add an HPTE to the hash table */
extern void add_hash_page(unsigned context, unsigned long va,
			  unsigned long pmdval);

/* Flush an entry from the TLB/hash table */
extern void flush_hash_entry(struct mm_struct *mm, pte_t *ptep,
			     unsigned long address);

/*
 * PTE updates. This function is called whenever an existing
 * valid PTE is updated. This does -not- include set_pte_at()
 * which nowadays only sets a new PTE.
 *
 * Depending on the type of MMU, we may need to use atomic updates
 * and the PTE may be either 32 or 64 bit wide. In the later case,
 * when using atomic updates, only the low part of the PTE is
 * accessed atomically.
 *
 * In addition, on 44x, we also maintain a global flag indicating
 * that an executable user mapping was modified, which is needed
 * to properly flush the virtually tagged instruction cache of
 * those implementations.
 */
#ifndef CONFIG_PTE_64BIT
static inline unsigned long pte_update(pte_t *p,
				       unsigned long clr,
				       unsigned long set)
{
#ifdef PTE_ATOMIC_UPDATES
	unsigned long old, tmp;

	__asm__ __volatile__("\
1:	lwarx	%0,0,%3\n\
	andc	%1,%0,%4\n\
	or	%1,%1,%5\n"
	PPC405_ERR77(0,%3)
"	stwcx.	%1,0,%3\n\
	bne-	1b"
	: "=&r" (old), "=&r" (tmp), "=m" (*p)
	: "r" (p), "r" (clr), "r" (set), "m" (*p)
	: "cc" );
#else /* PTE_ATOMIC_UPDATES */
	unsigned long old = pte_val(*p);
	*p = __pte((old & ~clr) | set);
#endif /* !PTE_ATOMIC_UPDATES */

#ifdef CONFIG_44x
	if ((old & _PAGE_USER) && (old & _PAGE_EXEC))
		icache_44x_need_flush = 1;
#endif
	return old;
}
#else /* CONFIG_PTE_64BIT */
static inline unsigned long long pte_update(pte_t *p,
					    unsigned long clr,
					    unsigned long set)
{
#ifdef PTE_ATOMIC_UPDATES
	unsigned long long old;
	unsigned long tmp;

	__asm__ __volatile__("\
1:	lwarx	%L0,0,%4\n\
	lwzx	%0,0,%3\n\
	andc	%1,%L0,%5\n\
	or	%1,%1,%6\n"
	PPC405_ERR77(0,%3)
"	stwcx.	%1,0,%4\n\
	bne-	1b"
	: "=&r" (old), "=&r" (tmp), "=m" (*p)
	: "r" (p), "r" ((unsigned long)(p) + 4), "r" (clr), "r" (set), "m" (*p)
	: "cc" );
#else /* PTE_ATOMIC_UPDATES */
	unsigned long long old = pte_val(*p);
	*p = __pte((old & ~(unsigned long long)clr) | set);
#endif /* !PTE_ATOMIC_UPDATES */

#ifdef CONFIG_44x
	if ((old & _PAGE_USER) && (old & _PAGE_EXEC))
		icache_44x_need_flush = 1;
#endif
	return old;
}
#endif /* CONFIG_PTE_64BIT */

/*
 * 2.6 calls this without flushing the TLB entry; this is wrong
 * for our hash-based implementation, we fix that up here.
 */
#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
static inline int __ptep_test_and_clear_young(unsigned int context, unsigned long addr, pte_t *ptep)
{
	unsigned long old;
	old = pte_update(ptep, _PAGE_ACCESSED, 0);
#if _PAGE_HASHPTE != 0
	if (old & _PAGE_HASHPTE) {
		unsigned long ptephys = __pa(ptep) & PAGE_MASK;
		flush_hash_pages(context, addr, ptephys, 1);
	}
#endif
	return (old & _PAGE_ACCESSED) != 0;
}
#define ptep_test_and_clear_young(__vma, __addr, __ptep) \
	__ptep_test_and_clear_young((__vma)->vm_mm->context.id, __addr, __ptep)

#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr,
				       pte_t *ptep)
{
	return __pte(pte_update(ptep, ~_PAGE_HASHPTE, 0));
}

#define __HAVE_ARCH_PTEP_SET_WRPROTECT
static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
				      pte_t *ptep)
{
	pte_update(ptep, (_PAGE_RW | _PAGE_HWWRITE), 0);
}
static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
					   unsigned long addr, pte_t *ptep)
{
	ptep_set_wrprotect(mm, addr, ptep);
}


static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry)
{
	unsigned long bits = pte_val(entry) &
		(_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW | _PAGE_EXEC);
	pte_update(ptep, 0, bits);
}

#define __HAVE_ARCH_PTE_SAME
#define pte_same(A,B)	(((pte_val(A) ^ pte_val(B)) & ~_PAGE_HASHPTE) == 0)

/*
 * Note that on Book E processors, the pmd contains the kernel virtual
 * (lowmem) address of the pte page.  The physical address is less useful
 * because everything runs with translation enabled (even the TLB miss
 * handler).  On everything else the pmd contains the physical address
 * of the pte page.  -- paulus
 */
#ifndef CONFIG_BOOKE
#define pmd_page_vaddr(pmd)	\
	((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
#define pmd_page(pmd)		\
	pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT)
#else
#define pmd_page_vaddr(pmd)	\
	((unsigned long) (pmd_val(pmd) & PAGE_MASK))
#define pmd_page(pmd)		\
	pfn_to_page((__pa(pmd_val(pmd)) >> PAGE_SHIFT))
#endif

/* to find an entry in a kernel page-table-directory */
#define pgd_offset_k(address) pgd_offset(&init_mm, address)

/* to find an entry in a page-table-directory */
#define pgd_index(address)	 ((address) >> PGDIR_SHIFT)
#define pgd_offset(mm, address)	 ((mm)->pgd + pgd_index(address))

/* Find an entry in the third-level page table.. */
#define pte_index(address)		\
	(((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
#define pte_offset_kernel(dir, addr)	\
	((pte_t *) pmd_page_vaddr(*(dir)) + pte_index(addr))
#define pte_offset_map(dir, addr)		\
	((pte_t *) kmap_atomic(pmd_page(*(dir))) + pte_index(addr))
#define pte_unmap(pte)		kunmap_atomic(pte)

/*
 * Encode and decode a swap entry.
 * Note that the bits we use in a PTE for representing a swap entry
 * must not include the _PAGE_PRESENT bit, the _PAGE_FILE bit, or the
 *_PAGE_HASHPTE bit (if used).  -- paulus
 */
#define __swp_type(entry)		((entry).val & 0x1f)
#define __swp_offset(entry)		((entry).val >> 5)
#define __swp_entry(type, offset)	((swp_entry_t) { (type) | ((offset) << 5) })
#define __pte_to_swp_entry(pte)		((swp_entry_t) { pte_val(pte) >> 3 })
#define __swp_entry_to_pte(x)		((pte_t) { (x).val << 3 })

/* Encode and decode a nonlinear file mapping entry */
#define PTE_FILE_MAX_BITS	29
#define pte_to_pgoff(pte)	(pte_val(pte) >> 3)
#define pgoff_to_pte(off)	((pte_t) { ((off) << 3) | _PAGE_FILE })

/*
 * No page table caches to initialise
 */
#define pgtable_cache_init()	do { } while (0)

extern int get_pteptr(struct mm_struct *mm, unsigned long addr, pte_t **ptep,
		      pmd_t **pmdp);

#endif /* !__ASSEMBLY__ */

#endif /* _ASM_POWERPC_PGTABLE_PPC32_H */
Commit	Line	Data
f88df14b DG	1	#ifndef _ASM_POWERPC_PGTABLE_PPC32_H
	2	#define _ASM_POWERPC_PGTABLE_PPC32_H
	3
d1953c88	4	#include <asm-generic/pgtable-nopmd.h>
f88df14b DG	5
	6	#ifndef __ASSEMBLY__
	7	#include <linux/sched.h>
	8	#include <linux/threads.h>
f88df14b	9	#include <asm/io.h> /* For sub-arch specific PPC_PIN_SIZE */
f88df14b DG	10
	11	extern unsigned long va_to_phys(unsigned long address);
	12	extern pte_t *va_to_pte(unsigned long address);
f637a49e	13	extern unsigned long ioremap_bot;
b98ac05d BH	14
	15	#ifdef CONFIG_44x
	16	extern int icache_44x_need_flush;
	17	#endif
	18
f88df14b DG	19	#endif /* __ASSEMBLY__ */
f88df14b DG	20
f88df14b DG	21	/*
	22	* The normal case is that PTEs are 32-bits and we have a 1-page
	23	* 1024-entry pgdir pointing to 1-page 1024-entry PTE pages. -- paulus
	24	*
	25	* For any >32-bit physical address platform, we can use the following
	26	* two level page table layout where the pgdir is 8KB and the MS 13 bits
	27	* are an index to the second level table. The combined pgdir/pmd first
	28	* level has 2048 entries and the second level has 512 64-bit PTE entries.
	29	* -Matt
	30	*/
f88df14b	31	/* PGDIR_SHIFT determines what a top-level page table entry can map */
d1953c88	32	#define PGDIR_SHIFT (PAGE_SHIFT + PTE_SHIFT)
f88df14b DG	33	#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
	34	#define PGDIR_MASK (~(PGDIR_SIZE-1))
	35
	36	/*
	37	* entries per page directory level: our page-table tree is two-level, so
	38	* we don't really have any PMD directory.
	39	*/
bee86f14 KG	40	#ifndef __ASSEMBLY__
	41	#define PTE_TABLE_SIZE (sizeof(pte_t) << PTE_SHIFT)
	42	#define PGD_TABLE_SIZE (sizeof(pgd_t) << (32 - PGDIR_SHIFT))
	43	#endif /* __ASSEMBLY__ */
	44
f88df14b DG	45	#define PTRS_PER_PTE (1 << PTE_SHIFT)
	46	#define PTRS_PER_PMD 1
	47	#define PTRS_PER_PGD (1 << (32 - PGDIR_SHIFT))
	48
	49	#define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
	50	#define FIRST_USER_ADDRESS 0
	51
f88df14b	52	#define pte_ERROR(e) \
0aeafb0c DG	53	printk("%s:%d: bad pte %llx.\n", __FILE__, __LINE__, \
0aeafb0c DG	54	(unsigned long long)pte_val(e))
f88df14b DG	55	#define pgd_ERROR(e) \
	56	printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
	57
f637a49e BH	58	/*
	59	* This is the bottom of the PKMAP area with HIGHMEM or an arbitrary
	60	* value (for now) on others, from where we can start layout kernel
	61	* virtual space that goes below PKMAP and FIXMAP
	62	*/
	63	#ifdef CONFIG_HIGHMEM
	64	#define KVIRT_TOP PKMAP_BASE
	65	#else
	66	#define KVIRT_TOP (0xfe000000UL) /* for now, could be FIXMAP_BASE ? */
	67	#endif
	68
	69	/*
	70	* ioremap_bot starts at that address. Early ioremaps move down from there,
	71	* until mem_init() at which point this becomes the top of the vmalloc
	72	* and ioremap space
	73	*/
8b31e49d BH	74	#ifdef CONFIG_NOT_COHERENT_CACHE
	75	#define IOREMAP_TOP ((KVIRT_TOP - CONFIG_CONSISTENT_SIZE) & PAGE_MASK)
	76	#else
f637a49e	77	#define IOREMAP_TOP KVIRT_TOP
8b31e49d	78	#endif
f637a49e	79
f88df14b DG	80	/*
f88df14b DG	81	* Just any arbitrary offset to the start of the vmalloc VM area: the
f637a49e	82	* current 16MB value just means that there will be a 64MB "hole" after the
f88df14b DG	83	* physical memory until the kernel virtual memory starts. That means that
	84	* any out-of-bounds memory accesses will hopefully be caught.
	85	* The vmalloc() routines leaves a hole of 4kB between each vmalloced
	86	* area for the same reason. ;)
	87	*
	88	* We no longer map larger than phys RAM with the BATs so we don't have
	89	* to worry about the VMALLOC_OFFSET causing problems. We do have to worry
	90	* about clashes between our early calls to ioremap() that start growing down
	91	* from ioremap_base being run into the VM area allocations (growing upwards
	92	* from VMALLOC_START). For this reason we have ioremap_bot to check when
	93	* we actually run into our mappings setup in the early boot with the VM
	94	* system. This really does become a problem for machines with good amounts
	95	* of RAM. -- Cort
	96	*/
	97	#define VMALLOC_OFFSET (0x1000000) /* 16M */
	98	#ifdef PPC_PIN_SIZE
	99	#define VMALLOC_START (((_ALIGN((long)high_memory, PPC_PIN_SIZE) + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
	100	#else
	101	#define VMALLOC_START ((((long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
	102	#endif
	103	#define VMALLOC_END ioremap_bot
	104
	105	/*
	106	* Bits in a linux-style PTE. These match the bits in the
	107	* (hardware-defined) PowerPC PTE as closely as possible.
	108	*/
	109
	110	#if defined(CONFIG_40x)
c605782b	111	#include <asm/pte-40x.h>
f88df14b	112	#elif defined(CONFIG_44x)
c605782b	113	#include <asm/pte-44x.h>
76acc2c1 KG	114	#elif defined(CONFIG_FSL_BOOKE) && defined(CONFIG_PTE_64BIT)
76acc2c1 KG	115	#include <asm/pte-book3e.h>
f88df14b	116	#elif defined(CONFIG_FSL_BOOKE)
c605782b	117	#include <asm/pte-fsl-booke.h>
f88df14b	118	#elif defined(CONFIG_8xx)
c605782b	119	#include <asm/pte-8xx.h>
f88df14b	120	#else /* CONFIG_6xx */
c605782b	121	#include <asm/pte-hash32.h>
4ee7084e	122	#endif
f88df14b	123
71087002 BH	124	/* And here we include common definitions */
71087002 BH	125	#include <asm/pte-common.h>
f88df14b DG	126
f88df14b DG	127	#ifndef __ASSEMBLY__
f88df14b	128
9bf2b5cd KG	129	#define pte_clear(mm, addr, ptep) \
9bf2b5cd KG	130	do { pte_update(ptep, ~_PAGE_HASHPTE, 0); } while (0)
f88df14b DG	131
	132	#define pmd_none(pmd) (!pmd_val(pmd))
	133	#define pmd_bad(pmd) (pmd_val(pmd) & _PMD_BAD)
	134	#define pmd_present(pmd) (pmd_val(pmd) & _PMD_PRESENT_MASK)
	135	#define pmd_clear(pmdp) do { pmd_val(*(pmdp)) = 0; } while (0)
	136
f88df14b DG	137	/*
	138	* When flushing the tlb entry for a page, we also need to flush the hash
	139	* table entry. flush_hash_pages is assembler (for speed) in hashtable.S.
	140	*/
	141	extern int flush_hash_pages(unsigned context, unsigned long va,
	142	unsigned long pmdval, int count);
	143
	144	/* Add an HPTE to the hash table */
	145	extern void add_hash_page(unsigned context, unsigned long va,
	146	unsigned long pmdval);
	147
4ee7084e BB	148	/* Flush an entry from the TLB/hash table */
	149	extern void flush_hash_entry(struct mm_struct mm, pte_t ptep,
	150	unsigned long address);
	151
f88df14b	152	/*
c605782b BH	153	* PTE updates. This function is called whenever an existing
	154	* valid PTE is updated. This does -not- include set_pte_at()
	155	* which nowadays only sets a new PTE.
	156	*
	157	* Depending on the type of MMU, we may need to use atomic updates
	158	* and the PTE may be either 32 or 64 bit wide. In the later case,
	159	* when using atomic updates, only the low part of the PTE is
	160	* accessed atomically.
f88df14b	161	*
c605782b BH	162	* In addition, on 44x, we also maintain a global flag indicating
	163	* that an executable user mapping was modified, which is needed
	164	* to properly flush the virtually tagged instruction cache of
	165	* those implementations.
f88df14b DG	166	*/
f88df14b DG	167	#ifndef CONFIG_PTE_64BIT
1bc54c03 BH	168	static inline unsigned long pte_update(pte_t *p,
1bc54c03 BH	169	unsigned long clr,
f88df14b DG	170	unsigned long set)
f88df14b DG	171	{
1bc54c03	172	#ifdef PTE_ATOMIC_UPDATES
f88df14b DG	173	unsigned long old, tmp;
	174
	175	__asm__ __volatile__("\
	176	1: lwarx %0,0,%3\n\
	177	andc %1,%0,%4\n\
	178	or %1,%1,%5\n"
	179	PPC405_ERR77(0,%3)
	180	" stwcx. %1,0,%3\n\
	181	bne- 1b"
	182	: "=&r" (old), "=&r" (tmp), "=m" (*p)
	183	: "r" (p), "r" (clr), "r" (set), "m" (*p)
	184	: "cc" );
1bc54c03 BH	185	#else /* PTE_ATOMIC_UPDATES */
	186	unsigned long old = pte_val(*p);
	187	*p = __pte((old & ~clr) \| set);
	188	#endif /* !PTE_ATOMIC_UPDATES */
	189
b98ac05d	190	#ifdef CONFIG_44x
ea3cc330	191	if ((old & _PAGE_USER) && (old & _PAGE_EXEC))
b98ac05d BH	192	icache_44x_need_flush = 1;
b98ac05d BH	193	#endif
f88df14b DG	194	return old;
f88df14b DG	195	}
1bc54c03	196	#else /* CONFIG_PTE_64BIT */
1bc54c03 BH	197	static inline unsigned long long pte_update(pte_t *p,
	198	unsigned long clr,
	199	unsigned long set)
f88df14b	200	{
1bc54c03	201	#ifdef PTE_ATOMIC_UPDATES
f88df14b DG	202	unsigned long long old;
	203	unsigned long tmp;
	204
	205	__asm__ __volatile__("\
	206	1: lwarx %L0,0,%4\n\
	207	lwzx %0,0,%3\n\
	208	andc %1,%L0,%5\n\
	209	or %1,%1,%6\n"
	210	PPC405_ERR77(0,%3)
	211	" stwcx. %1,0,%4\n\
	212	bne- 1b"
	213	: "=&r" (old), "=&r" (tmp), "=m" (*p)
	214	: "r" (p), "r" ((unsigned long)(p) + 4), "r" (clr), "r" (set), "m" (*p)
	215	: "cc" );
1bc54c03 BH	216	#else /* PTE_ATOMIC_UPDATES */
1bc54c03 BH	217	unsigned long long old = pte_val(*p);
585583d9	218	*p = __pte((old & ~(unsigned long long)clr) \| set);
1bc54c03 BH	219	#endif /* !PTE_ATOMIC_UPDATES */
1bc54c03 BH	220
b98ac05d	221	#ifdef CONFIG_44x
ea3cc330	222	if ((old & _PAGE_USER) && (old & _PAGE_EXEC))
b98ac05d BH	223	icache_44x_need_flush = 1;
b98ac05d BH	224	#endif
f88df14b DG	225	return old;
f88df14b DG	226	}
1bc54c03	227	#endif /* CONFIG_PTE_64BIT */
f88df14b	228
f88df14b	229	/*
bf2737f7 BB	230	* 2.6 calls this without flushing the TLB entry; this is wrong
bf2737f7 BB	231	* for our hash-based implementation, we fix that up here.
f88df14b DG	232	*/
	233	#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
	234	static inline int __ptep_test_and_clear_young(unsigned int context, unsigned long addr, pte_t *ptep)
	235	{
	236	unsigned long old;
	237	old = pte_update(ptep, _PAGE_ACCESSED, 0);
	238	#if _PAGE_HASHPTE != 0
	239	if (old & _PAGE_HASHPTE) {
	240	unsigned long ptephys = __pa(ptep) & PAGE_MASK;
	241	flush_hash_pages(context, addr, ptephys, 1);
	242	}
	243	#endif
	244	return (old & _PAGE_ACCESSED) != 0;
	245	}
	246	#define ptep_test_and_clear_young(__vma, __addr, __ptep) \
	247	__ptep_test_and_clear_young((__vma)->vm_mm->context.id, __addr, __ptep)
	248
f88df14b DG	249	#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
	250	static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr,
	251	pte_t *ptep)
	252	{
	253	return __pte(pte_update(ptep, ~_PAGE_HASHPTE, 0));
	254	}
	255
	256	#define __HAVE_ARCH_PTEP_SET_WRPROTECT
	257	static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
	258	pte_t *ptep)
	259	{
	260	pte_update(ptep, (_PAGE_RW \| _PAGE_HWWRITE), 0);
	261	}
016b33c4 AW	262	static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
	263	unsigned long addr, pte_t *ptep)
	264	{
	265	ptep_set_wrprotect(mm, addr, ptep);
	266	}
	267
f88df14b	268
8d30c14c	269	static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry)
f88df14b DG	270	{
f88df14b DG	271	unsigned long bits = pte_val(entry) &
ea3cc330	272	(_PAGE_DIRTY \| _PAGE_ACCESSED \| _PAGE_RW \| _PAGE_EXEC);
f88df14b DG	273	pte_update(ptep, 0, bits);
	274	}
	275
f88df14b DG	276	#define __HAVE_ARCH_PTE_SAME
	277	#define pte_same(A,B) (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HASHPTE) == 0)
	278
	279	/*
	280	* Note that on Book E processors, the pmd contains the kernel virtual
	281	* (lowmem) address of the pte page. The physical address is less useful
	282	* because everything runs with translation enabled (even the TLB miss
	283	* handler). On everything else the pmd contains the physical address
	284	* of the pte page. -- paulus
	285	*/
	286	#ifndef CONFIG_BOOKE
	287	#define pmd_page_vaddr(pmd) \
	288	((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
	289	#define pmd_page(pmd) \
43b5fefc	290	pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT)
f88df14b DG	291	#else
	292	#define pmd_page_vaddr(pmd) \
	293	((unsigned long) (pmd_val(pmd) & PAGE_MASK))
	294	#define pmd_page(pmd) \
af892e0f	295	pfn_to_page((__pa(pmd_val(pmd)) >> PAGE_SHIFT))
f88df14b DG	296	#endif
	297
	298	/* to find an entry in a kernel page-table-directory */
	299	#define pgd_offset_k(address) pgd_offset(&init_mm, address)
	300
	301	/* to find an entry in a page-table-directory */
	302	#define pgd_index(address) ((address) >> PGDIR_SHIFT)
	303	#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
	304
f88df14b DG	305	/* Find an entry in the third-level page table.. */
	306	#define pte_index(address) \
	307	(((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
	308	#define pte_offset_kernel(dir, addr) \
	309	((pte_t ) pmd_page_vaddr((dir)) + pte_index(addr))
	310	#define pte_offset_map(dir, addr) \
ece0e2b6 PZ	311	((pte_t ) kmap_atomic(pmd_page((dir))) + pte_index(addr))
ece0e2b6 PZ	312	#define pte_unmap(pte) kunmap_atomic(pte)
f88df14b	313
f88df14b DG	314	/*
	315	* Encode and decode a swap entry.
	316	* Note that the bits we use in a PTE for representing a swap entry
	317	* must not include the _PAGE_PRESENT bit, the _PAGE_FILE bit, or the
	318	*_PAGE_HASHPTE bit (if used). -- paulus
	319	*/
	320	#define __swp_type(entry) ((entry).val & 0x1f)
	321	#define __swp_offset(entry) ((entry).val >> 5)
	322	#define __swp_entry(type, offset) ((swp_entry_t) { (type) \| ((offset) << 5) })
	323	#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) >> 3 })
	324	#define __swp_entry_to_pte(x) ((pte_t) { (x).val << 3 })
	325
	326	/* Encode and decode a nonlinear file mapping entry */
	327	#define PTE_FILE_MAX_BITS 29
	328	#define pte_to_pgoff(pte) (pte_val(pte) >> 3)
	329	#define pgoff_to_pte(off) ((pte_t) { ((off) << 3) \| _PAGE_FILE })
	330
f88df14b DG	331	/*
	332	* No page table caches to initialise
	333	*/
	334	#define pgtable_cache_init() do { } while (0)
	335
	336	extern int get_pteptr(struct mm_struct mm, unsigned long addr, pte_t *ptep,
	337	pmd_t **pmdp);
	338
	339	#endif /* !__ASSEMBLY__ */
	340
	341	#endif /* _ASM_POWERPC_PGTABLE_PPC32_H */