[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / powerpc / include / asm / perf_event_fsl_emb.h

/*
 * Performance event support - Freescale embedded specific definitions.
 *
 * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
 * Copyright 2010 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */

#include <linux/types.h>
#include <asm/hw_irq.h>

#define MAX_HWEVENTS 4

/* event flags */
#define FSL_EMB_EVENT_VALID      1
#define FSL_EMB_EVENT_RESTRICTED 2

/* upper half of event flags is PMLCb */
#define FSL_EMB_EVENT_THRESHMUL  0x0000070000000000ULL
#define FSL_EMB_EVENT_THRESH     0x0000003f00000000ULL

struct fsl_emb_pmu {
	const char	*name;
	int		n_counter; /* total number of counters */

	/*
	 * The number of contiguous counters starting at zero that
	 * can hold restricted events, or zero if there are no
	 * restricted events.
	 *
	 * This isn't a very flexible method of expressing constraints,
	 * but it's very simple and is adequate for existing chips.
	 */
	int		n_restricted;

	/* Returns event flags and PMLCb (FSL_EMB_EVENT_*) */
	u64		(*xlate_event)(u64 event_id);

	int		n_generic;
	int		*generic_events;
	int		(*cache_events)[PERF_COUNT_HW_CACHE_MAX]
			       [PERF_COUNT_HW_CACHE_OP_MAX]
			       [PERF_COUNT_HW_CACHE_RESULT_MAX];
};

int register_fsl_emb_pmu(struct fsl_emb_pmu *);
Commit	Line	Data
a1110654 SW	1	/*
	2	* Performance event support - Freescale embedded specific definitions.
	3	*
	4	* Copyright 2008-2009 Paul Mackerras, IBM Corporation.
	5	* Copyright 2010 Freescale Semiconductor, Inc.
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License
	9	* as published by the Free Software Foundation; either version
	10	* 2 of the License, or (at your option) any later version.
	11	*/
	12
	13	#include <linux/types.h>
	14	#include <asm/hw_irq.h>
	15
	16	#define MAX_HWEVENTS 4
	17
	18	/* event flags */
	19	#define FSL_EMB_EVENT_VALID 1
	20	#define FSL_EMB_EVENT_RESTRICTED 2
	21
	22	/* upper half of event flags is PMLCb */
	23	#define FSL_EMB_EVENT_THRESHMUL 0x0000070000000000ULL
	24	#define FSL_EMB_EVENT_THRESH 0x0000003f00000000ULL
	25
	26	struct fsl_emb_pmu {
	27	const char *name;
	28	int n_counter; /* total number of counters */
	29
	30	/*
	31	* The number of contiguous counters starting at zero that
	32	* can hold restricted events, or zero if there are no
	33	* restricted events.
	34	*
	35	* This isn't a very flexible method of expressing constraints,
	36	* but it's very simple and is adequate for existing chips.
	37	*/
	38	int n_restricted;
	39
	40	/* Returns event flags and PMLCb (FSL_EMB_EVENT_) /
	41	u64 (*xlate_event)(u64 event_id);
	42
	43	int n_generic;
	44	int *generic_events;
	45	int (*cache_events)[PERF_COUNT_HW_CACHE_MAX]
	46	[PERF_COUNT_HW_CACHE_OP_MAX]
	47	[PERF_COUNT_HW_CACHE_RESULT_MAX];
	48	};
	49
	50	int register_fsl_emb_pmu(struct fsl_emb_pmu *);