[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / powerpc / include / asm / mmu.h

#ifndef _ASM_POWERPC_MMU_H_
#define _ASM_POWERPC_MMU_H_
#ifdef __KERNEL__

#include <linux/types.h>

#include <asm/asm-compat.h>
#include <asm/feature-fixups.h>

/*
 * MMU features bit definitions
 */

/*
 * First half is MMU families
 */
#define MMU_FTR_HPTE_TABLE		ASM_CONST(0x00000001)
#define MMU_FTR_TYPE_8xx		ASM_CONST(0x00000002)
#define MMU_FTR_TYPE_40x		ASM_CONST(0x00000004)
#define MMU_FTR_TYPE_44x		ASM_CONST(0x00000008)
#define MMU_FTR_TYPE_FSL_E		ASM_CONST(0x00000010)
#define MMU_FTR_TYPE_3E			ASM_CONST(0x00000020)
#define MMU_FTR_TYPE_47x		ASM_CONST(0x00000040)

/*
 * This is individual features
 */

/* Enable use of high BAT registers */
#define MMU_FTR_USE_HIGH_BATS		ASM_CONST(0x00010000)

/* Enable >32-bit physical addresses on 32-bit processor, only used
 * by CONFIG_6xx currently as BookE supports that from day 1
 */
#define MMU_FTR_BIG_PHYS		ASM_CONST(0x00020000)

/* Enable use of broadcast TLB invalidations. We don't always set it
 * on processors that support it due to other constraints with the
 * use of such invalidations
 */
#define MMU_FTR_USE_TLBIVAX_BCAST	ASM_CONST(0x00040000)

/* Enable use of tlbilx invalidate instructions.
 */
#define MMU_FTR_USE_TLBILX		ASM_CONST(0x00080000)

/* This indicates that the processor cannot handle multiple outstanding
 * broadcast tlbivax or tlbsync. This makes the code use a spinlock
 * around such invalidate forms.
 */
#define MMU_FTR_LOCK_BCAST_INVAL	ASM_CONST(0x00100000)

/* This indicates that the processor doesn't handle way selection
 * properly and needs SW to track and update the LRU state.  This
 * is specific to an errata on e300c2/c3/c4 class parts
 */
#define MMU_FTR_NEED_DTLB_SW_LRU	ASM_CONST(0x00200000)

/* Enable use of TLB reservation.  Processor should support tlbsrx.
 * instruction and MAS0[WQ].
 */
#define MMU_FTR_USE_TLBRSRV		ASM_CONST(0x00800000)

/* Use paired MAS registers (MAS7||MAS3, etc.)
 */
#define MMU_FTR_USE_PAIRED_MAS		ASM_CONST(0x01000000)

/* MMU is SLB-based
 */
#define MMU_FTR_SLB			ASM_CONST(0x02000000)

/* Support 16M large pages
 */
#define MMU_FTR_16M_PAGE		ASM_CONST(0x04000000)

/* Supports TLBIEL variant
 */
#define MMU_FTR_TLBIEL			ASM_CONST(0x08000000)

/* Supports tlbies w/o locking
 */
#define MMU_FTR_LOCKLESS_TLBIE		ASM_CONST(0x10000000)

/* Large pages can be marked CI
 */
#define MMU_FTR_CI_LARGE_PAGE		ASM_CONST(0x20000000)

/* 1T segments available
 */
#define MMU_FTR_1T_SEGMENT		ASM_CONST(0x40000000)

/* Doesn't support the B bit (1T segment) in SLBIE
 */
#define MMU_FTR_NO_SLBIE_B		ASM_CONST(0x80000000)

/* MMU feature bit sets for various CPUs */
#define MMU_FTRS_DEFAULT_HPTE_ARCH_V2	\
	MMU_FTR_HPTE_TABLE | MMU_FTR_PPCAS_ARCH_V2
#define MMU_FTRS_POWER4		MMU_FTRS_DEFAULT_HPTE_ARCH_V2
#define MMU_FTRS_PPC970		MMU_FTRS_POWER4
#define MMU_FTRS_POWER5		MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE
#define MMU_FTRS_POWER6		MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE
#define MMU_FTRS_POWER7		MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE
#define MMU_FTRS_CELL		MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \
				MMU_FTR_CI_LARGE_PAGE
#define MMU_FTRS_PA6T		MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \
				MMU_FTR_CI_LARGE_PAGE | MMU_FTR_NO_SLBIE_B
#define MMU_FTRS_A2		MMU_FTR_TYPE_3E | MMU_FTR_USE_TLBILX | \
				MMU_FTR_USE_TLBIVAX_BCAST | \
				MMU_FTR_LOCK_BCAST_INVAL | \
				MMU_FTR_USE_TLBRSRV | \
				MMU_FTR_USE_PAIRED_MAS | \
				MMU_FTR_TLBIEL | \
				MMU_FTR_16M_PAGE
#ifndef __ASSEMBLY__
#include <asm/cputable.h>

static inline int mmu_has_feature(unsigned long feature)
{
	return (cur_cpu_spec->mmu_features & feature);
}

static inline void mmu_clear_feature(unsigned long feature)
{
	cur_cpu_spec->mmu_features &= ~feature;
}

extern unsigned int __start___mmu_ftr_fixup, __stop___mmu_ftr_fixup;

/* MMU initialization */
extern void early_init_mmu(void);
extern void early_init_mmu_secondary(void);

extern void setup_initial_memory_limit(phys_addr_t first_memblock_base,
				       phys_addr_t first_memblock_size);

#ifdef CONFIG_PPC64
/* This is our real memory area size on ppc64 server, on embedded, we
 * make it match the size our of bolted TLB area
 */
extern u64 ppc64_rma_size;
#endif /* CONFIG_PPC64 */

#endif /* !__ASSEMBLY__ */

/* The kernel use the constants below to index in the page sizes array.
 * The use of fixed constants for this purpose is better for performances
 * of the low level hash refill handlers.
 *
 * A non supported page size has a "shift" field set to 0
 *
 * Any new page size being implemented can get a new entry in here. Whether
 * the kernel will use it or not is a different matter though. The actual page
 * size used by hugetlbfs is not defined here and may be made variable
 *
 * Note: This array ended up being a false good idea as it's growing to the
 * point where I wonder if we should replace it with something different,
 * to think about, feedback welcome. --BenH.
 */

/* There are #define as they have to be used in assembly
 *
 * WARNING: If you change this list, make sure to update the array of
 * names currently in arch/powerpc/mm/hugetlbpage.c or bad things will
 * happen
 */
#define MMU_PAGE_4K	0
#define MMU_PAGE_16K	1
#define MMU_PAGE_64K	2
#define MMU_PAGE_64K_AP	3	/* "Admixed pages" (hash64 only) */
#define MMU_PAGE_256K	4
#define MMU_PAGE_1M	5
#define MMU_PAGE_8M	6
#define MMU_PAGE_16M	7
#define MMU_PAGE_256M	8
#define MMU_PAGE_1G	9
#define MMU_PAGE_16G	10
#define MMU_PAGE_64G	11
#define MMU_PAGE_COUNT	12


#if defined(CONFIG_PPC_STD_MMU_64)
/* 64-bit classic hash table MMU */
#  include <asm/mmu-hash64.h>
#elif defined(CONFIG_PPC_STD_MMU_32)
/* 32-bit classic hash table MMU */
#  include <asm/mmu-hash32.h>
#elif defined(CONFIG_40x)
/* 40x-style software loaded TLB */
#  include <asm/mmu-40x.h>
#elif defined(CONFIG_44x)
/* 44x-style software loaded TLB */
#  include <asm/mmu-44x.h>
#elif defined(CONFIG_PPC_BOOK3E_MMU)
/* Freescale Book-E software loaded TLB or Book-3e (ISA 2.06+) MMU */
#  include <asm/mmu-book3e.h>
#elif defined (CONFIG_PPC_8xx)
/* Motorola/Freescale 8xx software loaded TLB */
#  include <asm/mmu-8xx.h>
#endif


#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_MMU_H_ */
Commit	Line	Data
047ea784 PM	1	#ifndef _ASM_POWERPC_MMU_H_
047ea784 PM	2	#define _ASM_POWERPC_MMU_H_
88ced031	3	#ifdef __KERNEL__
047ea784	4
cd3db0c4 BH	5	#include <linux/types.h>
cd3db0c4 BH	6
7c03d653 BH	7	#include <asm/asm-compat.h>
	8	#include <asm/feature-fixups.h>
	9
	10	/*
	11	* MMU features bit definitions
	12	*/
	13
	14	/*
	15	* First half is MMU families
	16	*/
	17	#define MMU_FTR_HPTE_TABLE ASM_CONST(0x00000001)
	18	#define MMU_FTR_TYPE_8xx ASM_CONST(0x00000002)
	19	#define MMU_FTR_TYPE_40x ASM_CONST(0x00000004)
	20	#define MMU_FTR_TYPE_44x ASM_CONST(0x00000008)
	21	#define MMU_FTR_TYPE_FSL_E ASM_CONST(0x00000010)
57e2a99f	22	#define MMU_FTR_TYPE_3E ASM_CONST(0x00000020)
e7f75ad0	23	#define MMU_FTR_TYPE_47x ASM_CONST(0x00000040)
7c03d653 BH	24
	25	/*
	26	* This is individual features
	27	*/
	28
	29	/* Enable use of high BAT registers */
	30	#define MMU_FTR_USE_HIGH_BATS ASM_CONST(0x00010000)
	31
	32	/* Enable >32-bit physical addresses on 32-bit processor, only used
	33	* by CONFIG_6xx currently as BookE supports that from day 1
	34	*/
	35	#define MMU_FTR_BIG_PHYS ASM_CONST(0x00020000)
	36
f048aace BH	37	/* Enable use of broadcast TLB invalidations. We don't always set it
	38	* on processors that support it due to other constraints with the
	39	* use of such invalidations
	40	*/
	41	#define MMU_FTR_USE_TLBIVAX_BCAST ASM_CONST(0x00040000)
	42
c3071951	43	/* Enable use of tlbilx invalidate instructions.
f048aace	44	*/
c3071951	45	#define MMU_FTR_USE_TLBILX ASM_CONST(0x00080000)
f048aace BH	46
	47	/* This indicates that the processor cannot handle multiple outstanding
	48	* broadcast tlbivax or tlbsync. This makes the code use a spinlock
	49	* around such invalidate forms.
	50	*/
	51	#define MMU_FTR_LOCK_BCAST_INVAL ASM_CONST(0x00100000)
	52
2319f123 KG	53	/* This indicates that the processor doesn't handle way selection
	54	* properly and needs SW to track and update the LRU state. This
	55	* is specific to an errata on e300c2/c3/c4 class parts
	56	*/
	57	#define MMU_FTR_NEED_DTLB_SW_LRU ASM_CONST(0x00200000)
	58
df5d6ecf KG	59	/* Enable use of TLB reservation. Processor should support tlbsrx.
	60	* instruction and MAS0[WQ].
	61	*/
	62	#define MMU_FTR_USE_TLBRSRV ASM_CONST(0x00800000)
	63
	64	/* Use paired MAS registers (MAS7\|\|MAS3, etc.)
	65	*/
	66	#define MMU_FTR_USE_PAIRED_MAS ASM_CONST(0x01000000)
	67
44ae3ab3 ME	68	/* MMU is SLB-based
	69	*/
	70	#define MMU_FTR_SLB ASM_CONST(0x02000000)
	71
	72	/* Support 16M large pages
	73	*/
	74	#define MMU_FTR_16M_PAGE ASM_CONST(0x04000000)
	75
	76	/* Supports TLBIEL variant
	77	*/
	78	#define MMU_FTR_TLBIEL ASM_CONST(0x08000000)
	79
	80	/* Supports tlbies w/o locking
	81	*/
	82	#define MMU_FTR_LOCKLESS_TLBIE ASM_CONST(0x10000000)
	83
	84	/* Large pages can be marked CI
	85	*/
	86	#define MMU_FTR_CI_LARGE_PAGE ASM_CONST(0x20000000)
	87
	88	/* 1T segments available
	89	*/
	90	#define MMU_FTR_1T_SEGMENT ASM_CONST(0x40000000)
	91
	92	/* Doesn't support the B bit (1T segment) in SLBIE
	93	*/
	94	#define MMU_FTR_NO_SLBIE_B ASM_CONST(0x80000000)
	95
	96	/* MMU feature bit sets for various CPUs */
	97	#define MMU_FTRS_DEFAULT_HPTE_ARCH_V2 \
	98	MMU_FTR_HPTE_TABLE \| MMU_FTR_PPCAS_ARCH_V2
	99	#define MMU_FTRS_POWER4 MMU_FTRS_DEFAULT_HPTE_ARCH_V2
	100	#define MMU_FTRS_PPC970 MMU_FTRS_POWER4
	101	#define MMU_FTRS_POWER5 MMU_FTRS_POWER4 \| MMU_FTR_LOCKLESS_TLBIE
	102	#define MMU_FTRS_POWER6 MMU_FTRS_POWER4 \| MMU_FTR_LOCKLESS_TLBIE
a32e252f	103	#define MMU_FTRS_POWER7 MMU_FTRS_POWER4 \| MMU_FTR_LOCKLESS_TLBIE
44ae3ab3 ME	104	#define MMU_FTRS_CELL MMU_FTRS_DEFAULT_HPTE_ARCH_V2 \| \
	105	MMU_FTR_CI_LARGE_PAGE
	106	#define MMU_FTRS_PA6T MMU_FTRS_DEFAULT_HPTE_ARCH_V2 \| \
	107	MMU_FTR_CI_LARGE_PAGE \| MMU_FTR_NO_SLBIE_B
	108	#define MMU_FTRS_A2 MMU_FTR_TYPE_3E \| MMU_FTR_USE_TLBILX \| \
	109	MMU_FTR_USE_TLBIVAX_BCAST \| \
	110	MMU_FTR_LOCK_BCAST_INVAL \| \
	111	MMU_FTR_USE_TLBRSRV \| \
	112	MMU_FTR_USE_PAIRED_MAS \| \
	113	MMU_FTR_TLBIEL \| \
	114	MMU_FTR_16M_PAGE
7c03d653 BH	115	#ifndef __ASSEMBLY__
	116	#include <asm/cputable.h>
	117
	118	static inline int mmu_has_feature(unsigned long feature)
	119	{
	120	return (cur_cpu_spec->mmu_features & feature);
	121	}
	122
91b191c7 DK	123	static inline void mmu_clear_feature(unsigned long feature)
	124	{
	125	cur_cpu_spec->mmu_features &= ~feature;
	126	}
	127
7c03d653 BH	128	extern unsigned int __start___mmu_ftr_fixup, __stop___mmu_ftr_fixup;
7c03d653 BH	129
91b191c7	130	/* MMU initialization */
757c74d2 BH	131	extern void early_init_mmu(void);
	132	extern void early_init_mmu_secondary(void);
	133
cd3db0c4 BH	134	extern void setup_initial_memory_limit(phys_addr_t first_memblock_base,
	135	phys_addr_t first_memblock_size);
	136
	137	#ifdef CONFIG_PPC64
	138	/* This is our real memory area size on ppc64 server, on embedded, we
	139	* make it match the size our of bolted TLB area
	140	*/
	141	extern u64 ppc64_rma_size;
	142	#endif /* CONFIG_PPC64 */
	143
7c03d653 BH	144	#endif /* !__ASSEMBLY__ */
7c03d653 BH	145
57e2a99f BH	146	/* The kernel use the constants below to index in the page sizes array.
	147	* The use of fixed constants for this purpose is better for performances
	148	* of the low level hash refill handlers.
	149	*
	150	* A non supported page size has a "shift" field set to 0
	151	*
	152	* Any new page size being implemented can get a new entry in here. Whether
	153	* the kernel will use it or not is a different matter though. The actual page
	154	* size used by hugetlbfs is not defined here and may be made variable
	155	*
	156	* Note: This array ended up being a false good idea as it's growing to the
	157	* point where I wonder if we should replace it with something different,
	158	* to think about, feedback welcome. --BenH.
	159	*/
	160
	161	/* There are #define as they have to be used in assembly
	162	*
	163	* WARNING: If you change this list, make sure to update the array of
	164	* names currently in arch/powerpc/mm/hugetlbpage.c or bad things will
	165	* happen
	166	*/
	167	#define MMU_PAGE_4K 0
	168	#define MMU_PAGE_16K 1
	169	#define MMU_PAGE_64K 2
	170	#define MMU_PAGE_64K_AP 3 /* "Admixed pages" (hash64 only) */
	171	#define MMU_PAGE_256K 4
	172	#define MMU_PAGE_1M 5
	173	#define MMU_PAGE_8M 6
	174	#define MMU_PAGE_16M 7
	175	#define MMU_PAGE_256M 8
	176	#define MMU_PAGE_1G 9
	177	#define MMU_PAGE_16G 10
	178	#define MMU_PAGE_64G 11
	179	#define MMU_PAGE_COUNT 12
	180
7c03d653	181
94491685	182	#if defined(CONFIG_PPC_STD_MMU_64)
8d2169e8 DG	183	/* 64-bit classic hash table MMU */
8d2169e8 DG	184	# include <asm/mmu-hash64.h>
94491685	185	#elif defined(CONFIG_PPC_STD_MMU_32)
4db68bfe DG	186	/* 32-bit classic hash table MMU */
4db68bfe DG	187	# include <asm/mmu-hash32.h>
4d922c8d JB	188	#elif defined(CONFIG_40x)
	189	/* 40x-style software loaded TLB */
	190	# include <asm/mmu-40x.h>
57d7909e DG	191	#elif defined(CONFIG_44x)
	192	/* 44x-style software loaded TLB */
	193	# include <asm/mmu-44x.h>
70fe3af8 KG	194	#elif defined(CONFIG_PPC_BOOK3E_MMU)
	195	/* Freescale Book-E software loaded TLB or Book-3e (ISA 2.06+) MMU */
	196	# include <asm/mmu-book3e.h>
31202345 DG	197	#elif defined (CONFIG_PPC_8xx)
	198	/* Motorola/Freescale 8xx software loaded TLB */
	199	# include <asm/mmu-8xx.h>
1f8d419e	200	#endif
1f8d419e	201
57e2a99f	202
88ced031	203	#endif /* __KERNEL__ */
047ea784	204	#endif /* _ASM_POWERPC_MMU_H_ */