Commit | Line | Data |
---|---|---|
30be4c96 TT |
1 | /* |
2 | * P1022 DS 36Bit Physical Address Map Device Tree Source | |
3 | * | |
4 | * Copyright 2010 Freescale Semiconductor, Inc. | |
5 | * | |
6 | * This file is licensed under the terms of the GNU General Public License | |
7 | * version 2. This program is licensed "as is" without any warranty of any | |
8 | * kind, whether express or implied. | |
9 | */ | |
10 | ||
ab827d97 | 11 | /include/ "fsl/p1022si-pre.dtsi" |
30be4c96 | 12 | / { |
ab827d97 | 13 | model = "fsl,P1022DS"; |
30be4c96 | 14 | compatible = "fsl,P1022DS"; |
30be4c96 TT |
15 | |
16 | memory { | |
17 | device_type = "memory"; | |
18 | }; | |
19 | ||
ab827d97 KG |
20 | lbc: localbus@fffe05000 { |
21 | reg = <0xf 0xffe05000 0 0x1000>; | |
30be4c96 TT |
22 | ranges = <0x0 0x0 0xf 0xe8000000 0x08000000 |
23 | 0x1 0x0 0xf 0xe0000000 0x08000000 | |
ab827d97 | 24 | 0x2 0x0 0xf 0xffa00000 0x00040000 |
30be4c96 TT |
25 | 0x3 0x0 0xf 0xffdf0000 0x00008000>; |
26 | ||
27 | nor@0,0 { | |
28 | #address-cells = <1>; | |
29 | #size-cells = <1>; | |
30 | compatible = "cfi-flash"; | |
31 | reg = <0x0 0x0 0x8000000>; | |
32 | bank-width = <2>; | |
33 | device-width = <1>; | |
34 | ||
35 | partition@0 { | |
36 | reg = <0x0 0x03000000>; | |
37 | label = "ramdisk-nor"; | |
38 | read-only; | |
39 | }; | |
40 | ||
41 | partition@3000000 { | |
42 | reg = <0x03000000 0x00e00000>; | |
43 | label = "diagnostic-nor"; | |
44 | read-only; | |
45 | }; | |
46 | ||
47 | partition@3e00000 { | |
48 | reg = <0x03e00000 0x00200000>; | |
49 | label = "dink-nor"; | |
50 | read-only; | |
51 | }; | |
52 | ||
53 | partition@4000000 { | |
54 | reg = <0x04000000 0x00400000>; | |
55 | label = "kernel-nor"; | |
56 | read-only; | |
57 | }; | |
58 | ||
59 | partition@4400000 { | |
60 | reg = <0x04400000 0x03b00000>; | |
61 | label = "jffs2-nor"; | |
62 | }; | |
63 | ||
64 | partition@7f00000 { | |
65 | reg = <0x07f00000 0x00080000>; | |
66 | label = "dtb-nor"; | |
67 | read-only; | |
68 | }; | |
69 | ||
70 | partition@7f80000 { | |
71 | reg = <0x07f80000 0x00080000>; | |
72 | label = "u-boot-nor"; | |
73 | read-only; | |
74 | }; | |
75 | }; | |
76 | ||
77 | nand@2,0 { | |
78 | #address-cells = <1>; | |
79 | #size-cells = <1>; | |
80 | compatible = "fsl,elbc-fcm-nand"; | |
81 | reg = <0x2 0x0 0x40000>; | |
82 | ||
83 | partition@0 { | |
84 | reg = <0x0 0x02000000>; | |
85 | label = "u-boot-nand"; | |
86 | read-only; | |
87 | }; | |
88 | ||
89 | partition@2000000 { | |
90 | reg = <0x02000000 0x10000000>; | |
91 | label = "jffs2-nand"; | |
92 | }; | |
93 | ||
94 | partition@12000000 { | |
95 | reg = <0x12000000 0x10000000>; | |
96 | label = "ramdisk-nand"; | |
97 | read-only; | |
98 | }; | |
99 | ||
100 | partition@22000000 { | |
101 | reg = <0x22000000 0x04000000>; | |
102 | label = "kernel-nand"; | |
103 | }; | |
104 | ||
105 | partition@26000000 { | |
106 | reg = <0x26000000 0x01000000>; | |
107 | label = "dtb-nand"; | |
108 | read-only; | |
109 | }; | |
110 | ||
111 | partition@27000000 { | |
112 | reg = <0x27000000 0x19000000>; | |
113 | label = "reserved-nand"; | |
114 | }; | |
115 | }; | |
6341efe4 TT |
116 | |
117 | board-control@3,0 { | |
499ccb27 | 118 | compatible = "fsl,p1022ds-fpga", "fsl,fpga-ngpixis"; |
6341efe4 TT |
119 | reg = <3 0 0x30>; |
120 | interrupt-parent = <&mpic>; | |
121 | /* | |
122 | * IRQ8 is generated if the "EVENT" switch is pressed | |
123 | * and PX_CTL[EVESEL] is set to 00. | |
124 | */ | |
c281739f | 125 | interrupts = <8 8 0 0>; |
6341efe4 | 126 | }; |
30be4c96 TT |
127 | }; |
128 | ||
ab827d97 | 129 | soc: soc@fffe00000 { |
30be4c96 | 130 | ranges = <0x0 0xf 0xffe00000 0x100000>; |
30be4c96 TT |
131 | |
132 | i2c@3100 { | |
30be4c96 TT |
133 | wm8776:codec@1a { |
134 | compatible = "wlf,wm8776"; | |
135 | reg = <0x1a>; | |
f3fed682 TT |
136 | /* |
137 | * clock-frequency will be set by U-Boot if | |
138 | * the clock is enabled. | |
139 | */ | |
30be4c96 TT |
140 | }; |
141 | }; | |
142 | ||
30be4c96 | 143 | spi@7000 { |
ab827d97 | 144 | flash@0 { |
30be4c96 TT |
145 | #address-cells = <1>; |
146 | #size-cells = <1>; | |
ab827d97 | 147 | compatible = "spansion,s25sl12801"; |
30be4c96 | 148 | reg = <0>; |
30be4c96 | 149 | spi-max-frequency = <40000000>; /* input clock */ |
ab827d97 | 150 | |
30be4c96 TT |
151 | partition@0 { |
152 | label = "u-boot-spi"; | |
153 | reg = <0x00000000 0x00100000>; | |
154 | read-only; | |
155 | }; | |
156 | partition@100000 { | |
157 | label = "kernel-spi"; | |
158 | reg = <0x00100000 0x00500000>; | |
159 | read-only; | |
160 | }; | |
161 | partition@600000 { | |
162 | label = "dtb-spi"; | |
163 | reg = <0x00600000 0x00100000>; | |
164 | read-only; | |
165 | }; | |
166 | partition@700000 { | |
167 | label = "file system-spi"; | |
168 | reg = <0x00700000 0x00900000>; | |
169 | }; | |
170 | }; | |
171 | }; | |
172 | ||
173 | ssi@15000 { | |
30be4c96 TT |
174 | fsl,mode = "i2s-slave"; |
175 | codec-handle = <&wm8776>; | |
f3fed682 | 176 | fsl,ssi-asynchronous; |
30be4c96 TT |
177 | }; |
178 | ||
30be4c96 | 179 | usb@22000 { |
30be4c96 TT |
180 | phy_type = "ulpi"; |
181 | }; | |
182 | ||
ab827d97 KG |
183 | usb@23000 { |
184 | status = "disabled"; | |
185 | }; | |
30be4c96 | 186 | |
ab827d97 | 187 | mdio@24000 { |
30be4c96 | 188 | phy0: ethernet-phy@0 { |
c281739f | 189 | interrupts = <3 1 0 0>; |
30be4c96 TT |
190 | reg = <0x1>; |
191 | }; | |
192 | phy1: ethernet-phy@1 { | |
c281739f | 193 | interrupts = <9 1 0 0>; |
30be4c96 TT |
194 | reg = <0x2>; |
195 | }; | |
196 | }; | |
197 | ||
ab827d97 | 198 | ethernet@b0000 { |
30be4c96 TT |
199 | phy-handle = <&phy0>; |
200 | phy-connection-type = "rgmii-id"; | |
30be4c96 TT |
201 | }; |
202 | ||
ab827d97 | 203 | ethernet@b1000 { |
30be4c96 TT |
204 | phy-handle = <&phy1>; |
205 | phy-connection-type = "rgmii-id"; | |
30be4c96 TT |
206 | }; |
207 | }; | |
208 | ||
209 | pci0: pcie@fffe09000 { | |
30be4c96 | 210 | reg = <0xf 0xffe09000 0 0x1000>; |
30be4c96 TT |
211 | ranges = <0x2000000 0x0 0xa0000000 0xc 0x20000000 0x0 0x20000000 |
212 | 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>; | |
30be4c96 | 213 | pcie@0 { |
30be4c96 TT |
214 | ranges = <0x2000000 0x0 0xe0000000 |
215 | 0x2000000 0x0 0xe0000000 | |
216 | 0x0 0x20000000 | |
217 | ||
218 | 0x1000000 0x0 0x0 | |
219 | 0x1000000 0x0 0x0 | |
220 | 0x0 0x100000>; | |
221 | }; | |
222 | }; | |
223 | ||
224 | pci1: pcie@fffe0a000 { | |
30be4c96 | 225 | reg = <0xf 0xffe0a000 0 0x1000>; |
30be4c96 TT |
226 | ranges = <0x2000000 0x0 0xc0000000 0xc 0x40000000 0x0 0x20000000 |
227 | 0x1000000 0x0 0x00000000 0xf 0xffc20000 0x0 0x10000>; | |
30be4c96 TT |
228 | pcie@0 { |
229 | reg = <0x0 0x0 0x0 0x0 0x0>; | |
30be4c96 TT |
230 | ranges = <0x2000000 0x0 0xe0000000 |
231 | 0x2000000 0x0 0xe0000000 | |
232 | 0x0 0x20000000 | |
233 | ||
234 | 0x1000000 0x0 0x0 | |
235 | 0x1000000 0x0 0x0 | |
236 | 0x0 0x100000>; | |
237 | }; | |
238 | }; | |
239 | ||
30be4c96 | 240 | pci2: pcie@fffe0b000 { |
30be4c96 | 241 | reg = <0xf 0xffe0b000 0 0x1000>; |
30be4c96 TT |
242 | ranges = <0x2000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000 |
243 | 0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>; | |
30be4c96 | 244 | pcie@0 { |
30be4c96 TT |
245 | ranges = <0x2000000 0x0 0xe0000000 |
246 | 0x2000000 0x0 0xe0000000 | |
247 | 0x0 0x20000000 | |
248 | ||
249 | 0x1000000 0x0 0x0 | |
250 | 0x1000000 0x0 0x0 | |
251 | 0x0 0x100000>; | |
252 | }; | |
253 | }; | |
254 | }; | |
ab827d97 KG |
255 | |
256 | /include/ "fsl/p1022si-post.dtsi" |