[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / powerpc / boot / dts / lite5200b.dts

/*
 * Lite5200B board Device Tree Source
 *
 * Copyright 2006-2007 Secret Lab Technologies Ltd.
 * Grant Likely <grant.likely@secretlab.ca>
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

/*
 * WARNING: Do not depend on this tree layout remaining static just yet.
 * The MPC5200 device tree conventions are still in flux
 * Keep an eye on the linuxppc-dev mailing list for more details
 */

/ {
	model = "fsl,lite5200b";
	// revision = "1.0";
	compatible = "fsl,lite5200b\0generic-mpc5200";
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		PowerPC,5200@0 {
			device_type = "cpu";
			reg = <0>;
			d-cache-line-size = <20>;
			i-cache-line-size = <20>;
			d-cache-size = <4000>;		// L1, 16K
			i-cache-size = <4000>;		// L1, 16K
			timebase-frequency = <0>;	// from bootloader
			bus-frequency = <0>;		// from bootloader
			clock-frequency = <0>;		// from bootloader
		};
	};

	memory {
		device_type = "memory";
		reg = <00000000 10000000>;	// 256MB
	};

	soc5200@f0000000 {
		model = "fsl,mpc5200b";
		compatible = "mpc5200";
		revision = "";			// from bootloader
		device_type = "soc";
		ranges = <0 f0000000 0000c000>;
		reg = <f0000000 00000100>;
		bus-frequency = <0>;		// from bootloader
		system-frequency = <0>;		// from bootloader

		cdm@200 {
			compatible = "mpc5200b-cdm\0mpc5200-cdm";
			reg = <200 38>;
		};

		mpc5200_pic: pic@500 {
			// 5200 interrupts are encoded into two levels;
			interrupt-controller;
			#interrupt-cells = <3>;
			device_type = "interrupt-controller";
			compatible = "mpc5200b-pic\0mpc5200-pic";
			reg = <500 80>;
		};

		gpt@600 {	// General Purpose Timer
			compatible = "mpc5200b-gpt\0mpc5200-gpt";
			device_type = "gpt";
			cell-index = <0>;
			reg = <600 10>;
			interrupts = <1 9 0>;
			interrupt-parent = <&mpc5200_pic>;
			has-wdt;
		};

		gpt@610 {	// General Purpose Timer
			compatible = "mpc5200b-gpt\0mpc5200-gpt";
			device_type = "gpt";
			cell-index = <1>;
			reg = <610 10>;
			interrupts = <1 a 0>;
			interrupt-parent = <&mpc5200_pic>;
		};

		gpt@620 {	// General Purpose Timer
			compatible = "mpc5200b-gpt\0mpc5200-gpt";
			device_type = "gpt";
			cell-index = <2>;
			reg = <620 10>;
			interrupts = <1 b 0>;
			interrupt-parent = <&mpc5200_pic>;
		};

		gpt@630 {	// General Purpose Timer
			compatible = "mpc5200b-gpt\0mpc5200-gpt";
			device_type = "gpt";
			cell-index = <3>;
			reg = <630 10>;
			interrupts = <1 c 0>;
			interrupt-parent = <&mpc5200_pic>;
		};

		gpt@640 {	// General Purpose Timer
			compatible = "mpc5200b-gpt\0mpc5200-gpt";
			device_type = "gpt";
			cell-index = <4>;
			reg = <640 10>;
			interrupts = <1 d 0>;
			interrupt-parent = <&mpc5200_pic>;
		};

		gpt@650 {	// General Purpose Timer
			compatible = "mpc5200b-gpt\0mpc5200-gpt";
			device_type = "gpt";
			cell-index = <5>;
			reg = <650 10>;
			interrupts = <1 e 0>;
			interrupt-parent = <&mpc5200_pic>;
		};

		gpt@660 {	// General Purpose Timer
			compatible = "mpc5200b-gpt\0mpc5200-gpt";
			device_type = "gpt";
			cell-index = <6>;
			reg = <660 10>;
			interrupts = <1 f 0>;
			interrupt-parent = <&mpc5200_pic>;
		};

		gpt@670 {	// General Purpose Timer
			compatible = "mpc5200b-gpt\0mpc5200-gpt";
			device_type = "gpt";
			cell-index = <7>;
			reg = <670 10>;
			interrupts = <1 10 0>;
			interrupt-parent = <&mpc5200_pic>;
		};

		rtc@800 {	// Real time clock
			compatible = "mpc5200b-rtc\0mpc5200-rtc";
			device_type = "rtc";
			reg = <800 100>;
			interrupts = <1 5 0 1 6 0>;
			interrupt-parent = <&mpc5200_pic>;
		};

		mscan@900 {
			device_type = "mscan";
			compatible = "mpc5200b-mscan\0mpc5200-mscan";
			cell-index = <0>;
			interrupts = <2 11 0>;
			interrupt-parent = <&mpc5200_pic>;
			reg = <900 80>;
		};

		mscan@980 {
			device_type = "mscan";
			compatible = "mpc5200b-mscan\0mpc5200-mscan";
			cell-index = <1>;
			interrupts = <2 12 0>;
			interrupt-parent = <&mpc5200_pic>;
			reg = <980 80>;
		};

		gpio@b00 {
			compatible = "mpc5200b-gpio\0mpc5200-gpio";
			reg = <b00 40>;
			interrupts = <1 7 0>;
			interrupt-parent = <&mpc5200_pic>;
		};

		gpio-wkup@c00 {
			compatible = "mpc5200b-gpio-wkup\0mpc5200-gpio-wkup";
			reg = <c00 40>;
			interrupts = <1 8 0 0 3 0>;
			interrupt-parent = <&mpc5200_pic>;
		};

		pci@0d00 {
			#interrupt-cells = <1>;
			#size-cells = <2>;
			#address-cells = <3>;
			device_type = "pci";
			compatible = "mpc5200b-pci\0mpc5200-pci";
			reg = <d00 100>;
			interrupt-map-mask = <f800 0 0 7>;
			interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
			                 c000 0 0 2 &mpc5200_pic 1 1 3
			                 c000 0 0 3 &mpc5200_pic 1 2 3
			                 c000 0 0 4 &mpc5200_pic 1 3 3

			                 c800 0 0 1 &mpc5200_pic 1 1 3 // 2nd slot
			                 c800 0 0 2 &mpc5200_pic 1 2 3
			                 c800 0 0 3 &mpc5200_pic 1 3 3
			                 c800 0 0 4 &mpc5200_pic 0 0 3>;
			clock-frequency = <0>; // From boot loader
			interrupts = <2 8 0 2 9 0 2 a 0>;
			interrupt-parent = <&mpc5200_pic>;
			bus-range = <0 0>;
			ranges = <42000000 0 80000000 80000000 0 20000000
			          02000000 0 a0000000 a0000000 0 10000000
			          01000000 0 00000000 b0000000 0 01000000>;
		};

		spi@f00 {
			device_type = "spi";
			compatible = "mpc5200b-spi\0mpc5200-spi";
			reg = <f00 20>;
			interrupts = <2 d 0 2 e 0>;
			interrupt-parent = <&mpc5200_pic>;
		};

		usb@1000 {
			device_type = "usb-ohci-be";
			compatible = "mpc5200b-ohci\0mpc5200-ohci\0ohci-be";
			reg = <1000 ff>;
			interrupts = <2 6 0>;
			interrupt-parent = <&mpc5200_pic>;
		};

		bestcomm@1200 {
			device_type = "dma-controller";
			compatible = "mpc5200b-bestcomm\0mpc5200-bestcomm";
			reg = <1200 80>;
			interrupts = <3 0 0  3 1 0  3 2 0  3 3 0
			              3 4 0  3 5 0  3 6 0  3 7 0
			              3 8 0  3 9 0  3 a 0  3 b 0
			              3 c 0  3 d 0  3 e 0  3 f 0>;
			interrupt-parent = <&mpc5200_pic>;
		};

		xlb@1f00 {
			compatible = "mpc5200b-xlb\0mpc5200-xlb";
			reg = <1f00 100>;
		};

		serial@2000 {		// PSC1
			device_type = "serial";
			compatible = "mpc5200b-psc-uart\0mpc5200-psc-uart";
			port-number = <0>;  // Logical port assignment
			cell-index = <0>;
			reg = <2000 100>;
			interrupts = <2 1 0>;
			interrupt-parent = <&mpc5200_pic>;
		};

		// PSC2 in ac97 mode example
		//ac97@2200 {		// PSC2
		//	device_type = "sound";
		//	compatible = "mpc5200b-psc-ac97\0mpc5200-psc-ac97";
		//	cell-index = <1>;
		//	reg = <2200 100>;
		//	interrupts = <2 2 0>;
		//	interrupt-parent = <&mpc5200_pic>;
		//};

		// PSC3 in CODEC mode example
		//i2s@2400 {		// PSC3
		//	device_type = "sound";
		//	compatible = "mpc5200b-psc-i2s"; //not 5200 compatible
		//	cell-index = <2>;
		//	reg = <2400 100>;
		//	interrupts = <2 3 0>;
		//	interrupt-parent = <&mpc5200_pic>;
		//};

		// PSC4 in uart mode example
		//serial@2600 {		// PSC4
		//	device_type = "serial";
		//	compatible = "mpc5200b-psc-uart\0mpc5200-psc-uart";
		//	cell-index = <3>;
		//	reg = <2600 100>;
		//	interrupts = <2 b 0>;
		//	interrupt-parent = <&mpc5200_pic>;
		//};

		// PSC5 in uart mode example
		//serial@2800 {		// PSC5
		//	device_type = "serial";
		//	compatible = "mpc5200b-psc-uart\0mpc5200-psc-uart";
		//	cell-index = <4>;
		//	reg = <2800 100>;
		//	interrupts = <2 c 0>;
		//	interrupt-parent = <&mpc5200_pic>;
		//};

		// PSC6 in spi mode example
		//spi@2c00 {		// PSC6
		//	device_type = "spi";
		//	compatible = "mpc5200b-psc-spi\0mpc5200-psc-spi";
		//	cell-index = <5>;
		//	reg = <2c00 100>;
		//	interrupts = <2 4 0>;
		//	interrupt-parent = <&mpc5200_pic>;
		//};

		ethernet@3000 {
			device_type = "network";
			compatible = "mpc5200b-fec\0mpc5200-fec";
			reg = <3000 800>;
			mac-address = [ 02 03 04 05 06 07 ]; // Bad!
			interrupts = <2 5 0>;
			interrupt-parent = <&mpc5200_pic>;
		};

		ata@3a00 {
			device_type = "ata";
			compatible = "mpc5200b-ata\0mpc5200-ata";
			reg = <3a00 100>;
			interrupts = <2 7 0>;
			interrupt-parent = <&mpc5200_pic>;
		};

		i2c@3d00 {
			device_type = "i2c";
			compatible = "mpc5200b-i2c\0mpc5200-i2c\0fsl-i2c";
			cell-index = <0>;
			reg = <3d00 40>;
			interrupts = <2 f 0>;
			interrupt-parent = <&mpc5200_pic>;
			fsl5200-clocking;
		};

		i2c@3d40 {
			device_type = "i2c";
			compatible = "mpc5200b-i2c\0mpc5200-i2c\0fsl-i2c";
			cell-index = <1>;
			reg = <3d40 40>;
			interrupts = <2 10 0>;
			interrupt-parent = <&mpc5200_pic>;
			fsl5200-clocking;
		};
		sram@8000 {
			device_type = "sram";
			compatible = "mpc5200b-sram\0mpc5200-sram\0sram";
			reg = <8000 4000>;
		};
	};
};
Commit	Line	Data
c6d4d657 GL	1	/*
	2	* Lite5200B board Device Tree Source
	3	*
05cbbc69	4	* Copyright 2006-2007 Secret Lab Technologies Ltd.
c6d4d657 GL	5	* Grant Likely <grant.likely@secretlab.ca>
	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms of the GNU General Public License as published by the
	9	* Free Software Foundation; either version 2 of the License, or (at your
	10	* option) any later version.
	11	*/
	12
121361f7 GL	13	/*
	14	* WARNING: Do not depend on this tree layout remaining static just yet.
	15	* The MPC5200 device tree conventions are still in flux
	16	* Keep an eye on the linuxppc-dev mailing list for more details
	17	*/
	18
c6d4d657	19	/ {
05cbbc69 GL	20	model = "fsl,lite5200b";
	21	// revision = "1.0";
	22	compatible = "fsl,lite5200b\0generic-mpc5200";
c6d4d657 GL	23	#address-cells = <1>;
	24	#size-cells = <1>;
	25
	26	cpus {
c6d4d657 GL	27	#address-cells = <1>;
	28	#size-cells = <0>;
	29
	30	PowerPC,5200@0 {
	31	device_type = "cpu";
	32	reg = <0>;
	33	d-cache-line-size = <20>;
	34	i-cache-line-size = <20>;
	35	d-cache-size = <4000>; // L1, 16K
	36	i-cache-size = <4000>; // L1, 16K
	37	timebase-frequency = <0>; // from bootloader
	38	bus-frequency = <0>; // from bootloader
	39	clock-frequency = <0>; // from bootloader
c6d4d657 GL	40	};
	41	};
	42
	43	memory {
	44	device_type = "memory";
	45	reg = <00000000 10000000>; // 256MB
	46	};
	47
	48	soc5200@f0000000 {
05cbbc69	49	model = "fsl,mpc5200b";
0d0f4bc7	50	compatible = "mpc5200";
05cbbc69	51	revision = ""; // from bootloader
c6d4d657	52	device_type = "soc";
f0c8ac80 KG	53	ranges = <0 f0000000 0000c000>;
f0c8ac80 KG	54	reg = <f0000000 00000100>;
c6d4d657	55	bus-frequency = <0>; // from bootloader
05cbbc69	56	system-frequency = <0>; // from bootloader
c6d4d657 GL	57
c6d4d657 GL	58	cdm@200 {
05cbbc69	59	compatible = "mpc5200b-cdm\0mpc5200-cdm";
c6d4d657 GL	60	reg = <200 38>;
	61	};
	62
5c1992f8	63	mpc5200_pic: pic@500 {
c6d4d657	64	// 5200 interrupts are encoded into two levels;
c6d4d657 GL	65	interrupt-controller;
	66	#interrupt-cells = <3>;
	67	device_type = "interrupt-controller";
f2fb9eb3	68	compatible = "mpc5200b-pic\0mpc5200-pic";
c6d4d657	69	reg = <500 80>;
c6d4d657 GL	70	};
	71
	72	gpt@600 { // General Purpose Timer
05cbbc69	73	compatible = "mpc5200b-gpt\0mpc5200-gpt";
c6d4d657	74	device_type = "gpt";
05cbbc69	75	cell-index = <0>;
c6d4d657 GL	76	reg = <600 10>;
c6d4d657 GL	77	interrupts = <1 9 0>;
5c1992f8	78	interrupt-parent = <&mpc5200_pic>;
05cbbc69	79	has-wdt;
c6d4d657 GL	80	};
	81
	82	gpt@610 { // General Purpose Timer
05cbbc69	83	compatible = "mpc5200b-gpt\0mpc5200-gpt";
c6d4d657	84	device_type = "gpt";
05cbbc69	85	cell-index = <1>;
c6d4d657 GL	86	reg = <610 10>;
c6d4d657 GL	87	interrupts = <1 a 0>;
5c1992f8	88	interrupt-parent = <&mpc5200_pic>;
c6d4d657 GL	89	};
	90
	91	gpt@620 { // General Purpose Timer
05cbbc69	92	compatible = "mpc5200b-gpt\0mpc5200-gpt";
c6d4d657	93	device_type = "gpt";
05cbbc69	94	cell-index = <2>;
c6d4d657 GL	95	reg = <620 10>;
c6d4d657 GL	96	interrupts = <1 b 0>;
5c1992f8	97	interrupt-parent = <&mpc5200_pic>;
c6d4d657 GL	98	};
	99
	100	gpt@630 { // General Purpose Timer
05cbbc69	101	compatible = "mpc5200b-gpt\0mpc5200-gpt";
c6d4d657	102	device_type = "gpt";
05cbbc69	103	cell-index = <3>;
c6d4d657 GL	104	reg = <630 10>;
c6d4d657 GL	105	interrupts = <1 c 0>;
5c1992f8	106	interrupt-parent = <&mpc5200_pic>;
c6d4d657 GL	107	};
	108
	109	gpt@640 { // General Purpose Timer
05cbbc69	110	compatible = "mpc5200b-gpt\0mpc5200-gpt";
c6d4d657	111	device_type = "gpt";
05cbbc69	112	cell-index = <4>;
c6d4d657 GL	113	reg = <640 10>;
c6d4d657 GL	114	interrupts = <1 d 0>;
5c1992f8	115	interrupt-parent = <&mpc5200_pic>;
c6d4d657 GL	116	};
	117
	118	gpt@650 { // General Purpose Timer
05cbbc69	119	compatible = "mpc5200b-gpt\0mpc5200-gpt";
c6d4d657	120	device_type = "gpt";
05cbbc69	121	cell-index = <5>;
c6d4d657 GL	122	reg = <650 10>;
c6d4d657 GL	123	interrupts = <1 e 0>;
5c1992f8	124	interrupt-parent = <&mpc5200_pic>;
c6d4d657 GL	125	};
	126
	127	gpt@660 { // General Purpose Timer
05cbbc69	128	compatible = "mpc5200b-gpt\0mpc5200-gpt";
c6d4d657	129	device_type = "gpt";
05cbbc69	130	cell-index = <6>;
c6d4d657 GL	131	reg = <660 10>;
c6d4d657 GL	132	interrupts = <1 f 0>;
5c1992f8	133	interrupt-parent = <&mpc5200_pic>;
c6d4d657 GL	134	};
	135
	136	gpt@670 { // General Purpose Timer
05cbbc69	137	compatible = "mpc5200b-gpt\0mpc5200-gpt";
c6d4d657	138	device_type = "gpt";
05cbbc69	139	cell-index = <7>;
c6d4d657 GL	140	reg = <670 10>;
c6d4d657 GL	141	interrupts = <1 10 0>;
5c1992f8	142	interrupt-parent = <&mpc5200_pic>;
c6d4d657 GL	143	};
	144
	145	rtc@800 { // Real time clock
05cbbc69	146	compatible = "mpc5200b-rtc\0mpc5200-rtc";
c6d4d657 GL	147	device_type = "rtc";
	148	reg = <800 100>;
	149	interrupts = <1 5 0 1 6 0>;
5c1992f8	150	interrupt-parent = <&mpc5200_pic>;
c6d4d657 GL	151	};
	152
	153	mscan@900 {
	154	device_type = "mscan";
05cbbc69 GL	155	compatible = "mpc5200b-mscan\0mpc5200-mscan";
05cbbc69 GL	156	cell-index = <0>;
c6d4d657	157	interrupts = <2 11 0>;
5c1992f8	158	interrupt-parent = <&mpc5200_pic>;
c6d4d657 GL	159	reg = <900 80>;
	160	};
	161
	162	mscan@980 {
	163	device_type = "mscan";
05cbbc69 GL	164	compatible = "mpc5200b-mscan\0mpc5200-mscan";
05cbbc69 GL	165	cell-index = <1>;
0d0f4bc7	166	interrupts = <2 12 0>;
5c1992f8	167	interrupt-parent = <&mpc5200_pic>;
c6d4d657 GL	168	reg = <980 80>;
	169	};
	170
	171	gpio@b00 {
05cbbc69	172	compatible = "mpc5200b-gpio\0mpc5200-gpio";
c6d4d657 GL	173	reg = <b00 40>;
c6d4d657 GL	174	interrupts = <1 7 0>;
5c1992f8	175	interrupt-parent = <&mpc5200_pic>;
c6d4d657 GL	176	};
c6d4d657 GL	177
0d0f4bc7	178	gpio-wkup@c00 {
05cbbc69	179	compatible = "mpc5200b-gpio-wkup\0mpc5200-gpio-wkup";
c6d4d657 GL	180	reg = <c00 40>;
c6d4d657 GL	181	interrupts = <1 8 0 0 3 0>;
5c1992f8	182	interrupt-parent = <&mpc5200_pic>;
c6d4d657 GL	183	};
	184
	185	pci@0d00 {
	186	#interrupt-cells = <1>;
	187	#size-cells = <2>;
	188	#address-cells = <3>;
	189	device_type = "pci";
05cbbc69	190	compatible = "mpc5200b-pci\0mpc5200-pci";
c6d4d657 GL	191	reg = <d00 100>;
c6d4d657 GL	192	interrupt-map-mask = <f800 0 0 7>;
5c1992f8 KG	193	interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
	194	c000 0 0 2 &mpc5200_pic 1 1 3
	195	c000 0 0 3 &mpc5200_pic 1 2 3
	196	c000 0 0 4 &mpc5200_pic 1 3 3
	197
	198	c800 0 0 1 &mpc5200_pic 1 1 3 // 2nd slot
	199	c800 0 0 2 &mpc5200_pic 1 2 3
	200	c800 0 0 3 &mpc5200_pic 1 3 3
	201	c800 0 0 4 &mpc5200_pic 0 0 3>;
c6d4d657 GL	202	clock-frequency = <0>; // From boot loader
c6d4d657 GL	203	interrupts = <2 8 0 2 9 0 2 a 0>;
5c1992f8	204	interrupt-parent = <&mpc5200_pic>;
c6d4d657 GL	205	bus-range = <0 0>;
	206	ranges = <42000000 0 80000000 80000000 0 20000000
	207	02000000 0 a0000000 a0000000 0 10000000
	208	01000000 0 00000000 b0000000 0 01000000>;
	209	};
	210
	211	spi@f00 {
	212	device_type = "spi";
05cbbc69	213	compatible = "mpc5200b-spi\0mpc5200-spi";
c6d4d657 GL	214	reg = <f00 20>;
c6d4d657 GL	215	interrupts = <2 d 0 2 e 0>;
5c1992f8	216	interrupt-parent = <&mpc5200_pic>;
c6d4d657 GL	217	};
	218
	219	usb@1000 {
	220	device_type = "usb-ohci-be";
05cbbc69	221	compatible = "mpc5200b-ohci\0mpc5200-ohci\0ohci-be";
c6d4d657 GL	222	reg = <1000 ff>;
c6d4d657 GL	223	interrupts = <2 6 0>;
5c1992f8	224	interrupt-parent = <&mpc5200_pic>;
c6d4d657 GL	225	};
	226
	227	bestcomm@1200 {
	228	device_type = "dma-controller";
05cbbc69	229	compatible = "mpc5200b-bestcomm\0mpc5200-bestcomm";
c6d4d657 GL	230	reg = <1200 80>;
	231	interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
	232	3 4 0 3 5 0 3 6 0 3 7 0
	233	3 8 0 3 9 0 3 a 0 3 b 0
	234	3 c 0 3 d 0 3 e 0 3 f 0>;
5c1992f8	235	interrupt-parent = <&mpc5200_pic>;
c6d4d657 GL	236	};
	237
	238	xlb@1f00 {
05cbbc69	239	compatible = "mpc5200b-xlb\0mpc5200-xlb";
c6d4d657 GL	240	reg = <1f00 100>;
	241	};
	242
	243	serial@2000 { // PSC1
	244	device_type = "serial";
05cbbc69	245	compatible = "mpc5200b-psc-uart\0mpc5200-psc-uart";
c6d4d657	246	port-number = <0>; // Logical port assignment
05cbbc69	247	cell-index = <0>;
c6d4d657 GL	248	reg = <2000 100>;
c6d4d657 GL	249	interrupts = <2 1 0>;
5c1992f8	250	interrupt-parent = <&mpc5200_pic>;
c6d4d657 GL	251	};
c6d4d657 GL	252
05cbbc69 GL	253	// PSC2 in ac97 mode example
	254	//ac97@2200 { // PSC2
	255	// device_type = "sound";
	256	// compatible = "mpc5200b-psc-ac97\0mpc5200-psc-ac97";
	257	// cell-index = <1>;
	258	// reg = <2200 100>;
	259	// interrupts = <2 2 0>;
5c1992f8	260	// interrupt-parent = <&mpc5200_pic>;
05cbbc69	261	//};
c6d4d657 GL	262
c6d4d657 GL	263	// PSC3 in CODEC mode example
05cbbc69 GL	264	//i2s@2400 { // PSC3
	265	// device_type = "sound";
	266	// compatible = "mpc5200b-psc-i2s"; //not 5200 compatible
	267	// cell-index = <2>;
	268	// reg = <2400 100>;
	269	// interrupts = <2 3 0>;
5c1992f8	270	// interrupt-parent = <&mpc5200_pic>;
05cbbc69	271	//};
c6d4d657	272
05cbbc69	273	// PSC4 in uart mode example
c6d4d657 GL	274	//serial@2600 { // PSC4
c6d4d657 GL	275	// device_type = "serial";
05cbbc69 GL	276	// compatible = "mpc5200b-psc-uart\0mpc5200-psc-uart";
05cbbc69 GL	277	// cell-index = <3>;
c6d4d657 GL	278	// reg = <2600 100>;
c6d4d657 GL	279	// interrupts = <2 b 0>;
5c1992f8	280	// interrupt-parent = <&mpc5200_pic>;
c6d4d657 GL	281	//};
c6d4d657 GL	282
05cbbc69	283	// PSC5 in uart mode example
c6d4d657 GL	284	//serial@2800 { // PSC5
c6d4d657 GL	285	// device_type = "serial";
05cbbc69 GL	286	// compatible = "mpc5200b-psc-uart\0mpc5200-psc-uart";
05cbbc69 GL	287	// cell-index = <4>;
c6d4d657 GL	288	// reg = <2800 100>;
c6d4d657 GL	289	// interrupts = <2 c 0>;
5c1992f8	290	// interrupt-parent = <&mpc5200_pic>;
c6d4d657 GL	291	//};
c6d4d657 GL	292
05cbbc69 GL	293	// PSC6 in spi mode example
	294	//spi@2c00 { // PSC6
	295	// device_type = "spi";
	296	// compatible = "mpc5200b-psc-spi\0mpc5200-psc-spi";
	297	// cell-index = <5>;
	298	// reg = <2c00 100>;
	299	// interrupts = <2 4 0>;
5c1992f8	300	// interrupt-parent = <&mpc5200_pic>;
05cbbc69	301	//};
c6d4d657 GL	302
	303	ethernet@3000 {
	304	device_type = "network";
05cbbc69	305	compatible = "mpc5200b-fec\0mpc5200-fec";
c6d4d657 GL	306	reg = <3000 800>;
	307	mac-address = [ 02 03 04 05 06 07 ]; // Bad!
	308	interrupts = <2 5 0>;
5c1992f8	309	interrupt-parent = <&mpc5200_pic>;
c6d4d657 GL	310	};
	311
	312	ata@3a00 {
	313	device_type = "ata";
05cbbc69	314	compatible = "mpc5200b-ata\0mpc5200-ata";
c6d4d657 GL	315	reg = <3a00 100>;
c6d4d657 GL	316	interrupts = <2 7 0>;
5c1992f8	317	interrupt-parent = <&mpc5200_pic>;
c6d4d657 GL	318	};
	319
	320	i2c@3d00 {
	321	device_type = "i2c";
5cae84c9	322	compatible = "mpc5200b-i2c\0mpc5200-i2c\0fsl-i2c";
05cbbc69	323	cell-index = <0>;
c6d4d657 GL	324	reg = <3d00 40>;
c6d4d657 GL	325	interrupts = <2 f 0>;
5c1992f8	326	interrupt-parent = <&mpc5200_pic>;
5cae84c9	327	fsl5200-clocking;
c6d4d657 GL	328	};
	329
	330	i2c@3d40 {
	331	device_type = "i2c";
5cae84c9	332	compatible = "mpc5200b-i2c\0mpc5200-i2c\0fsl-i2c";
05cbbc69	333	cell-index = <1>;
c6d4d657 GL	334	reg = <3d40 40>;
c6d4d657 GL	335	interrupts = <2 10 0>;
5c1992f8	336	interrupt-parent = <&mpc5200_pic>;
5cae84c9	337	fsl5200-clocking;
c6d4d657 GL	338	};
	339	sram@8000 {
	340	device_type = "sram";
05cbbc69	341	compatible = "mpc5200b-sram\0mpc5200-sram\0sram";
c6d4d657 GL	342	reg = <8000 4000>;
	343	};
	344	};
	345	};