[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / powerpc / boot / dts / lite5200b.dts

/*
 * Lite5200B board Device Tree Source
 *
 * Copyright 2006 Secret Lab Technologies Ltd.
 * Grant Likely <grant.likely@secretlab.ca>
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

/*
 * WARNING: Do not depend on this tree layout remaining static just yet.
 * The MPC5200 device tree conventions are still in flux
 * Keep an eye on the linuxppc-dev mailing list for more details
 */

/ {
	model = "Lite5200b";
	compatible = "lite5200b\0lite52xx\0mpc5200b\0mpc52xx";
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#cpus = <1>;
		#address-cells = <1>;
		#size-cells = <0>;

		PowerPC,5200@0 {
			device_type = "cpu";
			reg = <0>;
			d-cache-line-size = <20>;
			i-cache-line-size = <20>;
			d-cache-size = <4000>;		// L1, 16K
			i-cache-size = <4000>;		// L1, 16K
			timebase-frequency = <0>;	// from bootloader
			bus-frequency = <0>;		// from bootloader
			clock-frequency = <0>;		// from bootloader
			32-bit;
		};
	};

	memory {
		device_type = "memory";
		reg = <00000000 10000000>;	// 256MB
	};

	soc5200@f0000000 {
		#interrupt-cells = <3>;
		device_type = "soc";
		ranges = <0 f0000000 f0010000>;
		reg = <f0000000 00010000>;
		bus-frequency = <0>;		// from bootloader

		cdm@200 {
			compatible = "mpc5200b-cdm\0mpc52xx-cdm";
			reg = <200 38>;
		};

		pic@500 {
			// 5200 interrupts are encoded into two levels;
			linux,phandle = <500>;
			interrupt-controller;
			#interrupt-cells = <3>;
			device_type = "interrupt-controller";
			compatible = "mpc5200b-pic\0mpc52xx-pic";
			reg = <500 80>;
			built-in;
		};

		gpt@600 {	// General Purpose Timer
			compatible = "mpc5200b-gpt\0mpc52xx-gpt";
			device_type = "gpt";
			reg = <600 10>;
			interrupts = <1 9 0>;
			interrupt-parent = <500>;
		};

		gpt@610 {	// General Purpose Timer
			compatible = "mpc5200b-gpt\0mpc52xx-gpt";
			device_type = "gpt";
			reg = <610 10>;
			interrupts = <1 a 0>;
			interrupt-parent = <500>;
		};

		gpt@620 {	// General Purpose Timer
			compatible = "mpc5200b-gpt\0mpc52xx-gpt";
			device_type = "gpt";
			reg = <620 10>;
			interrupts = <1 b 0>;
			interrupt-parent = <500>;
		};

		gpt@630 {	// General Purpose Timer
			compatible = "mpc5200b-gpt\0mpc52xx-gpt";
			device_type = "gpt";
			reg = <630 10>;
			interrupts = <1 c 0>;
			interrupt-parent = <500>;
		};

		gpt@640 {	// General Purpose Timer
			compatible = "mpc5200b-gpt\0mpc52xx-gpt";
			device_type = "gpt";
			reg = <640 10>;
			interrupts = <1 d 0>;
			interrupt-parent = <500>;
		};

		gpt@650 {	// General Purpose Timer
			compatible = "mpc5200b-gpt\0mpc52xx-gpt";
			device_type = "gpt";
			reg = <650 10>;
			interrupts = <1 e 0>;
			interrupt-parent = <500>;
		};

		gpt@660 {	// General Purpose Timer
			compatible = "mpc5200b-gpt\0mpc52xx-gpt";
			device_type = "gpt";
			reg = <660 10>;
			interrupts = <1 f 0>;
			interrupt-parent = <500>;
		};

		gpt@670 {	// General Purpose Timer
			compatible = "mpc5200b-gpt\0mpc52xx-gpt";
			device_type = "gpt";
			reg = <670 10>;
			interrupts = <1 10 0>;
			interrupt-parent = <500>;
		};

		rtc@800 {	// Real time clock
			compatible = "mpc5200b-rtc\0mpc52xx-rtc";
			device_type = "rtc";
			reg = <800 100>;
			interrupts = <1 5 0 1 6 0>;
			interrupt-parent = <500>;
		};

		mscan@900 {
			device_type = "mscan";
			compatible = "mpc5200b-mscan\0mpc52xx-mscan";
			interrupts = <2 11 0>;
			interrupt-parent = <500>;
			reg = <900 80>;
		};

		mscan@980 {
			device_type = "mscan";
			compatible = "mpc5200b-mscan\0mpc52xx-mscan";
			interrupts = <1 12 0>;
			interrupt-parent = <500>;
			reg = <980 80>;
		};

		gpio@b00 {
			compatible = "mpc5200b-gpio\0mpc52xx-gpio";
			reg = <b00 40>;
			interrupts = <1 7 0>;
			interrupt-parent = <500>;
		};

		gpio-wkup@b00 {
			compatible = "mpc5200b-gpio-wkup\0mpc52xx-gpio-wkup";
			reg = <c00 40>;
			interrupts = <1 8 0 0 3 0>;
			interrupt-parent = <500>;
		};

		pci@0d00 {
			#interrupt-cells = <1>;
			#size-cells = <2>;
			#address-cells = <3>;
			device_type = "pci";
			compatible = "mpc5200b-pci\0mpc52xx-pci";
			reg = <d00 100>;
			interrupt-map-mask = <f800 0 0 7>;
			interrupt-map = <c000 0 0 1 500 0 0 3 // 1st slot
			                 c000 0 0 2 500 1 1 3
			                 c000 0 0 3 500 1 2 3
			                 c000 0 0 4 500 1 3 3

			                 c800 0 0 1 500 1 1 3 // 2nd slot
			                 c800 0 0 2 500 1 2 3
			                 c800 0 0 3 500 1 3 3
			                 c800 0 0 4 500 0 0 3>;
			clock-frequency = <0>; // From boot loader
			interrupts = <2 8 0 2 9 0 2 a 0>;
			interrupt-parent = <500>;
			bus-range = <0 0>;
			ranges = <42000000 0 80000000 80000000 0 20000000
			          02000000 0 a0000000 a0000000 0 10000000
			          01000000 0 00000000 b0000000 0 01000000>;
		};

		spi@f00 {
			device_type = "spi";
			compatible = "mpc5200b-spi\0mpc52xx-spi";
			reg = <f00 20>;
			interrupts = <2 d 0 2 e 0>;
			interrupt-parent = <500>;
		};

		usb@1000 {
			device_type = "usb-ohci-be";
			compatible = "mpc5200b-ohci\0mpc52xx-ohci\0ohci-be";
			reg = <1000 ff>;
			interrupts = <2 6 0>;
			interrupt-parent = <500>;
		};

		bestcomm@1200 {
			device_type = "dma-controller";
			compatible = "mpc5200b-bestcomm\0mpc52xx-bestcomm";
			reg = <1200 80>;
			interrupts = <3 0 0  3 1 0  3 2 0  3 3 0
			              3 4 0  3 5 0  3 6 0  3 7 0
			              3 8 0  3 9 0  3 a 0  3 b 0
			              3 c 0  3 d 0  3 e 0  3 f 0>;
			interrupt-parent = <500>;
		};

		xlb@1f00 {
			compatible = "mpc5200b-xlb\0mpc52xx-xlb";
			reg = <1f00 100>;
		};

		serial@2000 {		// PSC1
			device_type = "serial";
			compatible = "mpc5200b-psc-uart\0mpc52xx-psc-uart";
			port-number = <0>;  // Logical port assignment
			reg = <2000 100>;
			interrupts = <2 1 0>;
			interrupt-parent = <500>;
		};

		// PSC2 in spi mode example
		spi@2200 {		// PSC2
			device_type = "spi";
			compatible = "mpc5200b-psc-spi\0mpc52xx-psc-spi";
			reg = <2200 100>;
			interrupts = <2 2 0>;
			interrupt-parent = <500>;
		};

		// PSC3 in CODEC mode example
		i2s@2400 {		// PSC3
			device_type = "sound";
			compatible = "mpc5200b-psc-i2s\0mpc52xx-psc-i2s";
			reg = <2400 100>;
			interrupts = <2 3 0>;
			interrupt-parent = <500>;
		};

		// PSC4 unconfigured
		//serial@2600 {		// PSC4
		//	device_type = "serial";
		//	compatible = "mpc5200b-psc-uart\0mpc52xx-psc-uart";
		//	reg = <2600 100>;
		//	interrupts = <2 b 0>;
		//	interrupt-parent = <500>;
		//};

		// PSC5 unconfigured
		//serial@2800 {		// PSC5
		//	device_type = "serial";
		//	compatible = "mpc5200b-psc-uart\0mpc52xx-psc-uart";
		//	reg = <2800 100>;
		//	interrupts = <2 c 0>;
		//	interrupt-parent = <500>;
		//};

		// PSC6 in AC97 mode example
		ac97@2c00 {		// PSC6
			device_type = "sound";
			compatible = "mpc5200b-psc-ac97\0mpc52xx-psc-ac97";
			reg = <2c00 100>;
			interrupts = <2 4 0>;
			interrupt-parent = <500>;
		};

		ethernet@3000 {
			device_type = "network";
			compatible = "mpc5200b-fec\0mpc52xx-fec";
			reg = <3000 800>;
			mac-address = [ 02 03 04 05 06 07 ]; // Bad!
			interrupts = <2 5 0>;
			interrupt-parent = <500>;
		};

		ata@3a00 {
			device_type = "ata";
			compatible = "mpc5200b-ata\0mpc52xx-ata";
			reg = <3a00 100>;
			interrupts = <2 7 0>;
			interrupt-parent = <500>;
		};

		i2c@3d00 {
			device_type = "i2c";
			compatible = "mpc5200b-i2c\0mpc52xx-i2c";
			reg = <3d00 40>;
			interrupts = <2 f 0>;
			interrupt-parent = <500>;
		};

		i2c@3d40 {
			device_type = "i2c";
			compatible = "mpc5200b-i2c\0mpc52xx-i2c";
			reg = <3d40 40>;
			interrupts = <2 10 0>;
			interrupt-parent = <500>;
		};
		sram@8000 {
			device_type = "sram";
			compatible = "mpc5200b-sram\0mpc52xx-sram\0sram";
			reg = <8000 4000>;
		};
	};
};
Commit	Line	Data
c6d4d657 GL	1	/*
	2	* Lite5200B board Device Tree Source
	3	*
	4	* Copyright 2006 Secret Lab Technologies Ltd.
	5	* Grant Likely <grant.likely@secretlab.ca>
	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms of the GNU General Public License as published by the
	9	* Free Software Foundation; either version 2 of the License, or (at your
	10	* option) any later version.
	11	*/
	12
121361f7 GL	13	/*
	14	* WARNING: Do not depend on this tree layout remaining static just yet.
	15	* The MPC5200 device tree conventions are still in flux
	16	* Keep an eye on the linuxppc-dev mailing list for more details
	17	*/
	18
c6d4d657 GL	19	/ {
	20	model = "Lite5200b";
	21	compatible = "lite5200b\0lite52xx\0mpc5200b\0mpc52xx";
	22	#address-cells = <1>;
	23	#size-cells = <1>;
	24
	25	cpus {
	26	#cpus = <1>;
	27	#address-cells = <1>;
	28	#size-cells = <0>;
	29
	30	PowerPC,5200@0 {
	31	device_type = "cpu";
	32	reg = <0>;
	33	d-cache-line-size = <20>;
	34	i-cache-line-size = <20>;
	35	d-cache-size = <4000>; // L1, 16K
	36	i-cache-size = <4000>; // L1, 16K
	37	timebase-frequency = <0>; // from bootloader
	38	bus-frequency = <0>; // from bootloader
	39	clock-frequency = <0>; // from bootloader
	40	32-bit;
	41	};
	42	};
	43
	44	memory {
	45	device_type = "memory";
	46	reg = <00000000 10000000>; // 256MB
	47	};
	48
	49	soc5200@f0000000 {
	50	#interrupt-cells = <3>;
	51	device_type = "soc";
	52	ranges = <0 f0000000 f0010000>;
	53	reg = <f0000000 00010000>;
	54	bus-frequency = <0>; // from bootloader
	55
	56	cdm@200 {
	57	compatible = "mpc5200b-cdm\0mpc52xx-cdm";
	58	reg = <200 38>;
	59	};
	60
	61	pic@500 {
	62	// 5200 interrupts are encoded into two levels;
	63	linux,phandle = <500>;
	64	interrupt-controller;
	65	#interrupt-cells = <3>;
	66	device_type = "interrupt-controller";
	67	compatible = "mpc5200b-pic\0mpc52xx-pic";
	68	reg = <500 80>;
	69	built-in;
	70	};
	71
	72	gpt@600 { // General Purpose Timer
	73	compatible = "mpc5200b-gpt\0mpc52xx-gpt";
	74	device_type = "gpt";
	75	reg = <600 10>;
	76	interrupts = <1 9 0>;
	77	interrupt-parent = <500>;
	78	};
	79
	80	gpt@610 { // General Purpose Timer
	81	compatible = "mpc5200b-gpt\0mpc52xx-gpt";
	82	device_type = "gpt";
83	reg = <610 10>;
84	interrupts = <1 a 0>;
85	interrupt-parent = <500>;
86	};
87
88	gpt@620 { // General Purpose Timer
89	compatible = "mpc5200b-gpt\0mpc52xx-gpt";
90	device_type = "gpt";
91	reg = <620 10>;
92	interrupts = <1 b 0>;
93	interrupt-parent = <500>;
94	};
95
96	gpt@630 { // General Purpose Timer
97	compatible = "mpc5200b-gpt\0mpc52xx-gpt";
98	device_type = "gpt";
99	reg = <630 10>;
100	interrupts = <1 c 0>;
101	interrupt-parent = <500>;
102	};
103
104	gpt@640 { // General Purpose Timer
105	compatible = "mpc5200b-gpt\0mpc52xx-gpt";
106	device_type = "gpt";
107	reg = <640 10>;
108	interrupts = <1 d 0>;
109	interrupt-parent = <500>;
110	};
111
112	gpt@650 { // General Purpose Timer
113	compatible = "mpc5200b-gpt\0mpc52xx-gpt";
114	device_type = "gpt";
115	reg = <650 10>;
116	interrupts = <1 e 0>;
117	interrupt-parent = <500>;
118	};
119
120	gpt@660 { // General Purpose Timer
121	compatible = "mpc5200b-gpt\0mpc52xx-gpt";
122	device_type = "gpt";
123	reg = <660 10>;
124	interrupts = <1 f 0>;
125	interrupt-parent = <500>;
126	};
127
128	gpt@670 { // General Purpose Timer
129	compatible = "mpc5200b-gpt\0mpc52xx-gpt";
130	device_type = "gpt";
131	reg = <670 10>;
132	interrupts = <1 10 0>;
133	interrupt-parent = <500>;
134	};
135
136	rtc@800 { // Real time clock
137	compatible = "mpc5200b-rtc\0mpc52xx-rtc";
138	device_type = "rtc";
139	reg = <800 100>;
140	interrupts = <1 5 0 1 6 0>;
141	interrupt-parent = <500>;
142	};
143
144	mscan@900 {
145	device_type = "mscan";
146	compatible = "mpc5200b-mscan\0mpc52xx-mscan";
147	interrupts = <2 11 0>;
148	interrupt-parent = <500>;
149	reg = <900 80>;
150	};
151
152	mscan@980 {
153	device_type = "mscan";
154	compatible = "mpc5200b-mscan\0mpc52xx-mscan";
155	interrupts = <1 12 0>;
156	interrupt-parent = <500>;
157	reg = <980 80>;
158	};
159
160	gpio@b00 {
161	compatible = "mpc5200b-gpio\0mpc52xx-gpio";
162	reg = <b00 40>;
163	interrupts = <1 7 0>;
164	interrupt-parent = <500>;
165	};
166
167	gpio-wkup@b00 {
168	compatible = "mpc5200b-gpio-wkup\0mpc52xx-gpio-wkup";
169	reg = <c00 40>;
170	interrupts = <1 8 0 0 3 0>;
171	interrupt-parent = <500>;
172	};
173
174	pci@0d00 {
175	#interrupt-cells = <1>;
176	#size-cells = <2>;
177	#address-cells = <3>;
178	device_type = "pci";
179	compatible = "mpc5200b-pci\0mpc52xx-pci";
180	reg = <d00 100>;
181	interrupt-map-mask = <f800 0 0 7>;
182	interrupt-map = <c000 0 0 1 500 0 0 3 // 1st slot
183	c000 0 0 2 500 1 1 3
184	c000 0 0 3 500 1 2 3
185	c000 0 0 4 500 1 3 3
186
187	c800 0 0 1 500 1 1 3 // 2nd slot
188	c800 0 0 2 500 1 2 3
189	c800 0 0 3 500 1 3 3
190	c800 0 0 4 500 0 0 3>;
191	clock-frequency = <0>; // From boot loader
192	interrupts = <2 8 0 2 9 0 2 a 0>;
193	interrupt-parent = <500>;
194	bus-range = <0 0>;
195	ranges = <42000000 0 80000000 80000000 0 20000000
196	02000000 0 a0000000 a0000000 0 10000000
197	01000000 0 00000000 b0000000 0 01000000>;
198	};
199
200	spi@f00 {
201	device_type = "spi";
202	compatible = "mpc5200b-spi\0mpc52xx-spi";
203	reg = <f00 20>;
204	interrupts = <2 d 0 2 e 0>;
205	interrupt-parent = <500>;
206	};
207
208	usb@1000 {
209	device_type = "usb-ohci-be";
210	compatible = "mpc5200b-ohci\0mpc52xx-ohci\0ohci-be";
211	reg = <1000 ff>;
212	interrupts = <2 6 0>;
213	interrupt-parent = <500>;
214	};
215
216	bestcomm@1200 {
217	device_type = "dma-controller";
218	compatible = "mpc5200b-bestcomm\0mpc52xx-bestcomm";
219	reg = <1200 80>;
220	interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
221	3 4 0 3 5 0 3 6 0 3 7 0
222	3 8 0 3 9 0 3 a 0 3 b 0
223	3 c 0 3 d 0 3 e 0 3 f 0>;
224	interrupt-parent = <500>;
225	};
226
227	xlb@1f00 {
228	compatible = "mpc5200b-xlb\0mpc52xx-xlb";
229	reg = <1f00 100>;
230	};
231
232	serial@2000 { // PSC1
233	device_type = "serial";
234	compatible = "mpc5200b-psc-uart\0mpc52xx-psc-uart";
235	port-number = <0>; // Logical port assignment
236	reg = <2000 100>;
237	interrupts = <2 1 0>;
238	interrupt-parent = <500>;
239	};
240
241	// PSC2 in spi mode example
242	spi@2200 { // PSC2
243	device_type = "spi";
244	compatible = "mpc5200b-psc-spi\0mpc52xx-psc-spi";
245	reg = <2200 100>;
246	interrupts = <2 2 0>;
247	interrupt-parent = <500>;
248	};
249
250	// PSC3 in CODEC mode example
251	i2s@2400 { // PSC3
a5b6ad66	252	device_type = "sound";
c6d4d657 GL	253	compatible = "mpc5200b-psc-i2s\0mpc52xx-psc-i2s";
	254	reg = <2400 100>;
	255	interrupts = <2 3 0>;
	256	interrupt-parent = <500>;
	257	};
	258
	259	// PSC4 unconfigured
	260	//serial@2600 { // PSC4
	261	// device_type = "serial";
	262	// compatible = "mpc5200b-psc-uart\0mpc52xx-psc-uart";
	263	// reg = <2600 100>;
	264	// interrupts = <2 b 0>;
	265	// interrupt-parent = <500>;
	266	//};
	267
	268	// PSC5 unconfigured
	269	//serial@2800 { // PSC5
	270	// device_type = "serial";
	271	// compatible = "mpc5200b-psc-uart\0mpc52xx-psc-uart";
	272	// reg = <2800 100>;
	273	// interrupts = <2 c 0>;
	274	// interrupt-parent = <500>;
	275	//};
	276
	277	// PSC6 in AC97 mode example
	278	ac97@2c00 { // PSC6
a5b6ad66	279	device_type = "sound";
c6d4d657 GL	280	compatible = "mpc5200b-psc-ac97\0mpc52xx-psc-ac97";
	281	reg = <2c00 100>;
	282	interrupts = <2 4 0>;
	283	interrupt-parent = <500>;
	284	};
	285
	286	ethernet@3000 {
	287	device_type = "network";
	288	compatible = "mpc5200b-fec\0mpc52xx-fec";
	289	reg = <3000 800>;
	290	mac-address = [ 02 03 04 05 06 07 ]; // Bad!
	291	interrupts = <2 5 0>;
	292	interrupt-parent = <500>;
	293	};
	294
	295	ata@3a00 {
	296	device_type = "ata";
	297	compatible = "mpc5200b-ata\0mpc52xx-ata";
	298	reg = <3a00 100>;
	299	interrupts = <2 7 0>;
	300	interrupt-parent = <500>;
	301	};
	302
	303	i2c@3d00 {
	304	device_type = "i2c";
	305	compatible = "mpc5200b-i2c\0mpc52xx-i2c";
	306	reg = <3d00 40>;
	307	interrupts = <2 f 0>;
	308	interrupt-parent = <500>;
	309	};
	310
	311	i2c@3d40 {
	312	device_type = "i2c";
	313	compatible = "mpc5200b-i2c\0mpc52xx-i2c";
	314	reg = <3d40 40>;
	315	interrupts = <2 10 0>;
	316	interrupt-parent = <500>;
	317	};
	318	sram@8000 {
	319	device_type = "sram";
	320	compatible = "mpc5200b-sram\0mpc52xx-sram\0sram";
	321	reg = <8000 4000>;
	322	};
	323	};
	324	};