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c6d4d657 GL |
1 | /* |
2 | * Lite5200B board Device Tree Source | |
3 | * | |
05cbbc69 | 4 | * Copyright 2006-2007 Secret Lab Technologies Ltd. |
c6d4d657 GL |
5 | * Grant Likely <grant.likely@secretlab.ca> |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License as published by the | |
9 | * Free Software Foundation; either version 2 of the License, or (at your | |
10 | * option) any later version. | |
11 | */ | |
12 | ||
121361f7 GL |
13 | /* |
14 | * WARNING: Do not depend on this tree layout remaining static just yet. | |
15 | * The MPC5200 device tree conventions are still in flux | |
16 | * Keep an eye on the linuxppc-dev mailing list for more details | |
17 | */ | |
18 | ||
c6d4d657 | 19 | / { |
05cbbc69 GL |
20 | model = "fsl,lite5200b"; |
21 | // revision = "1.0"; | |
22 | compatible = "fsl,lite5200b\0generic-mpc5200"; | |
c6d4d657 GL |
23 | #address-cells = <1>; |
24 | #size-cells = <1>; | |
25 | ||
26 | cpus { | |
c6d4d657 GL |
27 | #address-cells = <1>; |
28 | #size-cells = <0>; | |
29 | ||
30 | PowerPC,5200@0 { | |
31 | device_type = "cpu"; | |
32 | reg = <0>; | |
33 | d-cache-line-size = <20>; | |
34 | i-cache-line-size = <20>; | |
35 | d-cache-size = <4000>; // L1, 16K | |
36 | i-cache-size = <4000>; // L1, 16K | |
37 | timebase-frequency = <0>; // from bootloader | |
38 | bus-frequency = <0>; // from bootloader | |
39 | clock-frequency = <0>; // from bootloader | |
40 | 32-bit; | |
41 | }; | |
42 | }; | |
43 | ||
44 | memory { | |
45 | device_type = "memory"; | |
46 | reg = <00000000 10000000>; // 256MB | |
47 | }; | |
48 | ||
49 | soc5200@f0000000 { | |
05cbbc69 | 50 | model = "fsl,mpc5200b"; |
0d0f4bc7 | 51 | compatible = "mpc5200"; |
05cbbc69 | 52 | revision = ""; // from bootloader |
c6d4d657 GL |
53 | #interrupt-cells = <3>; |
54 | device_type = "soc"; | |
55 | ranges = <0 f0000000 f0010000>; | |
56 | reg = <f0000000 00010000>; | |
57 | bus-frequency = <0>; // from bootloader | |
05cbbc69 | 58 | system-frequency = <0>; // from bootloader |
c6d4d657 GL |
59 | |
60 | cdm@200 { | |
05cbbc69 | 61 | compatible = "mpc5200b-cdm\0mpc5200-cdm"; |
c6d4d657 GL |
62 | reg = <200 38>; |
63 | }; | |
64 | ||
5c1992f8 | 65 | mpc5200_pic: pic@500 { |
c6d4d657 | 66 | // 5200 interrupts are encoded into two levels; |
c6d4d657 GL |
67 | interrupt-controller; |
68 | #interrupt-cells = <3>; | |
69 | device_type = "interrupt-controller"; | |
f2fb9eb3 | 70 | compatible = "mpc5200b-pic\0mpc5200-pic"; |
c6d4d657 GL |
71 | reg = <500 80>; |
72 | built-in; | |
73 | }; | |
74 | ||
75 | gpt@600 { // General Purpose Timer | |
05cbbc69 | 76 | compatible = "mpc5200b-gpt\0mpc5200-gpt"; |
c6d4d657 | 77 | device_type = "gpt"; |
05cbbc69 | 78 | cell-index = <0>; |
c6d4d657 GL |
79 | reg = <600 10>; |
80 | interrupts = <1 9 0>; | |
5c1992f8 | 81 | interrupt-parent = <&mpc5200_pic>; |
05cbbc69 | 82 | has-wdt; |
c6d4d657 GL |
83 | }; |
84 | ||
85 | gpt@610 { // General Purpose Timer | |
05cbbc69 | 86 | compatible = "mpc5200b-gpt\0mpc5200-gpt"; |
c6d4d657 | 87 | device_type = "gpt"; |
05cbbc69 | 88 | cell-index = <1>; |
c6d4d657 GL |
89 | reg = <610 10>; |
90 | interrupts = <1 a 0>; | |
5c1992f8 | 91 | interrupt-parent = <&mpc5200_pic>; |
c6d4d657 GL |
92 | }; |
93 | ||
94 | gpt@620 { // General Purpose Timer | |
05cbbc69 | 95 | compatible = "mpc5200b-gpt\0mpc5200-gpt"; |
c6d4d657 | 96 | device_type = "gpt"; |
05cbbc69 | 97 | cell-index = <2>; |
c6d4d657 GL |
98 | reg = <620 10>; |
99 | interrupts = <1 b 0>; | |
5c1992f8 | 100 | interrupt-parent = <&mpc5200_pic>; |
c6d4d657 GL |
101 | }; |
102 | ||
103 | gpt@630 { // General Purpose Timer | |
05cbbc69 | 104 | compatible = "mpc5200b-gpt\0mpc5200-gpt"; |
c6d4d657 | 105 | device_type = "gpt"; |
05cbbc69 | 106 | cell-index = <3>; |
c6d4d657 GL |
107 | reg = <630 10>; |
108 | interrupts = <1 c 0>; | |
5c1992f8 | 109 | interrupt-parent = <&mpc5200_pic>; |
c6d4d657 GL |
110 | }; |
111 | ||
112 | gpt@640 { // General Purpose Timer | |
05cbbc69 | 113 | compatible = "mpc5200b-gpt\0mpc5200-gpt"; |
c6d4d657 | 114 | device_type = "gpt"; |
05cbbc69 | 115 | cell-index = <4>; |
c6d4d657 GL |
116 | reg = <640 10>; |
117 | interrupts = <1 d 0>; | |
5c1992f8 | 118 | interrupt-parent = <&mpc5200_pic>; |
c6d4d657 GL |
119 | }; |
120 | ||
121 | gpt@650 { // General Purpose Timer | |
05cbbc69 | 122 | compatible = "mpc5200b-gpt\0mpc5200-gpt"; |
c6d4d657 | 123 | device_type = "gpt"; |
05cbbc69 | 124 | cell-index = <5>; |
c6d4d657 GL |
125 | reg = <650 10>; |
126 | interrupts = <1 e 0>; | |
5c1992f8 | 127 | interrupt-parent = <&mpc5200_pic>; |
c6d4d657 GL |
128 | }; |
129 | ||
130 | gpt@660 { // General Purpose Timer | |
05cbbc69 | 131 | compatible = "mpc5200b-gpt\0mpc5200-gpt"; |
c6d4d657 | 132 | device_type = "gpt"; |
05cbbc69 | 133 | cell-index = <6>; |
c6d4d657 GL |
134 | reg = <660 10>; |
135 | interrupts = <1 f 0>; | |
5c1992f8 | 136 | interrupt-parent = <&mpc5200_pic>; |
c6d4d657 GL |
137 | }; |
138 | ||
139 | gpt@670 { // General Purpose Timer | |
05cbbc69 | 140 | compatible = "mpc5200b-gpt\0mpc5200-gpt"; |
c6d4d657 | 141 | device_type = "gpt"; |
05cbbc69 | 142 | cell-index = <7>; |
c6d4d657 GL |
143 | reg = <670 10>; |
144 | interrupts = <1 10 0>; | |
5c1992f8 | 145 | interrupt-parent = <&mpc5200_pic>; |
c6d4d657 GL |
146 | }; |
147 | ||
148 | rtc@800 { // Real time clock | |
05cbbc69 | 149 | compatible = "mpc5200b-rtc\0mpc5200-rtc"; |
c6d4d657 GL |
150 | device_type = "rtc"; |
151 | reg = <800 100>; | |
152 | interrupts = <1 5 0 1 6 0>; | |
5c1992f8 | 153 | interrupt-parent = <&mpc5200_pic>; |
c6d4d657 GL |
154 | }; |
155 | ||
156 | mscan@900 { | |
157 | device_type = "mscan"; | |
05cbbc69 GL |
158 | compatible = "mpc5200b-mscan\0mpc5200-mscan"; |
159 | cell-index = <0>; | |
c6d4d657 | 160 | interrupts = <2 11 0>; |
5c1992f8 | 161 | interrupt-parent = <&mpc5200_pic>; |
c6d4d657 GL |
162 | reg = <900 80>; |
163 | }; | |
164 | ||
165 | mscan@980 { | |
166 | device_type = "mscan"; | |
05cbbc69 GL |
167 | compatible = "mpc5200b-mscan\0mpc5200-mscan"; |
168 | cell-index = <1>; | |
0d0f4bc7 | 169 | interrupts = <2 12 0>; |
5c1992f8 | 170 | interrupt-parent = <&mpc5200_pic>; |
c6d4d657 GL |
171 | reg = <980 80>; |
172 | }; | |
173 | ||
174 | gpio@b00 { | |
05cbbc69 | 175 | compatible = "mpc5200b-gpio\0mpc5200-gpio"; |
c6d4d657 GL |
176 | reg = <b00 40>; |
177 | interrupts = <1 7 0>; | |
5c1992f8 | 178 | interrupt-parent = <&mpc5200_pic>; |
c6d4d657 GL |
179 | }; |
180 | ||
0d0f4bc7 | 181 | gpio-wkup@c00 { |
05cbbc69 | 182 | compatible = "mpc5200b-gpio-wkup\0mpc5200-gpio-wkup"; |
c6d4d657 GL |
183 | reg = <c00 40>; |
184 | interrupts = <1 8 0 0 3 0>; | |
5c1992f8 | 185 | interrupt-parent = <&mpc5200_pic>; |
c6d4d657 GL |
186 | }; |
187 | ||
188 | pci@0d00 { | |
189 | #interrupt-cells = <1>; | |
190 | #size-cells = <2>; | |
191 | #address-cells = <3>; | |
192 | device_type = "pci"; | |
05cbbc69 | 193 | compatible = "mpc5200b-pci\0mpc5200-pci"; |
c6d4d657 GL |
194 | reg = <d00 100>; |
195 | interrupt-map-mask = <f800 0 0 7>; | |
5c1992f8 KG |
196 | interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot |
197 | c000 0 0 2 &mpc5200_pic 1 1 3 | |
198 | c000 0 0 3 &mpc5200_pic 1 2 3 | |
199 | c000 0 0 4 &mpc5200_pic 1 3 3 | |
200 | ||
201 | c800 0 0 1 &mpc5200_pic 1 1 3 // 2nd slot | |
202 | c800 0 0 2 &mpc5200_pic 1 2 3 | |
203 | c800 0 0 3 &mpc5200_pic 1 3 3 | |
204 | c800 0 0 4 &mpc5200_pic 0 0 3>; | |
c6d4d657 GL |
205 | clock-frequency = <0>; // From boot loader |
206 | interrupts = <2 8 0 2 9 0 2 a 0>; | |
5c1992f8 | 207 | interrupt-parent = <&mpc5200_pic>; |
c6d4d657 GL |
208 | bus-range = <0 0>; |
209 | ranges = <42000000 0 80000000 80000000 0 20000000 | |
210 | 02000000 0 a0000000 a0000000 0 10000000 | |
211 | 01000000 0 00000000 b0000000 0 01000000>; | |
212 | }; | |
213 | ||
214 | spi@f00 { | |
215 | device_type = "spi"; | |
05cbbc69 | 216 | compatible = "mpc5200b-spi\0mpc5200-spi"; |
c6d4d657 GL |
217 | reg = <f00 20>; |
218 | interrupts = <2 d 0 2 e 0>; | |
5c1992f8 | 219 | interrupt-parent = <&mpc5200_pic>; |
c6d4d657 GL |
220 | }; |
221 | ||
222 | usb@1000 { | |
223 | device_type = "usb-ohci-be"; | |
05cbbc69 | 224 | compatible = "mpc5200b-ohci\0mpc5200-ohci\0ohci-be"; |
c6d4d657 GL |
225 | reg = <1000 ff>; |
226 | interrupts = <2 6 0>; | |
5c1992f8 | 227 | interrupt-parent = <&mpc5200_pic>; |
c6d4d657 GL |
228 | }; |
229 | ||
230 | bestcomm@1200 { | |
231 | device_type = "dma-controller"; | |
05cbbc69 | 232 | compatible = "mpc5200b-bestcomm\0mpc5200-bestcomm"; |
c6d4d657 GL |
233 | reg = <1200 80>; |
234 | interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 | |
235 | 3 4 0 3 5 0 3 6 0 3 7 0 | |
236 | 3 8 0 3 9 0 3 a 0 3 b 0 | |
237 | 3 c 0 3 d 0 3 e 0 3 f 0>; | |
5c1992f8 | 238 | interrupt-parent = <&mpc5200_pic>; |
c6d4d657 GL |
239 | }; |
240 | ||
241 | xlb@1f00 { | |
05cbbc69 | 242 | compatible = "mpc5200b-xlb\0mpc5200-xlb"; |
c6d4d657 GL |
243 | reg = <1f00 100>; |
244 | }; | |
245 | ||
246 | serial@2000 { // PSC1 | |
247 | device_type = "serial"; | |
05cbbc69 | 248 | compatible = "mpc5200b-psc-uart\0mpc5200-psc-uart"; |
c6d4d657 | 249 | port-number = <0>; // Logical port assignment |
05cbbc69 | 250 | cell-index = <0>; |
c6d4d657 GL |
251 | reg = <2000 100>; |
252 | interrupts = <2 1 0>; | |
5c1992f8 | 253 | interrupt-parent = <&mpc5200_pic>; |
c6d4d657 GL |
254 | }; |
255 | ||
05cbbc69 GL |
256 | // PSC2 in ac97 mode example |
257 | //ac97@2200 { // PSC2 | |
258 | // device_type = "sound"; | |
259 | // compatible = "mpc5200b-psc-ac97\0mpc5200-psc-ac97"; | |
260 | // cell-index = <1>; | |
261 | // reg = <2200 100>; | |
262 | // interrupts = <2 2 0>; | |
5c1992f8 | 263 | // interrupt-parent = <&mpc5200_pic>; |
05cbbc69 | 264 | //}; |
c6d4d657 GL |
265 | |
266 | // PSC3 in CODEC mode example | |
05cbbc69 GL |
267 | //i2s@2400 { // PSC3 |
268 | // device_type = "sound"; | |
269 | // compatible = "mpc5200b-psc-i2s"; //not 5200 compatible | |
270 | // cell-index = <2>; | |
271 | // reg = <2400 100>; | |
272 | // interrupts = <2 3 0>; | |
5c1992f8 | 273 | // interrupt-parent = <&mpc5200_pic>; |
05cbbc69 | 274 | //}; |
c6d4d657 | 275 | |
05cbbc69 | 276 | // PSC4 in uart mode example |
c6d4d657 GL |
277 | //serial@2600 { // PSC4 |
278 | // device_type = "serial"; | |
05cbbc69 GL |
279 | // compatible = "mpc5200b-psc-uart\0mpc5200-psc-uart"; |
280 | // cell-index = <3>; | |
c6d4d657 GL |
281 | // reg = <2600 100>; |
282 | // interrupts = <2 b 0>; | |
5c1992f8 | 283 | // interrupt-parent = <&mpc5200_pic>; |
c6d4d657 GL |
284 | //}; |
285 | ||
05cbbc69 | 286 | // PSC5 in uart mode example |
c6d4d657 GL |
287 | //serial@2800 { // PSC5 |
288 | // device_type = "serial"; | |
05cbbc69 GL |
289 | // compatible = "mpc5200b-psc-uart\0mpc5200-psc-uart"; |
290 | // cell-index = <4>; | |
c6d4d657 GL |
291 | // reg = <2800 100>; |
292 | // interrupts = <2 c 0>; | |
5c1992f8 | 293 | // interrupt-parent = <&mpc5200_pic>; |
c6d4d657 GL |
294 | //}; |
295 | ||
05cbbc69 GL |
296 | // PSC6 in spi mode example |
297 | //spi@2c00 { // PSC6 | |
298 | // device_type = "spi"; | |
299 | // compatible = "mpc5200b-psc-spi\0mpc5200-psc-spi"; | |
300 | // cell-index = <5>; | |
301 | // reg = <2c00 100>; | |
302 | // interrupts = <2 4 0>; | |
5c1992f8 | 303 | // interrupt-parent = <&mpc5200_pic>; |
05cbbc69 | 304 | //}; |
c6d4d657 GL |
305 | |
306 | ethernet@3000 { | |
307 | device_type = "network"; | |
05cbbc69 | 308 | compatible = "mpc5200b-fec\0mpc5200-fec"; |
c6d4d657 GL |
309 | reg = <3000 800>; |
310 | mac-address = [ 02 03 04 05 06 07 ]; // Bad! | |
311 | interrupts = <2 5 0>; | |
5c1992f8 | 312 | interrupt-parent = <&mpc5200_pic>; |
c6d4d657 GL |
313 | }; |
314 | ||
315 | ata@3a00 { | |
316 | device_type = "ata"; | |
05cbbc69 | 317 | compatible = "mpc5200b-ata\0mpc5200-ata"; |
c6d4d657 GL |
318 | reg = <3a00 100>; |
319 | interrupts = <2 7 0>; | |
5c1992f8 | 320 | interrupt-parent = <&mpc5200_pic>; |
c6d4d657 GL |
321 | }; |
322 | ||
323 | i2c@3d00 { | |
324 | device_type = "i2c"; | |
5cae84c9 | 325 | compatible = "mpc5200b-i2c\0mpc5200-i2c\0fsl-i2c"; |
05cbbc69 | 326 | cell-index = <0>; |
c6d4d657 GL |
327 | reg = <3d00 40>; |
328 | interrupts = <2 f 0>; | |
5c1992f8 | 329 | interrupt-parent = <&mpc5200_pic>; |
5cae84c9 | 330 | fsl5200-clocking; |
c6d4d657 GL |
331 | }; |
332 | ||
333 | i2c@3d40 { | |
334 | device_type = "i2c"; | |
5cae84c9 | 335 | compatible = "mpc5200b-i2c\0mpc5200-i2c\0fsl-i2c"; |
05cbbc69 | 336 | cell-index = <1>; |
c6d4d657 GL |
337 | reg = <3d40 40>; |
338 | interrupts = <2 10 0>; | |
5c1992f8 | 339 | interrupt-parent = <&mpc5200_pic>; |
5cae84c9 | 340 | fsl5200-clocking; |
c6d4d657 GL |
341 | }; |
342 | sram@8000 { | |
343 | device_type = "sram"; | |
05cbbc69 | 344 | compatible = "mpc5200b-sram\0mpc5200-sram\0sram"; |
c6d4d657 GL |
345 | reg = <8000 4000>; |
346 | }; | |
347 | }; | |
348 | }; |