[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / powerpc / boot / dts / kilauea.dts

/*
 * Device Tree Source for AMCC Kilauea (405EX)
 *
 * Copyright 2007-2009 DENX Software Engineering, Stefan Roese <sr@denx.de>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without
 * any warranty of any kind, whether express or implied.
 */

/dts-v1/;

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	model = "amcc,kilauea";
	compatible = "amcc,kilauea";
	dcr-parent = <&{/cpus/cpu@0}>;

	aliases {
		ethernet0 = &EMAC0;
		ethernet1 = &EMAC1;
		serial0 = &UART0;
		serial1 = &UART1;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			model = "PowerPC,405EX";
			reg = <0x00000000>;
			clock-frequency = <0>; /* Filled in by U-Boot */
			timebase-frequency = <0>; /* Filled in by U-Boot */
			i-cache-line-size = <32>;
			d-cache-line-size = <32>;
			i-cache-size = <16384>; /* 16 kB */
			d-cache-size = <16384>; /* 16 kB */
			dcr-controller;
			dcr-access-method = "native";
		};
	};

	memory {
		device_type = "memory";
		reg = <0x00000000 0x00000000>; /* Filled in by U-Boot */
	};

	UIC0: interrupt-controller {
		compatible = "ibm,uic-405ex", "ibm,uic";
		interrupt-controller;
		cell-index = <0>;
		dcr-reg = <0x0c0 0x009>;
		#address-cells = <0>;
		#size-cells = <0>;
		#interrupt-cells = <2>;
	};

	UIC1: interrupt-controller1 {
		compatible = "ibm,uic-405ex","ibm,uic";
		interrupt-controller;
		cell-index = <1>;
		dcr-reg = <0x0d0 0x009>;
		#address-cells = <0>;
		#size-cells = <0>;
		#interrupt-cells = <2>;
		interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
		interrupt-parent = <&UIC0>;
	};

	UIC2: interrupt-controller2 {
		compatible = "ibm,uic-405ex","ibm,uic";
		interrupt-controller;
		cell-index = <2>;
		dcr-reg = <0x0e0 0x009>;
		#address-cells = <0>;
		#size-cells = <0>;
		#interrupt-cells = <2>;
		interrupts = <0x1c 0x4 0x1d 0x4>; /* cascade */
		interrupt-parent = <&UIC0>;
	};

	CPM0: cpm {
		compatible = "ibm,cpm";
		dcr-access-method = "native";
		dcr-reg = <0x0b0 0x003>;
		unused-units = <0x00000000>;
		idle-doze = <0x02000000>;
		standby = <0xe3e74800>;
	};

	plb {
		compatible = "ibm,plb-405ex", "ibm,plb4";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		clock-frequency = <0>; /* Filled in by U-Boot */

		SDRAM0: memory-controller {
			compatible = "ibm,sdram-405ex", "ibm,sdram-4xx-ddr2";
			dcr-reg = <0x010 0x002>;
			interrupt-parent = <&UIC2>;
			interrupts = <0x5 0x4	/* ECC DED Error */ 
				      0x6 0x4>;	/* ECC SEC Error */ 
		};

		CRYPTO: crypto@ef700000 {
			compatible = "amcc,ppc405ex-crypto", "amcc,ppc4xx-crypto";
			reg = <0xef700000 0x80400>;
			interrupt-parent = <&UIC0>;
			interrupts = <0x17 0x2>;
		};

		MAL0: mcmal {
			compatible = "ibm,mcmal-405ex", "ibm,mcmal2";
			dcr-reg = <0x180 0x062>;
			num-tx-chans = <2>;
			num-rx-chans = <2>;
			interrupt-parent = <&MAL0>;
			interrupts = <0x0 0x1 0x2 0x3 0x4>;
			#interrupt-cells = <1>;
			#address-cells = <0>;
			#size-cells = <0>;
			interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4
					/*RXEOB*/ 0x1 &UIC0 0xb 0x4
					/*SERR*/  0x2 &UIC1 0x0 0x4
					/*TXDE*/  0x3 &UIC1 0x1 0x4
					/*RXDE*/  0x4 &UIC1 0x2 0x4>;
			interrupt-map-mask = <0xffffffff>;
		};

		POB0: opb {
			compatible = "ibm,opb-405ex", "ibm,opb";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x80000000 0x80000000 0x10000000
				  0xef600000 0xef600000 0x00a00000
				  0xf0000000 0xf0000000 0x10000000>;
			dcr-reg = <0x0a0 0x005>;
			clock-frequency = <0>; /* Filled in by U-Boot */

			EBC0: ebc {
				compatible = "ibm,ebc-405ex", "ibm,ebc";
				dcr-reg = <0x012 0x002>;
				#address-cells = <2>;
				#size-cells = <1>;
				clock-frequency = <0>; /* Filled in by U-Boot */
				/* ranges property is supplied by U-Boot */
				interrupts = <0x5 0x1>;
				interrupt-parent = <&UIC1>;

				nor_flash@0,0 {
					compatible = "amd,s29gl512n", "cfi-flash";
					bank-width = <2>;
					reg = <0x00000000 0x00000000 0x04000000>;
					#address-cells = <1>;
					#size-cells = <1>;
					partition@0 {
						label = "kernel";
						reg = <0x00000000 0x001e0000>;
					};
					partition@1e0000 {
						label = "dtb";
						reg = <0x001e0000 0x00020000>;
					};
					partition@200000 {
						label = "root";
						reg = <0x00200000 0x00200000>;
					};
					partition@400000 {
						label = "user";
						reg = <0x00400000 0x03b60000>;
					};
					partition@3f60000 {
						label = "env";
						reg = <0x03f60000 0x00040000>;
					};
					partition@3fa0000 {
						label = "u-boot";
						reg = <0x03fa0000 0x00060000>;
					};
				};

				ndfc@1,0 {
					compatible = "ibm,ndfc";
					reg = <0x00000001 0x00000000 0x00002000>;
					ccr = <0x00001000>;
					bank-settings = <0x80002222>;
					#address-cells = <1>;
					#size-cells = <1>;

					nand {
						#address-cells = <1>;
						#size-cells = <1>;

						partition@0 {
							label = "u-boot";
							reg = <0x00000000 0x00100000>;
						};
						partition@100000 {
							label = "user";
							reg = <0x00000000 0x03f00000>;
						};
					};
				};
			};

			UART0: serial@ef600200 {
				device_type = "serial";
				compatible = "ns16550";
				reg = <0xef600200 0x00000008>;
				virtual-reg = <0xef600200>;
				clock-frequency = <0>; /* Filled in by U-Boot */
				current-speed = <0>;
				interrupt-parent = <&UIC0>;
				interrupts = <0x1a 0x4>;
			};

			UART1: serial@ef600300 {
				device_type = "serial";
				compatible = "ns16550";
				reg = <0xef600300 0x00000008>;
				virtual-reg = <0xef600300>;
				clock-frequency = <0>; /* Filled in by U-Boot */
				current-speed = <0>;
				interrupt-parent = <&UIC0>;
				interrupts = <0x1 0x4>;
			};

			IIC0: i2c@ef600400 {
				compatible = "ibm,iic-405ex", "ibm,iic";
				reg = <0xef600400 0x00000014>;
				interrupt-parent = <&UIC0>;
				interrupts = <0x2 0x4>;
				#address-cells = <1>;
				#size-cells = <0>;

				rtc@68 {
					compatible = "dallas,ds1338";
					reg = <0x68>;
				};

				dtt@48 {
					compatible = "dallas,ds1775";
					reg = <0x48>;
				};
			};

			IIC1: i2c@ef600500 {
				compatible = "ibm,iic-405ex", "ibm,iic";
				reg = <0xef600500 0x00000014>;
				interrupt-parent = <&UIC0>;
				interrupts = <0x7 0x4>;
			};

			RGMII0: emac-rgmii@ef600b00 {
				compatible = "ibm,rgmii-405ex", "ibm,rgmii";
				reg = <0xef600b00 0x00000104>;
				has-mdio;
			};

			EMAC0: ethernet@ef600900 {
				linux,network-index = <0x0>;
				device_type = "network";
				compatible = "ibm,emac-405ex", "ibm,emac4sync";
				interrupt-parent = <&EMAC0>;
				interrupts = <0x0 0x1>;
				#interrupt-cells = <1>;
				#address-cells = <0>;
				#size-cells = <0>;
				interrupt-map = </*Status*/ 0x0 &UIC0 0x18 0x4
						/*Wake*/  0x1 &UIC1 0x1d 0x4>;
				reg = <0xef600900 0x000000c4>;
				local-mac-address = [000000000000]; /* Filled in by U-Boot */
				mal-device = <&MAL0>;
				mal-tx-channel = <0>;
				mal-rx-channel = <0>;
				cell-index = <0>;
				max-frame-size = <9000>;
				rx-fifo-size = <4096>;
				tx-fifo-size = <2048>;
				rx-fifo-size-gige = <16384>;
				tx-fifo-size-gige = <16384>;
				phy-mode = "rgmii";
				phy-map = <0x00000000>;
				rgmii-device = <&RGMII0>;
				rgmii-channel = <0>;
				has-inverted-stacr-oc;
				has-new-stacr-staopc;
			};

			EMAC1: ethernet@ef600a00 {
				linux,network-index = <0x1>;
				device_type = "network";
				compatible = "ibm,emac-405ex", "ibm,emac4sync";
				interrupt-parent = <&EMAC1>;
				interrupts = <0x0 0x1>;
				#interrupt-cells = <1>;
				#address-cells = <0>;
				#size-cells = <0>;
				interrupt-map = </*Status*/ 0x0 &UIC0 0x19 0x4
						/*Wake*/  0x1 &UIC1 0x1f 0x4>;
				reg = <0xef600a00 0x000000c4>;
				local-mac-address = [000000000000]; /* Filled in by U-Boot */
				mal-device = <&MAL0>;
				mal-tx-channel = <1>;
				mal-rx-channel = <1>;
				cell-index = <1>;
				max-frame-size = <9000>;
				rx-fifo-size = <4096>;
				tx-fifo-size = <2048>;
				rx-fifo-size-gige = <16384>;
				tx-fifo-size-gige = <16384>;
				phy-mode = "rgmii";
				phy-map = <0x00000000>;
				rgmii-device = <&RGMII0>;
				rgmii-channel = <1>;
				has-inverted-stacr-oc;
				has-new-stacr-staopc;
			};
		};

		PCIE0: pciex@0a0000000 {
			device_type = "pci";
			#interrupt-cells = <1>;
			#size-cells = <2>;
			#address-cells = <3>;
			compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex";
			primary;
			port = <0x0>; /* port number */
			reg = <0xa0000000 0x20000000	/* Config space access */
			       0xef000000 0x00001000>;	/* Registers */
			dcr-reg = <0x040 0x020>;
			sdr-base = <0x400>;

			/* Outbound ranges, one memory and one IO,
			 * later cannot be changed
			 */
			ranges = <0x02000000 0x00000000 0x80000000 0x90000000 0x00000000 0x08000000
				  0x01000000 0x00000000 0x00000000 0xe0000000 0x00000000 0x00010000>;

			/* Inbound 2GB range starting at 0 */
			dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>;

			/* This drives busses 0x00 to 0x3f */
			bus-range = <0x0 0x3f>;

			/* Legacy interrupts (note the weird polarity, the bridge seems
			 * to invert PCIe legacy interrupts).
			 * We are de-swizzling here because the numbers are actually for
			 * port of the root complex virtual P2P bridge. But I want
			 * to avoid putting a node for it in the tree, so the numbers
			 * below are basically de-swizzled numbers.
			 * The real slot is on idsel 0, so the swizzling is 1:1
			 */
			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
			interrupt-map = <
				0x0 0x0 0x0 0x1 &UIC2 0x0 0x4 /* swizzled int A */
				0x0 0x0 0x0 0x2 &UIC2 0x1 0x4 /* swizzled int B */
				0x0 0x0 0x0 0x3 &UIC2 0x2 0x4 /* swizzled int C */
				0x0 0x0 0x0 0x4 &UIC2 0x3 0x4 /* swizzled int D */>;
		};

		PCIE1: pciex@0c0000000 {
			device_type = "pci";
			#interrupt-cells = <1>;
			#size-cells = <2>;
			#address-cells = <3>;
			compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex";
			primary;
			port = <0x1>; /* port number */
			reg = <0xc0000000 0x20000000	/* Config space access */
			       0xef001000 0x00001000>;	/* Registers */
			dcr-reg = <0x060 0x020>;
			sdr-base = <0x440>;

			/* Outbound ranges, one memory and one IO,
			 * later cannot be changed
			 */
			ranges = <0x02000000 0x00000000 0x80000000 0x98000000 0x00000000 0x08000000
				  0x01000000 0x00000000 0x00000000 0xe0010000 0x00000000 0x00010000>;

			/* Inbound 2GB range starting at 0 */
			dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>;

			/* This drives busses 0x40 to 0x7f */
			bus-range = <0x40 0x7f>;

			/* Legacy interrupts (note the weird polarity, the bridge seems
			 * to invert PCIe legacy interrupts).
			 * We are de-swizzling here because the numbers are actually for
			 * port of the root complex virtual P2P bridge. But I want
			 * to avoid putting a node for it in the tree, so the numbers
			 * below are basically de-swizzled numbers.
			 * The real slot is on idsel 0, so the swizzling is 1:1
			 */
			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
			interrupt-map = <
				0x0 0x0 0x0 0x1 &UIC2 0xb 0x4 /* swizzled int A */
				0x0 0x0 0x0 0x2 &UIC2 0xc 0x4 /* swizzled int B */
				0x0 0x0 0x0 0x3 &UIC2 0xd 0x4 /* swizzled int C */
				0x0 0x0 0x0 0x4 &UIC2 0xe 0x4 /* swizzled int D */>;
		};

		MSI: ppc4xx-msi@C10000000 {
			compatible = "amcc,ppc4xx-msi", "ppc4xx-msi";
			reg = < 0x0 0xEF620000 0x100>;
			sdr-base = <0x4B0>;
			msi-data = <0x00000000>;
			msi-mask = <0x44440000>;
			interrupt-count = <12>;
			interrupts = <0 1 2 3 4 5 6 7 8 9 0xA 0xB 0xC 0xD>;
			interrupt-parent = <&UIC2>;
			#interrupt-cells = <1>;
			#address-cells = <0>;
			#size-cells = <0>;
			interrupt-map = <0 &UIC2 0x10 1
					1 &UIC2 0x11 1
					2 &UIC2 0x12 1
					2 &UIC2 0x13 1
					2 &UIC2 0x14 1
					2 &UIC2 0x15 1
					2 &UIC2 0x16 1
					2 &UIC2 0x17 1
					2 &UIC2 0x18 1
					2 &UIC2 0x19 1
					2 &UIC2 0x1A 1
					2 &UIC2 0x1B 1
					2 &UIC2 0x1C 1
					3 &UIC2 0x1D 1>;
		};
	};
};
Commit	Line	Data
a62f48de SR	1	/*
	2	* Device Tree Source for AMCC Kilauea (405EX)
	3	*
13ae564f	4	* Copyright 2007-2009 DENX Software Engineering, Stefan Roese <sr@denx.de>
a62f48de SR	5	*
	6	* This file is licensed under the terms of the GNU General Public
	7	* License version 2. This program is licensed "as is" without
	8	* any warranty of any kind, whether express or implied.
	9	*/
	10
71f34979 DG	11	/dts-v1/;
71f34979 DG	12
a62f48de SR	13	/ {
	14	#address-cells = <1>;
	15	#size-cells = <1>;
	16	model = "amcc,kilauea";
	17	compatible = "amcc,kilauea";
71f34979	18	dcr-parent = <&{/cpus/cpu@0}>;
a62f48de	19
8aaed98c SR	20	aliases {
	21	ethernet0 = &EMAC0;
	22	ethernet1 = &EMAC1;
	23	serial0 = &UART0;
	24	serial1 = &UART1;
	25	};
	26
a62f48de SR	27	cpus {
	28	#address-cells = <1>;
	29	#size-cells = <0>;
	30
72fda114	31	cpu@0 {
a62f48de	32	device_type = "cpu";
72fda114	33	model = "PowerPC,405EX";
71f34979	34	reg = <0x00000000>;
a62f48de SR	35	clock-frequency = <0>; /* Filled in by U-Boot */
a62f48de SR	36	timebase-frequency = <0>; /* Filled in by U-Boot */
71f34979 DG	37	i-cache-line-size = <32>;
	38	d-cache-line-size = <32>;
	39	i-cache-size = <16384>; /* 16 kB */
	40	d-cache-size = <16384>; /* 16 kB */
a62f48de SR	41	dcr-controller;
	42	dcr-access-method = "native";
	43	};
	44	};
	45
	46	memory {
	47	device_type = "memory";
71f34979	48	reg = <0x00000000 0x00000000>; /* Filled in by U-Boot */
a62f48de SR	49	};
	50
	51	UIC0: interrupt-controller {
	52	compatible = "ibm,uic-405ex", "ibm,uic";
	53	interrupt-controller;
	54	cell-index = <0>;
71f34979	55	dcr-reg = <0x0c0 0x009>;
a62f48de SR	56	#address-cells = <0>;
	57	#size-cells = <0>;
	58	#interrupt-cells = <2>;
	59	};
	60
	61	UIC1: interrupt-controller1 {
	62	compatible = "ibm,uic-405ex","ibm,uic";
	63	interrupt-controller;
	64	cell-index = <1>;
71f34979	65	dcr-reg = <0x0d0 0x009>;
a62f48de SR	66	#address-cells = <0>;
	67	#size-cells = <0>;
	68	#interrupt-cells = <2>;
71f34979	69	interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
a62f48de SR	70	interrupt-parent = <&UIC0>;
	71	};
	72
	73	UIC2: interrupt-controller2 {
	74	compatible = "ibm,uic-405ex","ibm,uic";
	75	interrupt-controller;
	76	cell-index = <2>;
71f34979	77	dcr-reg = <0x0e0 0x009>;
a62f48de SR	78	#address-cells = <0>;
	79	#size-cells = <0>;
	80	#interrupt-cells = <2>;
71f34979	81	interrupts = <0x1c 0x4 0x1d 0x4>; /* cascade */
a62f48de SR	82	interrupt-parent = <&UIC0>;
	83	};
	84
05ed6087 VG	85	CPM0: cpm {
	86	compatible = "ibm,cpm";
	87	dcr-access-method = "native";
	88	dcr-reg = <0x0b0 0x003>;
	89	unused-units = <0x00000000>;
	90	idle-doze = <0x02000000>;
	91	standby = <0xe3e74800>;
	92	};
	93
a62f48de SR	94	plb {
	95	compatible = "ibm,plb-405ex", "ibm,plb4";
	96	#address-cells = <1>;
	97	#size-cells = <1>;
	98	ranges;
	99	clock-frequency = <0>; /* Filled in by U-Boot */
	100
	101	SDRAM0: memory-controller {
94ce1c58	102	compatible = "ibm,sdram-405ex", "ibm,sdram-4xx-ddr2";
71f34979	103	dcr-reg = <0x010 0x002>;
94ce1c58 GE	104	interrupt-parent = <&UIC2>;
	105	interrupts = <0x5 0x4 /* ECC DED Error */
	106	0x6 0x4>; /* ECC SEC Error */
a62f48de SR	107	};
a62f48de SR	108
049359d6 JH	109	CRYPTO: crypto@ef700000 {
	110	compatible = "amcc,ppc405ex-crypto", "amcc,ppc4xx-crypto";
	111	reg = <0xef700000 0x80400>;
	112	interrupt-parent = <&UIC0>;
	113	interrupts = <0x17 0x2>;
	114	};
	115
a62f48de SR	116	MAL0: mcmal {
a62f48de SR	117	compatible = "ibm,mcmal-405ex", "ibm,mcmal2";
71f34979	118	dcr-reg = <0x180 0x062>;
a62f48de SR	119	num-tx-chans = <2>;
	120	num-rx-chans = <2>;
	121	interrupt-parent = <&MAL0>;
71f34979	122	interrupts = <0x0 0x1 0x2 0x3 0x4>;
a62f48de SR	123	#interrupt-cells = <1>;
	124	#address-cells = <0>;
	125	#size-cells = <0>;
71f34979 DG	126	interrupt-map = </TXEOB/ 0x0 &UIC0 0xa 0x4
	127	/RXEOB/ 0x1 &UIC0 0xb 0x4
	128	/SERR/ 0x2 &UIC1 0x0 0x4
	129	/TXDE/ 0x3 &UIC1 0x1 0x4
	130	/RXDE/ 0x4 &UIC1 0x2 0x4>;
	131	interrupt-map-mask = <0xffffffff>;
a62f48de SR	132	};
	133
	134	POB0: opb {
	135	compatible = "ibm,opb-405ex", "ibm,opb";
	136	#address-cells = <1>;
	137	#size-cells = <1>;
71f34979 DG	138	ranges = <0x80000000 0x80000000 0x10000000
	139	0xef600000 0xef600000 0x00a00000
	140	0xf0000000 0xf0000000 0x10000000>;
	141	dcr-reg = <0x0a0 0x005>;
a62f48de SR	142	clock-frequency = <0>; /* Filled in by U-Boot */
	143
	144	EBC0: ebc {
	145	compatible = "ibm,ebc-405ex", "ibm,ebc";
71f34979	146	dcr-reg = <0x012 0x002>;
a62f48de SR	147	#address-cells = <2>;
	148	#size-cells = <1>;
	149	clock-frequency = <0>; /* Filled in by U-Boot */
	150	/* ranges property is supplied by U-Boot */
71f34979	151	interrupts = <0x5 0x1>;
a62f48de SR	152	interrupt-parent = <&UIC1>;
	153
	154	nor_flash@0,0 {
	155	compatible = "amd,s29gl512n", "cfi-flash";
	156	bank-width = <2>;
71f34979	157	reg = <0x00000000 0x00000000 0x04000000>;
a62f48de SR	158	#address-cells = <1>;
	159	#size-cells = <1>;
	160	partition@0 {
	161	label = "kernel";
13ae564f SR	162	reg = <0x00000000 0x001e0000>;
	163	};
	164	partition@1e0000 {
	165	label = "dtb";
	166	reg = <0x001e0000 0x00020000>;
a62f48de SR	167	};
	168	partition@200000 {
	169	label = "root";
71f34979	170	reg = <0x00200000 0x00200000>;
a62f48de SR	171	};
	172	partition@400000 {
	173	label = "user";
71f34979	174	reg = <0x00400000 0x03b60000>;
a62f48de SR	175	};
	176	partition@3f60000 {
	177	label = "env";
71f34979	178	reg = <0x03f60000 0x00040000>;
a62f48de SR	179	};
	180	partition@3fa0000 {
	181	label = "u-boot";
71f34979	182	reg = <0x03fa0000 0x00060000>;
a62f48de SR	183	};
a62f48de SR	184	};
13ae564f SR	185
	186	ndfc@1,0 {
	187	compatible = "ibm,ndfc";
	188	reg = <0x00000001 0x00000000 0x00002000>;
	189	ccr = <0x00001000>;
	190	bank-settings = <0x80002222>;
	191	#address-cells = <1>;
	192	#size-cells = <1>;
	193
	194	nand {
	195	#address-cells = <1>;
	196	#size-cells = <1>;
	197
	198	partition@0 {
	199	label = "u-boot";
	200	reg = <0x00000000 0x00100000>;
	201	};
	202	partition@100000 {
	203	label = "user";
	204	reg = <0x00000000 0x03f00000>;
	205	};
	206	};
	207	};
a62f48de SR	208	};
	209
	210	UART0: serial@ef600200 {
	211	device_type = "serial";
	212	compatible = "ns16550";
71f34979 DG	213	reg = <0xef600200 0x00000008>;
71f34979 DG	214	virtual-reg = <0xef600200>;
a62f48de SR	215	clock-frequency = <0>; /* Filled in by U-Boot */
	216	current-speed = <0>;
	217	interrupt-parent = <&UIC0>;
71f34979	218	interrupts = <0x1a 0x4>;
a62f48de SR	219	};
	220
	221	UART1: serial@ef600300 {
	222	device_type = "serial";
	223	compatible = "ns16550";
71f34979 DG	224	reg = <0xef600300 0x00000008>;
71f34979 DG	225	virtual-reg = <0xef600300>;
a62f48de SR	226	clock-frequency = <0>; /* Filled in by U-Boot */
	227	current-speed = <0>;
	228	interrupt-parent = <&UIC0>;
71f34979	229	interrupts = <0x1 0x4>;
a62f48de SR	230	};
	231
	232	IIC0: i2c@ef600400 {
a62f48de	233	compatible = "ibm,iic-405ex", "ibm,iic";
71f34979	234	reg = <0xef600400 0x00000014>;
a62f48de	235	interrupt-parent = <&UIC0>;
71f34979	236	interrupts = <0x2 0x4>;
13ae564f SR	237	#address-cells = <1>;
	238	#size-cells = <0>;
	239
	240	rtc@68 {
	241	compatible = "dallas,ds1338";
	242	reg = <0x68>;
	243	};
	244
	245	dtt@48 {
	246	compatible = "dallas,ds1775";
	247	reg = <0x48>;
	248	};
a62f48de SR	249	};
	250
	251	IIC1: i2c@ef600500 {
a62f48de	252	compatible = "ibm,iic-405ex", "ibm,iic";
71f34979	253	reg = <0xef600500 0x00000014>;
a62f48de	254	interrupt-parent = <&UIC0>;
71f34979	255	interrupts = <0x7 0x4>;
a62f48de SR	256	};
a62f48de SR	257
a62f48de	258	RGMII0: emac-rgmii@ef600b00 {
a62f48de	259	compatible = "ibm,rgmii-405ex", "ibm,rgmii";
71f34979	260	reg = <0xef600b00 0x00000104>;
0a6ea8be	261	has-mdio;
a62f48de SR	262	};
	263
	264	EMAC0: ethernet@ef600900 {
71f34979	265	linux,network-index = <0x0>;
a62f48de	266	device_type = "network";
05781ccd	267	compatible = "ibm,emac-405ex", "ibm,emac4sync";
a62f48de	268	interrupt-parent = <&EMAC0>;
71f34979	269	interrupts = <0x0 0x1>;
a62f48de SR	270	#interrupt-cells = <1>;
	271	#address-cells = <0>;
	272	#size-cells = <0>;
71f34979 DG	273	interrupt-map = </Status/ 0x0 &UIC0 0x18 0x4
71f34979 DG	274	/Wake/ 0x1 &UIC1 0x1d 0x4>;
05781ccd	275	reg = <0xef600900 0x000000c4>;
a62f48de SR	276	local-mac-address = [000000000000]; /* Filled in by U-Boot */
	277	mal-device = <&MAL0>;
	278	mal-tx-channel = <0>;
	279	mal-rx-channel = <0>;
	280	cell-index = <0>;
71f34979 DG	281	max-frame-size = <9000>;
	282	rx-fifo-size = <4096>;
	283	tx-fifo-size = <2048>;
835ad8e7 DM	284	rx-fifo-size-gige = <16384>;
835ad8e7 DM	285	tx-fifo-size-gige = <16384>;
a62f48de	286	phy-mode = "rgmii";
71f34979	287	phy-map = <0x00000000>;
a62f48de SR	288	rgmii-device = <&RGMII0>;
a62f48de SR	289	rgmii-channel = <0>;
0a6ea8be SR	290	has-inverted-stacr-oc;
0a6ea8be SR	291	has-new-stacr-staopc;
a62f48de SR	292	};
	293
	294	EMAC1: ethernet@ef600a00 {
71f34979	295	linux,network-index = <0x1>;
a62f48de	296	device_type = "network";
05781ccd	297	compatible = "ibm,emac-405ex", "ibm,emac4sync";
a62f48de	298	interrupt-parent = <&EMAC1>;
71f34979	299	interrupts = <0x0 0x1>;
a62f48de SR	300	#interrupt-cells = <1>;
	301	#address-cells = <0>;
	302	#size-cells = <0>;
71f34979 DG	303	interrupt-map = </Status/ 0x0 &UIC0 0x19 0x4
71f34979 DG	304	/Wake/ 0x1 &UIC1 0x1f 0x4>;
05781ccd	305	reg = <0xef600a00 0x000000c4>;
a62f48de SR	306	local-mac-address = [000000000000]; /* Filled in by U-Boot */
	307	mal-device = <&MAL0>;
	308	mal-tx-channel = <1>;
	309	mal-rx-channel = <1>;
	310	cell-index = <1>;
71f34979 DG	311	max-frame-size = <9000>;
	312	rx-fifo-size = <4096>;
	313	tx-fifo-size = <2048>;
835ad8e7 DM	314	rx-fifo-size-gige = <16384>;
835ad8e7 DM	315	tx-fifo-size-gige = <16384>;
a62f48de	316	phy-mode = "rgmii";
71f34979	317	phy-map = <0x00000000>;
a62f48de SR	318	rgmii-device = <&RGMII0>;
a62f48de SR	319	rgmii-channel = <1>;
0a6ea8be SR	320	has-inverted-stacr-oc;
0a6ea8be SR	321	has-new-stacr-staopc;
a62f48de SR	322	};
a62f48de SR	323	};
151161c6 SR	324
	325	PCIE0: pciex@0a0000000 {
	326	device_type = "pci";
	327	#interrupt-cells = <1>;
	328	#size-cells = <2>;
	329	#address-cells = <3>;
	330	compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex";
	331	primary;
71f34979 DG	332	port = <0x0>; /* port number */
	333	reg = <0xa0000000 0x20000000 /* Config space access */
	334	0xef000000 0x00001000>; /* Registers */
	335	dcr-reg = <0x040 0x020>;
	336	sdr-base = <0x400>;
151161c6 SR	337
	338	/* Outbound ranges, one memory and one IO,
	339	* later cannot be changed
	340	*/
71f34979 DG	341	ranges = <0x02000000 0x00000000 0x80000000 0x90000000 0x00000000 0x08000000
71f34979 DG	342	0x01000000 0x00000000 0x00000000 0xe0000000 0x00000000 0x00010000>;
151161c6 SR	343
151161c6 SR	344	/* Inbound 2GB range starting at 0 */
71f34979	345	dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>;
151161c6	346
dc88416b	347	/* This drives busses 0x00 to 0x3f */
71f34979	348	bus-range = <0x0 0x3f>;
151161c6 SR	349
	350	/* Legacy interrupts (note the weird polarity, the bridge seems
	351	* to invert PCIe legacy interrupts).
	352	* We are de-swizzling here because the numbers are actually for
	353	* port of the root complex virtual P2P bridge. But I want
	354	* to avoid putting a node for it in the tree, so the numbers
	355	* below are basically de-swizzled numbers.
	356	* The real slot is on idsel 0, so the swizzling is 1:1
	357	*/
71f34979	358	interrupt-map-mask = <0x0 0x0 0x0 0x7>;
151161c6	359	interrupt-map = <
71f34979 DG	360	0x0 0x0 0x0 0x1 &UIC2 0x0 0x4 /* swizzled int A */
	361	0x0 0x0 0x0 0x2 &UIC2 0x1 0x4 /* swizzled int B */
	362	0x0 0x0 0x0 0x3 &UIC2 0x2 0x4 /* swizzled int C */
	363	0x0 0x0 0x0 0x4 &UIC2 0x3 0x4 /* swizzled int D */>;
151161c6 SR	364	};
	365
	366	PCIE1: pciex@0c0000000 {
	367	device_type = "pci";
	368	#interrupt-cells = <1>;
	369	#size-cells = <2>;
	370	#address-cells = <3>;
	371	compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex";
	372	primary;
71f34979 DG	373	port = <0x1>; /* port number */
	374	reg = <0xc0000000 0x20000000 /* Config space access */
	375	0xef001000 0x00001000>; /* Registers */
	376	dcr-reg = <0x060 0x020>;
	377	sdr-base = <0x440>;
151161c6 SR	378
	379	/* Outbound ranges, one memory and one IO,
	380	* later cannot be changed
	381	*/
71f34979 DG	382	ranges = <0x02000000 0x00000000 0x80000000 0x98000000 0x00000000 0x08000000
71f34979 DG	383	0x01000000 0x00000000 0x00000000 0xe0010000 0x00000000 0x00010000>;
151161c6 SR	384
151161c6 SR	385	/* Inbound 2GB range starting at 0 */
71f34979	386	dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>;
151161c6	387
dc88416b	388	/* This drives busses 0x40 to 0x7f */
71f34979	389	bus-range = <0x40 0x7f>;
151161c6 SR	390
	391	/* Legacy interrupts (note the weird polarity, the bridge seems
	392	* to invert PCIe legacy interrupts).
	393	* We are de-swizzling here because the numbers are actually for
	394	* port of the root complex virtual P2P bridge. But I want
	395	* to avoid putting a node for it in the tree, so the numbers
	396	* below are basically de-swizzled numbers.
	397	* The real slot is on idsel 0, so the swizzling is 1:1
	398	*/
71f34979	399	interrupt-map-mask = <0x0 0x0 0x0 0x7>;
151161c6	400	interrupt-map = <
71f34979 DG	401	0x0 0x0 0x0 0x1 &UIC2 0xb 0x4 /* swizzled int A */
	402	0x0 0x0 0x0 0x2 &UIC2 0xc 0x4 /* swizzled int B */
	403	0x0 0x0 0x0 0x3 &UIC2 0xd 0x4 /* swizzled int C */
	404	0x0 0x0 0x0 0x4 &UIC2 0xe 0x4 /* swizzled int D */>;
151161c6	405	};
3fb79338 RS	406
	407	MSI: ppc4xx-msi@C10000000 {
	408	compatible = "amcc,ppc4xx-msi", "ppc4xx-msi";
	409	reg = < 0x0 0xEF620000 0x100>;
	410	sdr-base = <0x4B0>;
	411	msi-data = <0x00000000>;
	412	msi-mask = <0x44440000>;
	413	interrupt-count = <12>;
	414	interrupts = <0 1 2 3 4 5 6 7 8 9 0xA 0xB 0xC 0xD>;
	415	interrupt-parent = <&UIC2>;
	416	#interrupt-cells = <1>;
	417	#address-cells = <0>;
	418	#size-cells = <0>;
	419	interrupt-map = <0 &UIC2 0x10 1
	420	1 &UIC2 0x11 1
	421	2 &UIC2 0x12 1
	422	2 &UIC2 0x13 1
	423	2 &UIC2 0x14 1
	424	2 &UIC2 0x15 1
	425	2 &UIC2 0x16 1
	426	2 &UIC2 0x17 1
	427	2 &UIC2 0x18 1
	428	2 &UIC2 0x19 1
	429	2 &UIC2 0x1A 1
	430	2 &UIC2 0x1B 1
	431	2 &UIC2 0x1C 1
	432	3 &UIC2 0x1D 1>;
	433	};
a62f48de SR	434	};
a62f48de SR	435	};