[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / powerpc / boot / dts / kilauea.dts

/*
 * Device Tree Source for AMCC Kilauea (405EX)
 *
 * Copyright 2007-2009 DENX Software Engineering, Stefan Roese <sr@denx.de>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without
 * any warranty of any kind, whether express or implied.
 */

/dts-v1/;

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	model = "amcc,kilauea";
	compatible = "amcc,kilauea";
	dcr-parent = <&{/cpus/cpu@0}>;

	aliases {
		ethernet0 = &EMAC0;
		ethernet1 = &EMAC1;
		serial0 = &UART0;
		serial1 = &UART1;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			model = "PowerPC,405EX";
			reg = <0x00000000>;
			clock-frequency = <0>; /* Filled in by U-Boot */
			timebase-frequency = <0>; /* Filled in by U-Boot */
			i-cache-line-size = <32>;
			d-cache-line-size = <32>;
			i-cache-size = <16384>; /* 16 kB */
			d-cache-size = <16384>; /* 16 kB */
			dcr-controller;
			dcr-access-method = "native";
		};
	};

	memory {
		device_type = "memory";
		reg = <0x00000000 0x00000000>; /* Filled in by U-Boot */
	};

	UIC0: interrupt-controller {
		compatible = "ibm,uic-405ex", "ibm,uic";
		interrupt-controller;
		cell-index = <0>;
		dcr-reg = <0x0c0 0x009>;
		#address-cells = <0>;
		#size-cells = <0>;
		#interrupt-cells = <2>;
	};

	UIC1: interrupt-controller1 {
		compatible = "ibm,uic-405ex","ibm,uic";
		interrupt-controller;
		cell-index = <1>;
		dcr-reg = <0x0d0 0x009>;
		#address-cells = <0>;
		#size-cells = <0>;
		#interrupt-cells = <2>;
		interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
		interrupt-parent = <&UIC0>;
	};

	UIC2: interrupt-controller2 {
		compatible = "ibm,uic-405ex","ibm,uic";
		interrupt-controller;
		cell-index = <2>;
		dcr-reg = <0x0e0 0x009>;
		#address-cells = <0>;
		#size-cells = <0>;
		#interrupt-cells = <2>;
		interrupts = <0x1c 0x4 0x1d 0x4>; /* cascade */
		interrupt-parent = <&UIC0>;
	};

	plb {
		compatible = "ibm,plb-405ex", "ibm,plb4";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		clock-frequency = <0>; /* Filled in by U-Boot */

		SDRAM0: memory-controller {
			compatible = "ibm,sdram-405ex", "ibm,sdram-4xx-ddr2";
			dcr-reg = <0x010 0x002>;
			interrupt-parent = <&UIC2>;
			interrupts = <0x5 0x4	/* ECC DED Error */ 
				      0x6 0x4>;	/* ECC SEC Error */ 
		};

		CRYPTO: crypto@ef700000 {
			compatible = "amcc,ppc405ex-crypto", "amcc,ppc4xx-crypto";
			reg = <0xef700000 0x80400>;
			interrupt-parent = <&UIC0>;
			interrupts = <0x17 0x2>;
		};

		MAL0: mcmal {
			compatible = "ibm,mcmal-405ex", "ibm,mcmal2";
			dcr-reg = <0x180 0x062>;
			num-tx-chans = <2>;
			num-rx-chans = <2>;
			interrupt-parent = <&MAL0>;
			interrupts = <0x0 0x1 0x2 0x3 0x4>;
			#interrupt-cells = <1>;
			#address-cells = <0>;
			#size-cells = <0>;
			interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4
					/*RXEOB*/ 0x1 &UIC0 0xb 0x4
					/*SERR*/  0x2 &UIC1 0x0 0x4
					/*TXDE*/  0x3 &UIC1 0x1 0x4
					/*RXDE*/  0x4 &UIC1 0x2 0x4>;
			interrupt-map-mask = <0xffffffff>;
		};

		POB0: opb {
			compatible = "ibm,opb-405ex", "ibm,opb";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x80000000 0x80000000 0x10000000
				  0xef600000 0xef600000 0x00a00000
				  0xf0000000 0xf0000000 0x10000000>;
			dcr-reg = <0x0a0 0x005>;
			clock-frequency = <0>; /* Filled in by U-Boot */

			EBC0: ebc {
				compatible = "ibm,ebc-405ex", "ibm,ebc";
				dcr-reg = <0x012 0x002>;
				#address-cells = <2>;
				#size-cells = <1>;
				clock-frequency = <0>; /* Filled in by U-Boot */
				/* ranges property is supplied by U-Boot */
				interrupts = <0x5 0x1>;
				interrupt-parent = <&UIC1>;

				nor_flash@0,0 {
					compatible = "amd,s29gl512n", "cfi-flash";
					bank-width = <2>;
					reg = <0x00000000 0x00000000 0x04000000>;
					#address-cells = <1>;
					#size-cells = <1>;
					partition@0 {
						label = "kernel";
						reg = <0x00000000 0x001e0000>;
					};
					partition@1e0000 {
						label = "dtb";
						reg = <0x001e0000 0x00020000>;
					};
					partition@200000 {
						label = "root";
						reg = <0x00200000 0x00200000>;
					};
					partition@400000 {
						label = "user";
						reg = <0x00400000 0x03b60000>;
					};
					partition@3f60000 {
						label = "env";
						reg = <0x03f60000 0x00040000>;
					};
					partition@3fa0000 {
						label = "u-boot";
						reg = <0x03fa0000 0x00060000>;
					};
				};

				ndfc@1,0 {
					compatible = "ibm,ndfc";
					reg = <0x00000001 0x00000000 0x00002000>;
					ccr = <0x00001000>;
					bank-settings = <0x80002222>;
					#address-cells = <1>;
					#size-cells = <1>;

					nand {
						#address-cells = <1>;
						#size-cells = <1>;

						partition@0 {
							label = "u-boot";
							reg = <0x00000000 0x00100000>;
						};
						partition@100000 {
							label = "user";
							reg = <0x00000000 0x03f00000>;
						};
					};
				};
			};

			UART0: serial@ef600200 {
				device_type = "serial";
				compatible = "ns16550";
				reg = <0xef600200 0x00000008>;
				virtual-reg = <0xef600200>;
				clock-frequency = <0>; /* Filled in by U-Boot */
				current-speed = <0>;
				interrupt-parent = <&UIC0>;
				interrupts = <0x1a 0x4>;
			};

			UART1: serial@ef600300 {
				device_type = "serial";
				compatible = "ns16550";
				reg = <0xef600300 0x00000008>;
				virtual-reg = <0xef600300>;
				clock-frequency = <0>; /* Filled in by U-Boot */
				current-speed = <0>;
				interrupt-parent = <&UIC0>;
				interrupts = <0x1 0x4>;
			};

			IIC0: i2c@ef600400 {
				compatible = "ibm,iic-405ex", "ibm,iic";
				reg = <0xef600400 0x00000014>;
				interrupt-parent = <&UIC0>;
				interrupts = <0x2 0x4>;
				#address-cells = <1>;
				#size-cells = <0>;

				rtc@68 {
					compatible = "dallas,ds1338";
					reg = <0x68>;
				};

				dtt@48 {
					compatible = "dallas,ds1775";
					reg = <0x48>;
				};
			};

			IIC1: i2c@ef600500 {
				compatible = "ibm,iic-405ex", "ibm,iic";
				reg = <0xef600500 0x00000014>;
				interrupt-parent = <&UIC0>;
				interrupts = <0x7 0x4>;
			};

			RGMII0: emac-rgmii@ef600b00 {
				compatible = "ibm,rgmii-405ex", "ibm,rgmii";
				reg = <0xef600b00 0x00000104>;
				has-mdio;
			};

			EMAC0: ethernet@ef600900 {
				linux,network-index = <0x0>;
				device_type = "network";
				compatible = "ibm,emac-405ex", "ibm,emac4sync";
				interrupt-parent = <&EMAC0>;
				interrupts = <0x0 0x1>;
				#interrupt-cells = <1>;
				#address-cells = <0>;
				#size-cells = <0>;
				interrupt-map = </*Status*/ 0x0 &UIC0 0x18 0x4
						/*Wake*/  0x1 &UIC1 0x1d 0x4>;
				reg = <0xef600900 0x000000c4>;
				local-mac-address = [000000000000]; /* Filled in by U-Boot */
				mal-device = <&MAL0>;
				mal-tx-channel = <0>;
				mal-rx-channel = <0>;
				cell-index = <0>;
				max-frame-size = <9000>;
				rx-fifo-size = <4096>;
				tx-fifo-size = <2048>;
				phy-mode = "rgmii";
				phy-map = <0x00000000>;
				rgmii-device = <&RGMII0>;
				rgmii-channel = <0>;
				has-inverted-stacr-oc;
				has-new-stacr-staopc;
			};

			EMAC1: ethernet@ef600a00 {
				linux,network-index = <0x1>;
				device_type = "network";
				compatible = "ibm,emac-405ex", "ibm,emac4sync";
				interrupt-parent = <&EMAC1>;
				interrupts = <0x0 0x1>;
				#interrupt-cells = <1>;
				#address-cells = <0>;
				#size-cells = <0>;
				interrupt-map = </*Status*/ 0x0 &UIC0 0x19 0x4
						/*Wake*/  0x1 &UIC1 0x1f 0x4>;
				reg = <0xef600a00 0x000000c4>;
				local-mac-address = [000000000000]; /* Filled in by U-Boot */
				mal-device = <&MAL0>;
				mal-tx-channel = <1>;
				mal-rx-channel = <1>;
				cell-index = <1>;
				max-frame-size = <9000>;
				rx-fifo-size = <4096>;
				tx-fifo-size = <2048>;
				phy-mode = "rgmii";
				phy-map = <0x00000000>;
				rgmii-device = <&RGMII0>;
				rgmii-channel = <1>;
				has-inverted-stacr-oc;
				has-new-stacr-staopc;
			};
		};

		PCIE0: pciex@0a0000000 {
			device_type = "pci";
			#interrupt-cells = <1>;
			#size-cells = <2>;
			#address-cells = <3>;
			compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex";
			primary;
			port = <0x0>; /* port number */
			reg = <0xa0000000 0x20000000	/* Config space access */
			       0xef000000 0x00001000>;	/* Registers */
			dcr-reg = <0x040 0x020>;
			sdr-base = <0x400>;

			/* Outbound ranges, one memory and one IO,
			 * later cannot be changed
			 */
			ranges = <0x02000000 0x00000000 0x80000000 0x90000000 0x00000000 0x08000000
				  0x01000000 0x00000000 0x00000000 0xe0000000 0x00000000 0x00010000>;

			/* Inbound 2GB range starting at 0 */
			dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>;

			/* This drives busses 0x00 to 0x3f */
			bus-range = <0x0 0x3f>;

			/* Legacy interrupts (note the weird polarity, the bridge seems
			 * to invert PCIe legacy interrupts).
			 * We are de-swizzling here because the numbers are actually for
			 * port of the root complex virtual P2P bridge. But I want
			 * to avoid putting a node for it in the tree, so the numbers
			 * below are basically de-swizzled numbers.
			 * The real slot is on idsel 0, so the swizzling is 1:1
			 */
			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
			interrupt-map = <
				0x0 0x0 0x0 0x1 &UIC2 0x0 0x4 /* swizzled int A */
				0x0 0x0 0x0 0x2 &UIC2 0x1 0x4 /* swizzled int B */
				0x0 0x0 0x0 0x3 &UIC2 0x2 0x4 /* swizzled int C */
				0x0 0x0 0x0 0x4 &UIC2 0x3 0x4 /* swizzled int D */>;
		};

		PCIE1: pciex@0c0000000 {
			device_type = "pci";
			#interrupt-cells = <1>;
			#size-cells = <2>;
			#address-cells = <3>;
			compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex";
			primary;
			port = <0x1>; /* port number */
			reg = <0xc0000000 0x20000000	/* Config space access */
			       0xef001000 0x00001000>;	/* Registers */
			dcr-reg = <0x060 0x020>;
			sdr-base = <0x440>;

			/* Outbound ranges, one memory and one IO,
			 * later cannot be changed
			 */
			ranges = <0x02000000 0x00000000 0x80000000 0x98000000 0x00000000 0x08000000
				  0x01000000 0x00000000 0x00000000 0xe0010000 0x00000000 0x00010000>;

			/* Inbound 2GB range starting at 0 */
			dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>;

			/* This drives busses 0x40 to 0x7f */
			bus-range = <0x40 0x7f>;

			/* Legacy interrupts (note the weird polarity, the bridge seems
			 * to invert PCIe legacy interrupts).
			 * We are de-swizzling here because the numbers are actually for
			 * port of the root complex virtual P2P bridge. But I want
			 * to avoid putting a node for it in the tree, so the numbers
			 * below are basically de-swizzled numbers.
			 * The real slot is on idsel 0, so the swizzling is 1:1
			 */
			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
			interrupt-map = <
				0x0 0x0 0x0 0x1 &UIC2 0xb 0x4 /* swizzled int A */
				0x0 0x0 0x0 0x2 &UIC2 0xc 0x4 /* swizzled int B */
				0x0 0x0 0x0 0x3 &UIC2 0xd 0x4 /* swizzled int C */
				0x0 0x0 0x0 0x4 &UIC2 0xe 0x4 /* swizzled int D */>;
		};
	};
};
Commit	Line	Data
a62f48de SR	1	/*
	2	* Device Tree Source for AMCC Kilauea (405EX)
	3	*
13ae564f	4	* Copyright 2007-2009 DENX Software Engineering, Stefan Roese <sr@denx.de>
a62f48de SR	5	*
	6	* This file is licensed under the terms of the GNU General Public
	7	* License version 2. This program is licensed "as is" without
	8	* any warranty of any kind, whether express or implied.
	9	*/
	10
71f34979 DG	11	/dts-v1/;
71f34979 DG	12
a62f48de SR	13	/ {
	14	#address-cells = <1>;
	15	#size-cells = <1>;
	16	model = "amcc,kilauea";
	17	compatible = "amcc,kilauea";
71f34979	18	dcr-parent = <&{/cpus/cpu@0}>;
a62f48de	19
8aaed98c SR	20	aliases {
	21	ethernet0 = &EMAC0;
	22	ethernet1 = &EMAC1;
	23	serial0 = &UART0;
	24	serial1 = &UART1;
	25	};
	26
a62f48de SR	27	cpus {
	28	#address-cells = <1>;
	29	#size-cells = <0>;
	30
72fda114	31	cpu@0 {
a62f48de	32	device_type = "cpu";
72fda114	33	model = "PowerPC,405EX";
71f34979	34	reg = <0x00000000>;
a62f48de SR	35	clock-frequency = <0>; /* Filled in by U-Boot */
a62f48de SR	36	timebase-frequency = <0>; /* Filled in by U-Boot */
71f34979 DG	37	i-cache-line-size = <32>;
	38	d-cache-line-size = <32>;
	39	i-cache-size = <16384>; /* 16 kB */
	40	d-cache-size = <16384>; /* 16 kB */
a62f48de SR	41	dcr-controller;
	42	dcr-access-method = "native";
	43	};
	44	};
	45
	46	memory {
	47	device_type = "memory";
71f34979	48	reg = <0x00000000 0x00000000>; /* Filled in by U-Boot */
a62f48de SR	49	};
	50
	51	UIC0: interrupt-controller {
	52	compatible = "ibm,uic-405ex", "ibm,uic";
	53	interrupt-controller;
	54	cell-index = <0>;
71f34979	55	dcr-reg = <0x0c0 0x009>;
a62f48de SR	56	#address-cells = <0>;
	57	#size-cells = <0>;
	58	#interrupt-cells = <2>;
	59	};
	60
	61	UIC1: interrupt-controller1 {
	62	compatible = "ibm,uic-405ex","ibm,uic";
	63	interrupt-controller;
	64	cell-index = <1>;
71f34979	65	dcr-reg = <0x0d0 0x009>;
a62f48de SR	66	#address-cells = <0>;
	67	#size-cells = <0>;
	68	#interrupt-cells = <2>;
71f34979	69	interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
a62f48de SR	70	interrupt-parent = <&UIC0>;
	71	};
	72
	73	UIC2: interrupt-controller2 {
	74	compatible = "ibm,uic-405ex","ibm,uic";
	75	interrupt-controller;
	76	cell-index = <2>;
71f34979	77	dcr-reg = <0x0e0 0x009>;
a62f48de SR	78	#address-cells = <0>;
	79	#size-cells = <0>;
	80	#interrupt-cells = <2>;
71f34979	81	interrupts = <0x1c 0x4 0x1d 0x4>; /* cascade */
a62f48de SR	82	interrupt-parent = <&UIC0>;
	83	};
	84
	85	plb {
	86	compatible = "ibm,plb-405ex", "ibm,plb4";
	87	#address-cells = <1>;
	88	#size-cells = <1>;
	89	ranges;
	90	clock-frequency = <0>; /* Filled in by U-Boot */
	91
	92	SDRAM0: memory-controller {
94ce1c58	93	compatible = "ibm,sdram-405ex", "ibm,sdram-4xx-ddr2";
71f34979	94	dcr-reg = <0x010 0x002>;
94ce1c58 GE	95	interrupt-parent = <&UIC2>;
	96	interrupts = <0x5 0x4 /* ECC DED Error */
	97	0x6 0x4>; /* ECC SEC Error */
a62f48de SR	98	};
a62f48de SR	99
049359d6 JH	100	CRYPTO: crypto@ef700000 {
	101	compatible = "amcc,ppc405ex-crypto", "amcc,ppc4xx-crypto";
	102	reg = <0xef700000 0x80400>;
	103	interrupt-parent = <&UIC0>;
	104	interrupts = <0x17 0x2>;
	105	};
	106
a62f48de SR	107	MAL0: mcmal {
a62f48de SR	108	compatible = "ibm,mcmal-405ex", "ibm,mcmal2";
71f34979	109	dcr-reg = <0x180 0x062>;
a62f48de SR	110	num-tx-chans = <2>;
	111	num-rx-chans = <2>;
	112	interrupt-parent = <&MAL0>;
71f34979	113	interrupts = <0x0 0x1 0x2 0x3 0x4>;
a62f48de SR	114	#interrupt-cells = <1>;
	115	#address-cells = <0>;
	116	#size-cells = <0>;
71f34979 DG	117	interrupt-map = </TXEOB/ 0x0 &UIC0 0xa 0x4
	118	/RXEOB/ 0x1 &UIC0 0xb 0x4
	119	/SERR/ 0x2 &UIC1 0x0 0x4
	120	/TXDE/ 0x3 &UIC1 0x1 0x4
	121	/RXDE/ 0x4 &UIC1 0x2 0x4>;
	122	interrupt-map-mask = <0xffffffff>;
a62f48de SR	123	};
	124
	125	POB0: opb {
	126	compatible = "ibm,opb-405ex", "ibm,opb";
	127	#address-cells = <1>;
	128	#size-cells = <1>;
71f34979 DG	129	ranges = <0x80000000 0x80000000 0x10000000
	130	0xef600000 0xef600000 0x00a00000
	131	0xf0000000 0xf0000000 0x10000000>;
	132	dcr-reg = <0x0a0 0x005>;
a62f48de SR	133	clock-frequency = <0>; /* Filled in by U-Boot */
	134
	135	EBC0: ebc {
	136	compatible = "ibm,ebc-405ex", "ibm,ebc";
71f34979	137	dcr-reg = <0x012 0x002>;
a62f48de SR	138	#address-cells = <2>;
	139	#size-cells = <1>;
	140	clock-frequency = <0>; /* Filled in by U-Boot */
	141	/* ranges property is supplied by U-Boot */
71f34979	142	interrupts = <0x5 0x1>;
a62f48de SR	143	interrupt-parent = <&UIC1>;
	144
	145	nor_flash@0,0 {
	146	compatible = "amd,s29gl512n", "cfi-flash";
	147	bank-width = <2>;
71f34979	148	reg = <0x00000000 0x00000000 0x04000000>;
a62f48de SR	149	#address-cells = <1>;
	150	#size-cells = <1>;
	151	partition@0 {
	152	label = "kernel";
13ae564f SR	153	reg = <0x00000000 0x001e0000>;
	154	};
	155	partition@1e0000 {
	156	label = "dtb";
	157	reg = <0x001e0000 0x00020000>;
a62f48de SR	158	};
	159	partition@200000 {
	160	label = "root";
71f34979	161	reg = <0x00200000 0x00200000>;
a62f48de SR	162	};
	163	partition@400000 {
	164	label = "user";
71f34979	165	reg = <0x00400000 0x03b60000>;
a62f48de SR	166	};
	167	partition@3f60000 {
	168	label = "env";
71f34979	169	reg = <0x03f60000 0x00040000>;
a62f48de SR	170	};
	171	partition@3fa0000 {
	172	label = "u-boot";
71f34979	173	reg = <0x03fa0000 0x00060000>;
a62f48de SR	174	};
a62f48de SR	175	};
13ae564f SR	176
	177	ndfc@1,0 {
	178	compatible = "ibm,ndfc";
	179	reg = <0x00000001 0x00000000 0x00002000>;
	180	ccr = <0x00001000>;
	181	bank-settings = <0x80002222>;
	182	#address-cells = <1>;
	183	#size-cells = <1>;
	184
	185	nand {
	186	#address-cells = <1>;
	187	#size-cells = <1>;
	188
	189	partition@0 {
	190	label = "u-boot";
	191	reg = <0x00000000 0x00100000>;
	192	};
	193	partition@100000 {
	194	label = "user";
	195	reg = <0x00000000 0x03f00000>;
	196	};
	197	};
	198	};
a62f48de SR	199	};
	200
	201	UART0: serial@ef600200 {
	202	device_type = "serial";
	203	compatible = "ns16550";
71f34979 DG	204	reg = <0xef600200 0x00000008>;
71f34979 DG	205	virtual-reg = <0xef600200>;
a62f48de SR	206	clock-frequency = <0>; /* Filled in by U-Boot */
	207	current-speed = <0>;
	208	interrupt-parent = <&UIC0>;
71f34979	209	interrupts = <0x1a 0x4>;
a62f48de SR	210	};
	211
	212	UART1: serial@ef600300 {
	213	device_type = "serial";
	214	compatible = "ns16550";
71f34979 DG	215	reg = <0xef600300 0x00000008>;
71f34979 DG	216	virtual-reg = <0xef600300>;
a62f48de SR	217	clock-frequency = <0>; /* Filled in by U-Boot */
	218	current-speed = <0>;
	219	interrupt-parent = <&UIC0>;
71f34979	220	interrupts = <0x1 0x4>;
a62f48de SR	221	};
	222
	223	IIC0: i2c@ef600400 {
a62f48de	224	compatible = "ibm,iic-405ex", "ibm,iic";
71f34979	225	reg = <0xef600400 0x00000014>;
a62f48de	226	interrupt-parent = <&UIC0>;
71f34979	227	interrupts = <0x2 0x4>;
13ae564f SR	228	#address-cells = <1>;
	229	#size-cells = <0>;
	230
	231	rtc@68 {
	232	compatible = "dallas,ds1338";
	233	reg = <0x68>;
	234	};
	235
	236	dtt@48 {
	237	compatible = "dallas,ds1775";
	238	reg = <0x48>;
	239	};
a62f48de SR	240	};
	241
	242	IIC1: i2c@ef600500 {
a62f48de	243	compatible = "ibm,iic-405ex", "ibm,iic";
71f34979	244	reg = <0xef600500 0x00000014>;
a62f48de	245	interrupt-parent = <&UIC0>;
71f34979	246	interrupts = <0x7 0x4>;
a62f48de SR	247	};
a62f48de SR	248
a62f48de	249	RGMII0: emac-rgmii@ef600b00 {
a62f48de	250	compatible = "ibm,rgmii-405ex", "ibm,rgmii";
71f34979	251	reg = <0xef600b00 0x00000104>;
0a6ea8be	252	has-mdio;
a62f48de SR	253	};
	254
	255	EMAC0: ethernet@ef600900 {
71f34979	256	linux,network-index = <0x0>;
a62f48de	257	device_type = "network";
05781ccd	258	compatible = "ibm,emac-405ex", "ibm,emac4sync";
a62f48de	259	interrupt-parent = <&EMAC0>;
71f34979	260	interrupts = <0x0 0x1>;
a62f48de SR	261	#interrupt-cells = <1>;
	262	#address-cells = <0>;
	263	#size-cells = <0>;
71f34979 DG	264	interrupt-map = </Status/ 0x0 &UIC0 0x18 0x4
71f34979 DG	265	/Wake/ 0x1 &UIC1 0x1d 0x4>;
05781ccd	266	reg = <0xef600900 0x000000c4>;
a62f48de SR	267	local-mac-address = [000000000000]; /* Filled in by U-Boot */
	268	mal-device = <&MAL0>;
	269	mal-tx-channel = <0>;
	270	mal-rx-channel = <0>;
	271	cell-index = <0>;
71f34979 DG	272	max-frame-size = <9000>;
	273	rx-fifo-size = <4096>;
	274	tx-fifo-size = <2048>;
a62f48de	275	phy-mode = "rgmii";
71f34979	276	phy-map = <0x00000000>;
a62f48de SR	277	rgmii-device = <&RGMII0>;
a62f48de SR	278	rgmii-channel = <0>;
0a6ea8be SR	279	has-inverted-stacr-oc;
0a6ea8be SR	280	has-new-stacr-staopc;
a62f48de SR	281	};
	282
	283	EMAC1: ethernet@ef600a00 {
71f34979	284	linux,network-index = <0x1>;
a62f48de	285	device_type = "network";
05781ccd	286	compatible = "ibm,emac-405ex", "ibm,emac4sync";
a62f48de	287	interrupt-parent = <&EMAC1>;
71f34979	288	interrupts = <0x0 0x1>;
a62f48de SR	289	#interrupt-cells = <1>;
	290	#address-cells = <0>;
	291	#size-cells = <0>;
71f34979 DG	292	interrupt-map = </Status/ 0x0 &UIC0 0x19 0x4
71f34979 DG	293	/Wake/ 0x1 &UIC1 0x1f 0x4>;
05781ccd	294	reg = <0xef600a00 0x000000c4>;
a62f48de SR	295	local-mac-address = [000000000000]; /* Filled in by U-Boot */
	296	mal-device = <&MAL0>;
	297	mal-tx-channel = <1>;
	298	mal-rx-channel = <1>;
	299	cell-index = <1>;
71f34979 DG	300	max-frame-size = <9000>;
	301	rx-fifo-size = <4096>;
	302	tx-fifo-size = <2048>;
a62f48de	303	phy-mode = "rgmii";
71f34979	304	phy-map = <0x00000000>;
a62f48de SR	305	rgmii-device = <&RGMII0>;
a62f48de SR	306	rgmii-channel = <1>;
0a6ea8be SR	307	has-inverted-stacr-oc;
0a6ea8be SR	308	has-new-stacr-staopc;
a62f48de SR	309	};
a62f48de SR	310	};
151161c6 SR	311
	312	PCIE0: pciex@0a0000000 {
	313	device_type = "pci";
	314	#interrupt-cells = <1>;
	315	#size-cells = <2>;
	316	#address-cells = <3>;
	317	compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex";
	318	primary;
71f34979 DG	319	port = <0x0>; /* port number */
	320	reg = <0xa0000000 0x20000000 /* Config space access */
	321	0xef000000 0x00001000>; /* Registers */
	322	dcr-reg = <0x040 0x020>;
	323	sdr-base = <0x400>;
151161c6 SR	324
	325	/* Outbound ranges, one memory and one IO,
	326	* later cannot be changed
	327	*/
71f34979 DG	328	ranges = <0x02000000 0x00000000 0x80000000 0x90000000 0x00000000 0x08000000
71f34979 DG	329	0x01000000 0x00000000 0x00000000 0xe0000000 0x00000000 0x00010000>;
151161c6 SR	330
151161c6 SR	331	/* Inbound 2GB range starting at 0 */
71f34979	332	dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>;
151161c6	333
dc88416b	334	/* This drives busses 0x00 to 0x3f */
71f34979	335	bus-range = <0x0 0x3f>;
151161c6 SR	336
	337	/* Legacy interrupts (note the weird polarity, the bridge seems
	338	* to invert PCIe legacy interrupts).
	339	* We are de-swizzling here because the numbers are actually for
	340	* port of the root complex virtual P2P bridge. But I want
	341	* to avoid putting a node for it in the tree, so the numbers
	342	* below are basically de-swizzled numbers.
	343	* The real slot is on idsel 0, so the swizzling is 1:1
	344	*/
71f34979	345	interrupt-map-mask = <0x0 0x0 0x0 0x7>;
151161c6	346	interrupt-map = <
71f34979 DG	347	0x0 0x0 0x0 0x1 &UIC2 0x0 0x4 /* swizzled int A */
	348	0x0 0x0 0x0 0x2 &UIC2 0x1 0x4 /* swizzled int B */
	349	0x0 0x0 0x0 0x3 &UIC2 0x2 0x4 /* swizzled int C */
	350	0x0 0x0 0x0 0x4 &UIC2 0x3 0x4 /* swizzled int D */>;
151161c6 SR	351	};
	352
	353	PCIE1: pciex@0c0000000 {
	354	device_type = "pci";
	355	#interrupt-cells = <1>;
	356	#size-cells = <2>;
	357	#address-cells = <3>;
	358	compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex";
	359	primary;
71f34979 DG	360	port = <0x1>; /* port number */
	361	reg = <0xc0000000 0x20000000 /* Config space access */
	362	0xef001000 0x00001000>; /* Registers */
	363	dcr-reg = <0x060 0x020>;
	364	sdr-base = <0x440>;
151161c6 SR	365
	366	/* Outbound ranges, one memory and one IO,
	367	* later cannot be changed
	368	*/
71f34979 DG	369	ranges = <0x02000000 0x00000000 0x80000000 0x98000000 0x00000000 0x08000000
71f34979 DG	370	0x01000000 0x00000000 0x00000000 0xe0010000 0x00000000 0x00010000>;
151161c6 SR	371
151161c6 SR	372	/* Inbound 2GB range starting at 0 */
71f34979	373	dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>;
151161c6	374
dc88416b	375	/* This drives busses 0x40 to 0x7f */
71f34979	376	bus-range = <0x40 0x7f>;
151161c6 SR	377
	378	/* Legacy interrupts (note the weird polarity, the bridge seems
	379	* to invert PCIe legacy interrupts).
	380	* We are de-swizzling here because the numbers are actually for
	381	* port of the root complex virtual P2P bridge. But I want
	382	* to avoid putting a node for it in the tree, so the numbers
	383	* below are basically de-swizzled numbers.
	384	* The real slot is on idsel 0, so the swizzling is 1:1
	385	*/
71f34979	386	interrupt-map-mask = <0x0 0x0 0x0 0x7>;
151161c6	387	interrupt-map = <
71f34979 DG	388	0x0 0x0 0x0 0x1 &UIC2 0xb 0x4 /* swizzled int A */
	389	0x0 0x0 0x0 0x2 &UIC2 0xc 0x4 /* swizzled int B */
	390	0x0 0x0 0x0 0x3 &UIC2 0xd 0x4 /* swizzled int C */
	391	0x0 0x0 0x0 0x4 &UIC2 0xe 0x4 /* swizzled int D */>;
151161c6	392	};
a62f48de SR	393	};
a62f48de SR	394	};