[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / powerpc / boot / dts / katmai.dts

/*
 * Device Tree Source for AMCC Katmai eval board
 *
 * Copyright (c) 2006, 2007 IBM Corp.
 * Benjamin Herrenschmidt <benh@kernel.crashing.org>
 *
 * Copyright (c) 2006, 2007 IBM Corp.
 * Josh Boyer <jwboyer@linux.vnet.ibm.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without
 * any warranty of any kind, whether express or implied.
 */

/dts-v1/;

/ {
	#address-cells = <2>;
	#size-cells = <2>;
	model = "amcc,katmai";
	compatible = "amcc,katmai";
	dcr-parent = <&{/cpus/cpu@0}>;

	aliases {
		ethernet0 = &EMAC0;
		serial0 = &UART0;
		serial1 = &UART1;
		serial2 = &UART2;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			model = "PowerPC,440SPe";
			reg = <0x00000000>;
			clock-frequency = <0>; /* Filled in by zImage */
			timebase-frequency = <0>; /* Filled in by zImage */
			i-cache-line-size = <32>;
			d-cache-line-size = <32>;
			i-cache-size = <32768>;
			d-cache-size = <32768>;
			dcr-controller;
			dcr-access-method = "native";
		};
	};

	memory {
		device_type = "memory";
		reg = <0x0 0x00000000 0x0 0x00000000>; /* Filled in by U-Boot */
	};

	UIC0: interrupt-controller0 {
		compatible = "ibm,uic-440spe","ibm,uic";
		interrupt-controller;
		cell-index = <0>;
		dcr-reg = <0x0c0 0x009>;
		#address-cells = <0>;
		#size-cells = <0>;
		#interrupt-cells = <2>;
	};

	UIC1: interrupt-controller1 {
		compatible = "ibm,uic-440spe","ibm,uic";
		interrupt-controller;
		cell-index = <1>;
		dcr-reg = <0x0d0 0x009>;
		#address-cells = <0>;
		#size-cells = <0>;
		#interrupt-cells = <2>;
		interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
		interrupt-parent = <&UIC0>;
	};

	UIC2: interrupt-controller2 {
		compatible = "ibm,uic-440spe","ibm,uic";
		interrupt-controller;
		cell-index = <2>;
		dcr-reg = <0x0e0 0x009>;
		#address-cells = <0>;
		#size-cells = <0>;
		#interrupt-cells = <2>;
		interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
		interrupt-parent = <&UIC0>;
	};

	UIC3: interrupt-controller3 {
		compatible = "ibm,uic-440spe","ibm,uic";
		interrupt-controller;
		cell-index = <3>;
		dcr-reg = <0x0f0 0x009>;
		#address-cells = <0>;
		#size-cells = <0>;
		#interrupt-cells = <2>;
		interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
		interrupt-parent = <&UIC0>;
	};

	SDR0: sdr {
		compatible = "ibm,sdr-440spe";
		dcr-reg = <0x00e 0x002>;
	};

	CPR0: cpr {
		compatible = "ibm,cpr-440spe";
		dcr-reg = <0x00c 0x002>;
	};

	plb {
		compatible = "ibm,plb-440spe", "ibm,plb-440gp", "ibm,plb4";
		#address-cells = <2>;
		#size-cells = <1>;
		/*        addr-child     addr-parent    size */
		ranges = <0x4 0xe0000000 0x4 0xe0000000 0x20000000
			  0xc 0x00000000 0xc 0x00000000 0x20000000
			  0xd 0x00000000 0xd 0x00000000 0x80000000
			  0xd 0x80000000 0xd 0x80000000 0x80000000
			  0xe 0x00000000 0xe 0x00000000 0x80000000
			  0xe 0x80000000 0xe 0x80000000 0x80000000
			  0xf 0x00000000 0xf 0x00000000 0x80000000
			  0xf 0x80000000 0xf 0x80000000 0x80000000>;
		clock-frequency = <0>; /* Filled in by zImage */

		SDRAM0: sdram {
			compatible = "ibm,sdram-440spe", "ibm,sdram-405gp";
			dcr-reg = <0x010 0x002>;
		};

		MAL0: mcmal {
			compatible = "ibm,mcmal-440spe", "ibm,mcmal2";
			dcr-reg = <0x180 0x062>;
			num-tx-chans = <2>;
			num-rx-chans = <1>;
			interrupt-parent = <&MAL0>;
			interrupts = <0x0 0x1 0x2 0x3 0x4>;
			#interrupt-cells = <1>;
			#address-cells = <0>;
			#size-cells = <0>;
			interrupt-map = </*TXEOB*/ 0x0 &UIC1 0x6 0x4
					 /*RXEOB*/ 0x1 &UIC1 0x7 0x4
					 /*SERR*/  0x2 &UIC1 0x1 0x4
					 /*TXDE*/  0x3 &UIC1 0x2 0x4
					 /*RXDE*/  0x4 &UIC1 0x3 0x4>;
		};

		POB0: opb {
			compatible = "ibm,opb-440spe", "ibm,opb-440gp", "ibm,opb";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x00000000 0x00000004 0xe0000000 0x20000000>;
			clock-frequency = <0>; /* Filled in by zImage */

			EBC0: ebc {
				compatible = "ibm,ebc-440spe", "ibm,ebc-440gp", "ibm,ebc";
				dcr-reg = <0x012 0x002>;
				#address-cells = <2>;
				#size-cells = <1>;
				clock-frequency = <0>; /* Filled in by zImage */
				interrupts = <0x5 0x1>;
				interrupt-parent = <&UIC1>;
			};

			UART0: serial@10000200 {
				device_type = "serial";
				compatible = "ns16550";
				reg = <0x10000200 0x00000008>;
				virtual-reg = <0xa0000200>;
				clock-frequency = <0>; /* Filled in by zImage */
				current-speed = <115200>;
				interrupt-parent = <&UIC0>;
				interrupts = <0x0 0x4>;
			};

			UART1: serial@10000300 {
				device_type = "serial";
				compatible = "ns16550";
				reg = <0x10000300 0x00000008>;
				virtual-reg = <0xa0000300>;
				clock-frequency = <0>;
				current-speed = <0>;
				interrupt-parent = <&UIC0>;
				interrupts = <0x1 0x4>;
			};


			UART2: serial@10000600 {
				device_type = "serial";
				compatible = "ns16550";
				reg = <0x10000600 0x00000008>;
				virtual-reg = <0xa0000600>;
				clock-frequency = <0>;
				current-speed = <0>;
				interrupt-parent = <&UIC1>;
				interrupts = <0x5 0x4>;
			};

			IIC0: i2c@10000400 {
				compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic";
				reg = <0x10000400 0x00000014>;
				interrupt-parent = <&UIC0>;
				interrupts = <0x2 0x4>;
			};

			IIC1: i2c@10000500 {
				compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic";
				reg = <0x10000500 0x00000014>;
				interrupt-parent = <&UIC0>;
				interrupts = <0x3 0x4>;
			};

			EMAC0: ethernet@10000800 {
				linux,network-index = <0x0>;
				device_type = "network";
				compatible = "ibm,emac-440spe", "ibm,emac4";
				interrupt-parent = <&UIC1>;
				interrupts = <0x1c 0x4 0x1d 0x4>;
				reg = <0x10000800 0x00000074>;
				local-mac-address = [000000000000];
				mal-device = <&MAL0>;
				mal-tx-channel = <0>;
				mal-rx-channel = <0>;
				cell-index = <0>;
				max-frame-size = <9000>;
				rx-fifo-size = <4096>;
				tx-fifo-size = <2048>;
				phy-mode = "gmii";
				phy-map = <0x00000000>;
				has-inverted-stacr-oc;
				has-new-stacr-staopc;
			};
		};

		PCIX0: pci@c0ec00000 {
			device_type = "pci";
			#interrupt-cells = <1>;
			#size-cells = <2>;
			#address-cells = <3>;
			compatible = "ibm,plb-pcix-440spe", "ibm,plb-pcix";
			primary;
			large-inbound-windows;
			enable-msi-hole;
			reg = <0x0000000c 0x0ec00000   0x00000008	/* Config space access */
			       0x00000000 0x00000000 0x00000000		/* no IACK cycles */
			       0x0000000c 0x0ed00000   0x00000004   /* Special cycles */
			       0x0000000c 0x0ec80000 0x00000100	/* Internal registers */
			       0x0000000c 0x0ec80100  0x000000fc>;	/* Internal messaging registers */

			/* Outbound ranges, one memory and one IO,
			 * later cannot be changed
			 */
			ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000
				  0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>;

			/* Inbound 2GB range starting at 0 */
			dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;

			/* This drives busses 0 to 0xf */
			bus-range = <0x0 0xf>;

			/*
			 * On Katmai, the following PCI-X interrupts signals
			 * have to be enabled via jumpers (only INTA is
			 * enabled per default):
			 *
			 * INTB: J3: 1-2
			 * INTC: J2: 1-2
			 * INTD: J1: 1-2
			 */
			interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
			interrupt-map = <
				/* IDSEL 1 */
				0x800 0x0 0x0 0x1 &UIC1 0x14 0x8
				0x800 0x0 0x0 0x2 &UIC1 0x13 0x8
				0x800 0x0 0x0 0x3 &UIC1 0x12 0x8
				0x800 0x0 0x0 0x4 &UIC1 0x11 0x8
			>;
		};

		PCIE0: pciex@d00000000 {
			device_type = "pci";
			#interrupt-cells = <1>;
			#size-cells = <2>;
			#address-cells = <3>;
			compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex";
			primary;
			port = <0x0>; /* port number */
			reg = <0x0000000d 0x00000000 0x20000000	/* Config space access */
			       0x0000000c 0x10000000 0x00001000>;	/* Registers */
			dcr-reg = <0x100 0x020>;
			sdr-base = <0x300>;

			/* Outbound ranges, one memory and one IO,
			 * later cannot be changed
			 */
			ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
				  0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;

			/* Inbound 2GB range starting at 0 */
			dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;

			/* This drives busses 10 to 0x1f */
			bus-range = <0x10 0x1f>;

			/* Legacy interrupts (note the weird polarity, the bridge seems
			 * to invert PCIe legacy interrupts).
			 * We are de-swizzling here because the numbers are actually for
			 * port of the root complex virtual P2P bridge. But I want
			 * to avoid putting a node for it in the tree, so the numbers
			 * below are basically de-swizzled numbers.
			 * The real slot is on idsel 0, so the swizzling is 1:1
			 */
			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
			interrupt-map = <
				0x0 0x0 0x0 0x1 &UIC3 0x0 0x4 /* swizzled int A */
				0x0 0x0 0x0 0x2 &UIC3 0x1 0x4 /* swizzled int B */
				0x0 0x0 0x0 0x3 &UIC3 0x2 0x4 /* swizzled int C */
				0x0 0x0 0x0 0x4 &UIC3 0x3 0x4 /* swizzled int D */>;
		};

		PCIE1: pciex@d20000000 {
			device_type = "pci";
			#interrupt-cells = <1>;
			#size-cells = <2>;
			#address-cells = <3>;
			compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex";
			primary;
			port = <0x1>; /* port number */
			reg = <0x0000000d 0x20000000 0x20000000	/* Config space access */
			       0x0000000c 0x10001000 0x00001000>;	/* Registers */
			dcr-reg = <0x120 0x020>;
			sdr-base = <0x340>;

			/* Outbound ranges, one memory and one IO,
			 * later cannot be changed
			 */
			ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000
				  0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>;

			/* Inbound 2GB range starting at 0 */
			dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;

			/* This drives busses 10 to 0x1f */
			bus-range = <0x20 0x2f>;

			/* Legacy interrupts (note the weird polarity, the bridge seems
			 * to invert PCIe legacy interrupts).
			 * We are de-swizzling here because the numbers are actually for
			 * port of the root complex virtual P2P bridge. But I want
			 * to avoid putting a node for it in the tree, so the numbers
			 * below are basically de-swizzled numbers.
			 * The real slot is on idsel 0, so the swizzling is 1:1
			 */
			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
			interrupt-map = <
				0x0 0x0 0x0 0x1 &UIC3 0x4 0x4 /* swizzled int A */
				0x0 0x0 0x0 0x2 &UIC3 0x5 0x4 /* swizzled int B */
				0x0 0x0 0x0 0x3 &UIC3 0x6 0x4 /* swizzled int C */
				0x0 0x0 0x0 0x4 &UIC3 0x7 0x4 /* swizzled int D */>;
		};

		PCIE2: pciex@d40000000 {
			device_type = "pci";
			#interrupt-cells = <1>;
			#size-cells = <2>;
			#address-cells = <3>;
			compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex";
			primary;
			port = <0x2>; /* port number */
			reg = <0x0000000d 0x40000000 0x20000000	/* Config space access */
			       0x0000000c 0x10002000 0x00001000>;	/* Registers */
			dcr-reg = <0x140 0x020>;
			sdr-base = <0x370>;

			/* Outbound ranges, one memory and one IO,
			 * later cannot be changed
			 */
			ranges = <0x02000000 0x00000000 0x80000000 0x0000000f 0x00000000 0x00000000 0x80000000
				  0x01000000 0x00000000 0x00000000 0x0000000f 0x80020000 0x00000000 0x00010000>;

			/* Inbound 2GB range starting at 0 */
			dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;

			/* This drives busses 10 to 0x1f */
			bus-range = <0x30 0x3f>;

			/* Legacy interrupts (note the weird polarity, the bridge seems
			 * to invert PCIe legacy interrupts).
			 * We are de-swizzling here because the numbers are actually for
			 * port of the root complex virtual P2P bridge. But I want
			 * to avoid putting a node for it in the tree, so the numbers
			 * below are basically de-swizzled numbers.
			 * The real slot is on idsel 0, so the swizzling is 1:1
			 */
			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
			interrupt-map = <
				0x0 0x0 0x0 0x1 &UIC3 0x8 0x4 /* swizzled int A */
				0x0 0x0 0x0 0x2 &UIC3 0x9 0x4 /* swizzled int B */
				0x0 0x0 0x0 0x3 &UIC3 0xa 0x4 /* swizzled int C */
				0x0 0x0 0x0 0x4 &UIC3 0xb 0x4 /* swizzled int D */>;
		};
	};

	chosen {
		linux,stdout-path = "/plb/opb/serial@10000200";
	};
};
Commit	Line	Data
3de9c9cd BH	1	/*
	2	* Device Tree Source for AMCC Katmai eval board
	3	*
	4	* Copyright (c) 2006, 2007 IBM Corp.
	5	* Benjamin Herrenschmidt <benh@kernel.crashing.org>
	6	*
	7	* Copyright (c) 2006, 2007 IBM Corp.
	8	* Josh Boyer <jwboyer@linux.vnet.ibm.com>
	9	*
	10	* This file is licensed under the terms of the GNU General Public
	11	* License version 2. This program is licensed "as is" without
	12	* any warranty of any kind, whether express or implied.
	13	*/
	14
71f34979 DG	15	/dts-v1/;
71f34979 DG	16
3de9c9cd BH	17	/ {
3de9c9cd BH	18	#address-cells = <2>;
59e1d495	19	#size-cells = <2>;
3de9c9cd BH	20	model = "amcc,katmai";
3de9c9cd BH	21	compatible = "amcc,katmai";
71f34979	22	dcr-parent = <&{/cpus/cpu@0}>;
3de9c9cd	23
8aaed98c SR	24	aliases {
	25	ethernet0 = &EMAC0;
	26	serial0 = &UART0;
	27	serial1 = &UART1;
	28	serial2 = &UART2;
	29	};
	30
3de9c9cd BH	31	cpus {
	32	#address-cells = <1>;
	33	#size-cells = <0>;
	34
72fda114	35	cpu@0 {
3de9c9cd	36	device_type = "cpu";
72fda114	37	model = "PowerPC,440SPe";
71f34979	38	reg = <0x00000000>;
3de9c9cd BH	39	clock-frequency = <0>; /* Filled in by zImage */
3de9c9cd BH	40	timebase-frequency = <0>; /* Filled in by zImage */
71f34979 DG	41	i-cache-line-size = <32>;
	42	d-cache-line-size = <32>;
	43	i-cache-size = <32768>;
	44	d-cache-size = <32768>;
3de9c9cd BH	45	dcr-controller;
	46	dcr-access-method = "native";
	47	};
	48	};
	49
	50	memory {
	51	device_type = "memory";
59e1d495	52	reg = <0x0 0x00000000 0x0 0x00000000>; /* Filled in by U-Boot */
3de9c9cd BH	53	};
	54
	55	UIC0: interrupt-controller0 {
	56	compatible = "ibm,uic-440spe","ibm,uic";
	57	interrupt-controller;
	58	cell-index = <0>;
71f34979	59	dcr-reg = <0x0c0 0x009>;
3de9c9cd BH	60	#address-cells = <0>;
	61	#size-cells = <0>;
	62	#interrupt-cells = <2>;
	63	};
	64
	65	UIC1: interrupt-controller1 {
	66	compatible = "ibm,uic-440spe","ibm,uic";
	67	interrupt-controller;
	68	cell-index = <1>;
71f34979	69	dcr-reg = <0x0d0 0x009>;
3de9c9cd BH	70	#address-cells = <0>;
	71	#size-cells = <0>;
	72	#interrupt-cells = <2>;
71f34979	73	interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
3de9c9cd BH	74	interrupt-parent = <&UIC0>;
	75	};
	76
	77	UIC2: interrupt-controller2 {
	78	compatible = "ibm,uic-440spe","ibm,uic";
	79	interrupt-controller;
	80	cell-index = <2>;
71f34979	81	dcr-reg = <0x0e0 0x009>;
3de9c9cd BH	82	#address-cells = <0>;
	83	#size-cells = <0>;
	84	#interrupt-cells = <2>;
71f34979	85	interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
3de9c9cd BH	86	interrupt-parent = <&UIC0>;
	87	};
	88
	89	UIC3: interrupt-controller3 {
	90	compatible = "ibm,uic-440spe","ibm,uic";
	91	interrupt-controller;
	92	cell-index = <3>;
71f34979	93	dcr-reg = <0x0f0 0x009>;
3de9c9cd BH	94	#address-cells = <0>;
	95	#size-cells = <0>;
	96	#interrupt-cells = <2>;
71f34979	97	interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
3de9c9cd BH	98	interrupt-parent = <&UIC0>;
	99	};
	100
	101	SDR0: sdr {
	102	compatible = "ibm,sdr-440spe";
71f34979	103	dcr-reg = <0x00e 0x002>;
3de9c9cd BH	104	};
	105
	106	CPR0: cpr {
	107	compatible = "ibm,cpr-440spe";
71f34979	108	dcr-reg = <0x00c 0x002>;
3de9c9cd BH	109	};
	110
	111	plb {
	112	compatible = "ibm,plb-440spe", "ibm,plb-440gp", "ibm,plb4";
	113	#address-cells = <2>;
	114	#size-cells = <1>;
59e1d495 SR	115	/* addr-child addr-parent size */
	116	ranges = <0x4 0xe0000000 0x4 0xe0000000 0x20000000
	117	0xc 0x00000000 0xc 0x00000000 0x20000000
	118	0xd 0x00000000 0xd 0x00000000 0x80000000
	119	0xd 0x80000000 0xd 0x80000000 0x80000000
	120	0xe 0x00000000 0xe 0x00000000 0x80000000
	121	0xe 0x80000000 0xe 0x80000000 0x80000000
	122	0xf 0x00000000 0xf 0x00000000 0x80000000
	123	0xf 0x80000000 0xf 0x80000000 0x80000000>;
3de9c9cd BH	124	clock-frequency = <0>; /* Filled in by zImage */
	125
	126	SDRAM0: sdram {
	127	compatible = "ibm,sdram-440spe", "ibm,sdram-405gp";
71f34979	128	dcr-reg = <0x010 0x002>;
3de9c9cd BH	129	};
	130
	131	MAL0: mcmal {
	132	compatible = "ibm,mcmal-440spe", "ibm,mcmal2";
71f34979	133	dcr-reg = <0x180 0x062>;
3de9c9cd BH	134	num-tx-chans = <2>;
	135	num-rx-chans = <1>;
	136	interrupt-parent = <&MAL0>;
71f34979	137	interrupts = <0x0 0x1 0x2 0x3 0x4>;
3de9c9cd BH	138	#interrupt-cells = <1>;
	139	#address-cells = <0>;
	140	#size-cells = <0>;
71f34979 DG	141	interrupt-map = </TXEOB/ 0x0 &UIC1 0x6 0x4
	142	/RXEOB/ 0x1 &UIC1 0x7 0x4
	143	/SERR/ 0x2 &UIC1 0x1 0x4
	144	/TXDE/ 0x3 &UIC1 0x2 0x4
	145	/RXDE/ 0x4 &UIC1 0x3 0x4>;
3de9c9cd BH	146	};
	147
	148	POB0: opb {
3db3ba03	149	compatible = "ibm,opb-440spe", "ibm,opb-440gp", "ibm,opb";
3de9c9cd BH	150	#address-cells = <1>;
3de9c9cd BH	151	#size-cells = <1>;
71f34979	152	ranges = <0x00000000 0x00000004 0xe0000000 0x20000000>;
3db3ba03	153	clock-frequency = <0>; /* Filled in by zImage */
3de9c9cd BH	154
	155	EBC0: ebc {
	156	compatible = "ibm,ebc-440spe", "ibm,ebc-440gp", "ibm,ebc";
71f34979	157	dcr-reg = <0x012 0x002>;
3de9c9cd BH	158	#address-cells = <2>;
	159	#size-cells = <1>;
	160	clock-frequency = <0>; /* Filled in by zImage */
71f34979	161	interrupts = <0x5 0x1>;
3de9c9cd BH	162	interrupt-parent = <&UIC1>;
	163	};
	164
	165	UART0: serial@10000200 {
3db3ba03 SR	166	device_type = "serial";
3db3ba03 SR	167	compatible = "ns16550";
71f34979 DG	168	reg = <0x10000200 0x00000008>;
71f34979 DG	169	virtual-reg = <0xa0000200>;
3db3ba03	170	clock-frequency = <0>; /* Filled in by zImage */
71f34979	171	current-speed = <115200>;
3db3ba03	172	interrupt-parent = <&UIC0>;
71f34979	173	interrupts = <0x0 0x4>;
3db3ba03	174	};
3de9c9cd BH	175
3de9c9cd BH	176	UART1: serial@10000300 {
3db3ba03 SR	177	device_type = "serial";
3db3ba03 SR	178	compatible = "ns16550";
71f34979 DG	179	reg = <0x10000300 0x00000008>;
71f34979 DG	180	virtual-reg = <0xa0000300>;
3db3ba03 SR	181	clock-frequency = <0>;
	182	current-speed = <0>;
	183	interrupt-parent = <&UIC0>;
71f34979	184	interrupts = <0x1 0x4>;
3db3ba03	185	};
3de9c9cd BH	186
	187
	188	UART2: serial@10000600 {
3db3ba03 SR	189	device_type = "serial";
3db3ba03 SR	190	compatible = "ns16550";
71f34979 DG	191	reg = <0x10000600 0x00000008>;
71f34979 DG	192	virtual-reg = <0xa0000600>;
3db3ba03 SR	193	clock-frequency = <0>;
	194	current-speed = <0>;
	195	interrupt-parent = <&UIC1>;
71f34979	196	interrupts = <0x5 0x4>;
3db3ba03	197	};
3de9c9cd BH	198
3de9c9cd BH	199	IIC0: i2c@10000400 {
3de9c9cd	200	compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic";
71f34979	201	reg = <0x10000400 0x00000014>;
3de9c9cd	202	interrupt-parent = <&UIC0>;
71f34979	203	interrupts = <0x2 0x4>;
3de9c9cd BH	204	};
	205
	206	IIC1: i2c@10000500 {
3de9c9cd	207	compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic";
71f34979	208	reg = <0x10000500 0x00000014>;
3de9c9cd	209	interrupt-parent = <&UIC0>;
71f34979	210	interrupts = <0x3 0x4>;
3de9c9cd BH	211	};
	212
	213	EMAC0: ethernet@10000800 {
71f34979	214	linux,network-index = <0x0>;
3de9c9cd BH	215	device_type = "network";
	216	compatible = "ibm,emac-440spe", "ibm,emac4";
	217	interrupt-parent = <&UIC1>;
71f34979	218	interrupts = <0x1c 0x4 0x1d 0x4>;
05781ccd	219	reg = <0x10000800 0x00000074>;
3de9c9cd BH	220	local-mac-address = [000000000000];
	221	mal-device = <&MAL0>;
	222	mal-tx-channel = <0>;
	223	mal-rx-channel = <0>;
	224	cell-index = <0>;
71f34979 DG	225	max-frame-size = <9000>;
	226	rx-fifo-size = <4096>;
	227	tx-fifo-size = <2048>;
3de9c9cd	228	phy-mode = "gmii";
71f34979	229	phy-map = <0x00000000>;
3de9c9cd BH	230	has-inverted-stacr-oc;
	231	has-new-stacr-staopc;
	232	};
	233	};
	234
	235	PCIX0: pci@c0ec00000 {
	236	device_type = "pci";
	237	#interrupt-cells = <1>;
	238	#size-cells = <2>;
	239	#address-cells = <3>;
	240	compatible = "ibm,plb-pcix-440spe", "ibm,plb-pcix";
	241	primary;
	242	large-inbound-windows;
	243	enable-msi-hole;
71f34979 DG	244	reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */
	245	0x00000000 0x00000000 0x00000000 /* no IACK cycles */
	246	0x0000000c 0x0ed00000 0x00000004 /* Special cycles */
	247	0x0000000c 0x0ec80000 0x00000100 /* Internal registers */
	248	0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */
3de9c9cd BH	249
	250	/* Outbound ranges, one memory and one IO,
	251	* later cannot be changed
	252	*/
71f34979 DG	253	ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000
71f34979 DG	254	0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>;
3de9c9cd BH	255
3de9c9cd BH	256	/* Inbound 2GB range starting at 0 */
71f34979	257	dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
3de9c9cd BH	258
3de9c9cd BH	259	/* This drives busses 0 to 0xf */
71f34979	260	bus-range = <0x0 0xf>;
3de9c9cd BH	261
	262	/*
	263	* On Katmai, the following PCI-X interrupts signals
	264	* have to be enabled via jumpers (only INTA is
	265	* enabled per default):
	266	*
	267	* INTB: J3: 1-2
	268	* INTC: J2: 1-2
	269	* INTD: J1: 1-2
	270	*/
71f34979	271	interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
3de9c9cd BH	272	interrupt-map = <
3de9c9cd BH	273	/* IDSEL 1 */
71f34979 DG	274	0x800 0x0 0x0 0x1 &UIC1 0x14 0x8
	275	0x800 0x0 0x0 0x2 &UIC1 0x13 0x8
	276	0x800 0x0 0x0 0x3 &UIC1 0x12 0x8
	277	0x800 0x0 0x0 0x4 &UIC1 0x11 0x8
3de9c9cd BH	278	>;
	279	};
	280
	281	PCIE0: pciex@d00000000 {
	282	device_type = "pci";
	283	#interrupt-cells = <1>;
	284	#size-cells = <2>;
	285	#address-cells = <3>;
accf5ef2	286	compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex";
3de9c9cd	287	primary;
71f34979 DG	288	port = <0x0>; /* port number */
	289	reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */
	290	0x0000000c 0x10000000 0x00001000>; /* Registers */
	291	dcr-reg = <0x100 0x020>;
	292	sdr-base = <0x300>;
3de9c9cd BH	293
	294	/* Outbound ranges, one memory and one IO,
	295	* later cannot be changed
	296	*/
71f34979 DG	297	ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
71f34979 DG	298	0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
3de9c9cd BH	299
3de9c9cd BH	300	/* Inbound 2GB range starting at 0 */
71f34979	301	dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
3de9c9cd BH	302
3de9c9cd BH	303	/* This drives busses 10 to 0x1f */
71f34979	304	bus-range = <0x10 0x1f>;
3de9c9cd BH	305
	306	/* Legacy interrupts (note the weird polarity, the bridge seems
	307	* to invert PCIe legacy interrupts).
	308	* We are de-swizzling here because the numbers are actually for
	309	* port of the root complex virtual P2P bridge. But I want
	310	* to avoid putting a node for it in the tree, so the numbers
	311	* below are basically de-swizzled numbers.
	312	* The real slot is on idsel 0, so the swizzling is 1:1
	313	*/
71f34979	314	interrupt-map-mask = <0x0 0x0 0x0 0x7>;
3de9c9cd	315	interrupt-map = <
71f34979 DG	316	0x0 0x0 0x0 0x1 &UIC3 0x0 0x4 /* swizzled int A */
	317	0x0 0x0 0x0 0x2 &UIC3 0x1 0x4 /* swizzled int B */
	318	0x0 0x0 0x0 0x3 &UIC3 0x2 0x4 /* swizzled int C */
	319	0x0 0x0 0x0 0x4 &UIC3 0x3 0x4 /* swizzled int D */>;
3de9c9cd BH	320	};
	321
	322	PCIE1: pciex@d20000000 {
	323	device_type = "pci";
	324	#interrupt-cells = <1>;
	325	#size-cells = <2>;
	326	#address-cells = <3>;
accf5ef2	327	compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex";
3de9c9cd	328	primary;
71f34979 DG	329	port = <0x1>; /* port number */
	330	reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */
	331	0x0000000c 0x10001000 0x00001000>; /* Registers */
	332	dcr-reg = <0x120 0x020>;
	333	sdr-base = <0x340>;
3de9c9cd BH	334
	335	/* Outbound ranges, one memory and one IO,
	336	* later cannot be changed
	337	*/
71f34979 DG	338	ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000
71f34979 DG	339	0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>;
3de9c9cd BH	340
3de9c9cd BH	341	/* Inbound 2GB range starting at 0 */
71f34979	342	dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
3de9c9cd BH	343
3de9c9cd BH	344	/* This drives busses 10 to 0x1f */
71f34979	345	bus-range = <0x20 0x2f>;
3de9c9cd BH	346
	347	/* Legacy interrupts (note the weird polarity, the bridge seems
	348	* to invert PCIe legacy interrupts).
	349	* We are de-swizzling here because the numbers are actually for
	350	* port of the root complex virtual P2P bridge. But I want
	351	* to avoid putting a node for it in the tree, so the numbers
	352	* below are basically de-swizzled numbers.
	353	* The real slot is on idsel 0, so the swizzling is 1:1
	354	*/
71f34979	355	interrupt-map-mask = <0x0 0x0 0x0 0x7>;
3de9c9cd	356	interrupt-map = <
71f34979 DG	357	0x0 0x0 0x0 0x1 &UIC3 0x4 0x4 /* swizzled int A */
	358	0x0 0x0 0x0 0x2 &UIC3 0x5 0x4 /* swizzled int B */
	359	0x0 0x0 0x0 0x3 &UIC3 0x6 0x4 /* swizzled int C */
	360	0x0 0x0 0x0 0x4 &UIC3 0x7 0x4 /* swizzled int D */>;
3de9c9cd BH	361	};
	362
	363	PCIE2: pciex@d40000000 {
	364	device_type = "pci";
	365	#interrupt-cells = <1>;
	366	#size-cells = <2>;
	367	#address-cells = <3>;
accf5ef2	368	compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex";
3de9c9cd	369	primary;
71f34979 DG	370	port = <0x2>; /* port number */
	371	reg = <0x0000000d 0x40000000 0x20000000 /* Config space access */
	372	0x0000000c 0x10002000 0x00001000>; /* Registers */
	373	dcr-reg = <0x140 0x020>;
	374	sdr-base = <0x370>;
3de9c9cd BH	375
	376	/* Outbound ranges, one memory and one IO,
	377	* later cannot be changed
	378	*/
71f34979 DG	379	ranges = <0x02000000 0x00000000 0x80000000 0x0000000f 0x00000000 0x00000000 0x80000000
71f34979 DG	380	0x01000000 0x00000000 0x00000000 0x0000000f 0x80020000 0x00000000 0x00010000>;
3de9c9cd BH	381
3de9c9cd BH	382	/* Inbound 2GB range starting at 0 */
71f34979	383	dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
3de9c9cd BH	384
3de9c9cd BH	385	/* This drives busses 10 to 0x1f */
71f34979	386	bus-range = <0x30 0x3f>;
3de9c9cd BH	387
	388	/* Legacy interrupts (note the weird polarity, the bridge seems
	389	* to invert PCIe legacy interrupts).
	390	* We are de-swizzling here because the numbers are actually for
	391	* port of the root complex virtual P2P bridge. But I want
	392	* to avoid putting a node for it in the tree, so the numbers
	393	* below are basically de-swizzled numbers.
	394	* The real slot is on idsel 0, so the swizzling is 1:1
	395	*/
71f34979	396	interrupt-map-mask = <0x0 0x0 0x0 0x7>;
3de9c9cd	397	interrupt-map = <
71f34979 DG	398	0x0 0x0 0x0 0x1 &UIC3 0x8 0x4 /* swizzled int A */
	399	0x0 0x0 0x0 0x2 &UIC3 0x9 0x4 /* swizzled int B */
	400	0x0 0x0 0x0 0x3 &UIC3 0xa 0x4 /* swizzled int C */
	401	0x0 0x0 0x0 0x4 &UIC3 0xb 0x4 /* swizzled int D */>;
3de9c9cd BH	402	};
	403	};
	404
	405	chosen {
	406	linux,stdout-path = "/plb/opb/serial@10000200";
	407	};
	408	};