[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / powerpc / boot / dts / ebony.dts

/*
 * Device Tree Source for IBM Ebony
 *
 * Copyright (c) 2006, 2007 IBM Corp.
 * Josh Boyer <jwboyer@linux.vnet.ibm.com>, David Gibson <dwg@au1.ibm.com>
 *
 * FIXME: Draft only!
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without
 * any warranty of any kind, whether express or implied.
 */

/dts-v1/;

/ {
	#address-cells = <2>;
	#size-cells = <1>;
	model = "ibm,ebony";
	compatible = "ibm,ebony";
	dcr-parent = <&{/cpus/cpu@0}>;

	aliases {
		ethernet0 = &EMAC0;
		ethernet1 = &EMAC1;
		serial0 = &UART0;
		serial1 = &UART1;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			model = "PowerPC,440GP";
			reg = <0x00000000>;
			clock-frequency = <0>; // Filled in by zImage
			timebase-frequency = <0>; // Filled in by zImage
			i-cache-line-size = <32>;
			d-cache-line-size = <32>;
			i-cache-size = <32768>; /* 32 kB */
			d-cache-size = <32768>; /* 32 kB */
			dcr-controller;
			dcr-access-method = "native";
		};
	};

	memory {
		device_type = "memory";
		reg = <0x00000000 0x00000000 0x00000000>; // Filled in by zImage
	};

	UIC0: interrupt-controller0 {
		compatible = "ibm,uic-440gp", "ibm,uic";
		interrupt-controller;
		cell-index = <0>;
		dcr-reg = <0x0c0 0x009>;
		#address-cells = <0>;
		#size-cells = <0>;
		#interrupt-cells = <2>;

	};

	UIC1: interrupt-controller1 {
		compatible = "ibm,uic-440gp", "ibm,uic";
		interrupt-controller;
		cell-index = <1>;
		dcr-reg = <0x0d0 0x009>;
		#address-cells = <0>;
		#size-cells = <0>;
		#interrupt-cells = <2>;
		interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
		interrupt-parent = <&UIC0>;
	};

	CPC0: cpc {
		compatible = "ibm,cpc-440gp";
		dcr-reg = <0x0b0 0x003 0x0e0 0x010>;
		// FIXME: anything else?
	};

	plb {
		compatible = "ibm,plb-440gp", "ibm,plb4";
		#address-cells = <2>;
		#size-cells = <1>;
		ranges;
		clock-frequency = <0>; // Filled in by zImage

		SDRAM0: memory-controller {
			compatible = "ibm,sdram-440gp";
			dcr-reg = <0x010 0x002>;
			// FIXME: anything else?
		};

		SRAM0: sram {
			compatible = "ibm,sram-440gp";
			dcr-reg = <0x020 0x008 0x00a 0x001>;
		};

		DMA0: dma {
			// FIXME: ???
			compatible = "ibm,dma-440gp";
			dcr-reg = <0x100 0x027>;
		};

		MAL0: mcmal {
			compatible = "ibm,mcmal-440gp", "ibm,mcmal";
			dcr-reg = <0x180 0x062>;
			num-tx-chans = <4>;
			num-rx-chans = <4>;
			interrupt-parent = <&MAL0>;
			interrupts = <0x0 0x1 0x2 0x3 0x4>;
			#interrupt-cells = <1>;
			#address-cells = <0>;
			#size-cells = <0>;
			interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4
					 /*RXEOB*/ 0x1 &UIC0 0xb 0x4
					 /*SERR*/  0x2 &UIC1 0x0 0x4
					 /*TXDE*/  0x3 &UIC1 0x1 0x4
					 /*RXDE*/  0x4 &UIC1 0x2 0x4>;
			interrupt-map-mask = <0xffffffff>;
		};

		POB0: opb {
			compatible = "ibm,opb-440gp", "ibm,opb";
			#address-cells = <1>;
			#size-cells = <1>;
			/* Wish there was a nicer way of specifying a full 32-bit
			   range */
			ranges = <0x00000000 0x00000001 0x00000000 0x80000000
				  0x80000000 0x00000001 0x80000000 0x80000000>;
			dcr-reg = <0x090 0x00b>;
			interrupt-parent = <&UIC1>;
			interrupts = <0x7 0x4>;
			clock-frequency = <0>; // Filled in by zImage

			EBC0: ebc {
				compatible = "ibm,ebc-440gp", "ibm,ebc";
				dcr-reg = <0x012 0x002>;
				#address-cells = <2>;
				#size-cells = <1>;
				clock-frequency = <0>; // Filled in by zImage
				// ranges property is supplied by zImage
				// based on firmware's configuration of the
				// EBC bridge
				interrupts = <0x5 0x4>;
				interrupt-parent = <&UIC1>;

				small-flash@0,80000 {
					compatible = "jedec-flash";
					bank-width = <1>;
					reg = <0x00000000 0x00080000 0x00080000>;
					#address-cells = <1>;
					#size-cells = <1>;
					partition@0 {
						label = "OpenBIOS";
						reg = <0x00000000 0x00080000>;
						read-only;
					};
				};

				nvram@1,0 {
					/* NVRAM & RTC */
					compatible = "ds1743-nvram";
					#bytes = <0x2000>;
					reg = <0x00000001 0x00000000 0x00002000>;
				};

				large-flash@2,0 {
					compatible = "jedec-flash";
					bank-width = <1>;
					reg = <0x00000002 0x00000000 0x00400000>;
					#address-cells = <1>;
					#size-cells = <1>;
					partition@0 {
						label = "fs";
						reg = <0x00000000 0x00380000>;
					};
					partition@380000 {
						label = "firmware";
						reg = <0x00380000 0x00080000>;
					};
				};

				ir@3,0 {
					reg = <0x00000003 0x00000000 0x00000010>;
				};

				fpga@7,0 {
					compatible = "Ebony-FPGA";
					reg = <0x00000007 0x00000000 0x00000010>;
					virtual-reg = <0xe8300000>;
				};
			};

			UART0: serial@40000200 {
				device_type = "serial";
				compatible = "ns16550";
				reg = <0x40000200 0x00000008>;
				virtual-reg = <0xe0000200>;
				clock-frequency = <11059200>;
				current-speed = <9600>;
				interrupt-parent = <&UIC0>;
				interrupts = <0x0 0x4>;
			};

			UART1: serial@40000300 {
				device_type = "serial";
				compatible = "ns16550";
				reg = <0x40000300 0x00000008>;
				virtual-reg = <0xe0000300>;
				clock-frequency = <11059200>;
				current-speed = <9600>;
				interrupt-parent = <&UIC0>;
				interrupts = <0x1 0x4>;
			};

			IIC0: i2c@40000400 {
				/* FIXME */
				compatible = "ibm,iic-440gp", "ibm,iic";
				reg = <0x40000400 0x00000014>;
				interrupt-parent = <&UIC0>;
				interrupts = <0x2 0x4>;
			};
			IIC1: i2c@40000500 {
				/* FIXME */
				compatible = "ibm,iic-440gp", "ibm,iic";
				reg = <0x40000500 0x00000014>;
				interrupt-parent = <&UIC0>;
				interrupts = <0x3 0x4>;
			};

			GPIO0: gpio@40000700 {
				/* FIXME */
				compatible = "ibm,gpio-440gp";
				reg = <0x40000700 0x00000020>;
			};

			ZMII0: emac-zmii@40000780 {
				compatible = "ibm,zmii-440gp", "ibm,zmii";
				reg = <0x40000780 0x0000000c>;
			};

			EMAC0: ethernet@40000800 {
				device_type = "network";
				compatible = "ibm,emac-440gp", "ibm,emac";
				interrupt-parent = <&UIC1>;
				interrupts = <0x1c 0x4 0x1d 0x4>;
				reg = <0x40000800 0x00000070>;
				local-mac-address = [000000000000]; // Filled in by zImage
				mal-device = <&MAL0>;
				mal-tx-channel = <0 1>;
				mal-rx-channel = <0>;
				cell-index = <0>;
				max-frame-size = <1500>;
				rx-fifo-size = <4096>;
				tx-fifo-size = <2048>;
				phy-mode = "rmii";
				phy-map = <0x00000001>;
				zmii-device = <&ZMII0>;
				zmii-channel = <0>;
			};
			EMAC1: ethernet@40000900 {
				device_type = "network";
				compatible = "ibm,emac-440gp", "ibm,emac";
				interrupt-parent = <&UIC1>;
				interrupts = <0x1e 0x4 0x1f 0x4>;
				reg = <0x40000900 0x00000070>;
				local-mac-address = [000000000000]; // Filled in by zImage
				mal-device = <&MAL0>;
				mal-tx-channel = <2 3>;
				mal-rx-channel = <1>;
				cell-index = <1>;
				max-frame-size = <1500>;
				rx-fifo-size = <4096>;
				tx-fifo-size = <2048>;
				phy-mode = "rmii";
				phy-map = <0x00000001>;
				zmii-device = <&ZMII0>;
				zmii-channel = <1>;
			};


			GPT0: gpt@40000a00 {
				/* FIXME */
				reg = <0x40000a00 0x000000d4>;
				interrupt-parent = <&UIC0>;
				interrupts = <0x12 0x4 0x13 0x4 0x14 0x4 0x15 0x4 0x16 0x4>;
			};

		};

		PCIX0: pci@20ec00000 {
			device_type = "pci";
			#interrupt-cells = <1>;
			#size-cells = <2>;
			#address-cells = <3>;
			compatible = "ibm,plb440gp-pcix", "ibm,plb-pcix";
			primary;
			reg = <0x00000002 0x0ec00000 0x00000008	/* Config space access */
			       0x00000000 0x00000000 0x00000000		/* no IACK cycles */
			       0x00000002 0x0ed00000 0x00000004     /* Special cycles */
			       0x00000002 0x0ec80000 0x000000f0	/* Internal registers */
			       0x00000002 0x0ec80100 0x000000fc>;	/* Internal messaging registers */

			/* Outbound ranges, one memory and one IO,
			 * later cannot be changed
			 */
			ranges = <0x02000000 0x00000000 0x80000000 0x00000003 0x80000000 0x00000000 0x80000000
				  0x01000000 0x00000000 0x00000000 0x00000002 0x08000000 0x00000000 0x00010000>;

			/* Inbound 2GB range starting at 0 */
			dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;

			/* Ebony has all 4 IRQ pins tied together per slot */
			interrupt-map-mask = <0xf800 0x0 0x0 0x0>;
			interrupt-map = <
				/* IDSEL 1 */
				0x800 0x0 0x0 0x0 &UIC0 0x17 0x8

				/* IDSEL 2 */
				0x1000 0x0 0x0 0x0 &UIC0 0x18 0x8

				/* IDSEL 3 */
				0x1800 0x0 0x0 0x0 &UIC0 0x19 0x8

				/* IDSEL 4 */
				0x2000 0x0 0x0 0x0 &UIC0 0x1a 0x8
			>;
		};
	};

	chosen {
		linux,stdout-path = "/plb/opb/serial@40000200";
	};
};
Commit	Line	Data
ea20ff5d DG	1	/*
	2	* Device Tree Source for IBM Ebony
	3	*
	4	* Copyright (c) 2006, 2007 IBM Corp.
	5	* Josh Boyer <jwboyer@linux.vnet.ibm.com>, David Gibson <dwg@au1.ibm.com>
	6	*
	7	* FIXME: Draft only!
	8	*
	9	* This file is licensed under the terms of the GNU General Public
	10	* License version 2. This program is licensed "as is" without
	11	* any warranty of any kind, whether express or implied.
ea20ff5d DG	12	*/
ea20ff5d DG	13
71f34979 DG	14	/dts-v1/;
71f34979 DG	15
ea20ff5d DG	16	/ {
	17	#address-cells = <2>;
	18	#size-cells = <1>;
	19	model = "ibm,ebony";
	20	compatible = "ibm,ebony";
71f34979	21	dcr-parent = <&{/cpus/cpu@0}>;
8aaed98c SR	22
	23	aliases {
	24	ethernet0 = &EMAC0;
	25	ethernet1 = &EMAC1;
	26	serial0 = &UART0;
	27	serial1 = &UART1;
	28	};
ea20ff5d DG	29
	30	cpus {
	31	#address-cells = <1>;
	32	#size-cells = <0>;
	33
72fda114	34	cpu@0 {
ea20ff5d	35	device_type = "cpu";
72fda114	36	model = "PowerPC,440GP";
71f34979	37	reg = <0x00000000>;
ea20ff5d DG	38	clock-frequency = <0>; // Filled in by zImage
ea20ff5d DG	39	timebase-frequency = <0>; // Filled in by zImage
71f34979 DG	40	i-cache-line-size = <32>;
	41	d-cache-line-size = <32>;
	42	i-cache-size = <32768>; /* 32 kB */
	43	d-cache-size = <32768>; /* 32 kB */
ea20ff5d DG	44	dcr-controller;
	45	dcr-access-method = "native";
	46	};
	47	};
	48
	49	memory {
	50	device_type = "memory";
71f34979	51	reg = <0x00000000 0x00000000 0x00000000>; // Filled in by zImage
ea20ff5d DG	52	};
	53
	54	UIC0: interrupt-controller0 {
ea20ff5d DG	55	compatible = "ibm,uic-440gp", "ibm,uic";
	56	interrupt-controller;
	57	cell-index = <0>;
71f34979	58	dcr-reg = <0x0c0 0x009>;
ea20ff5d DG	59	#address-cells = <0>;
	60	#size-cells = <0>;
	61	#interrupt-cells = <2>;
	62
	63	};
	64
	65	UIC1: interrupt-controller1 {
ea20ff5d DG	66	compatible = "ibm,uic-440gp", "ibm,uic";
	67	interrupt-controller;
	68	cell-index = <1>;
71f34979	69	dcr-reg = <0x0d0 0x009>;
ea20ff5d DG	70	#address-cells = <0>;
	71	#size-cells = <0>;
	72	#interrupt-cells = <2>;
71f34979	73	interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
ea20ff5d DG	74	interrupt-parent = <&UIC0>;
	75	};
	76
	77	CPC0: cpc {
ea20ff5d	78	compatible = "ibm,cpc-440gp";
71f34979	79	dcr-reg = <0x0b0 0x003 0x0e0 0x010>;
ea20ff5d DG	80	// FIXME: anything else?
	81	};
	82
	83	plb {
ea20ff5d DG	84	compatible = "ibm,plb-440gp", "ibm,plb4";
	85	#address-cells = <2>;
	86	#size-cells = <1>;
	87	ranges;
	88	clock-frequency = <0>; // Filled in by zImage
	89
c72ea777 DG	90	SDRAM0: memory-controller {
c72ea777 DG	91	compatible = "ibm,sdram-440gp";
71f34979	92	dcr-reg = <0x010 0x002>;
ea20ff5d DG	93	// FIXME: anything else?
	94	};
	95
c72ea777 DG	96	SRAM0: sram {
c72ea777 DG	97	compatible = "ibm,sram-440gp";
71f34979	98	dcr-reg = <0x020 0x008 0x00a 0x001>;
c72ea777 DG	99	};
c72ea777 DG	100
ea20ff5d DG	101	DMA0: dma {
ea20ff5d DG	102	// FIXME: ???
c72ea777	103	compatible = "ibm,dma-440gp";
71f34979	104	dcr-reg = <0x100 0x027>;
ea20ff5d DG	105	};
	106
	107	MAL0: mcmal {
ea20ff5d	108	compatible = "ibm,mcmal-440gp", "ibm,mcmal";
71f34979	109	dcr-reg = <0x180 0x062>;
ea20ff5d DG	110	num-tx-chans = <4>;
	111	num-rx-chans = <4>;
	112	interrupt-parent = <&MAL0>;
71f34979	113	interrupts = <0x0 0x1 0x2 0x3 0x4>;
ea20ff5d DG	114	#interrupt-cells = <1>;
	115	#address-cells = <0>;
	116	#size-cells = <0>;
71f34979 DG	117	interrupt-map = </TXEOB/ 0x0 &UIC0 0xa 0x4
	118	/RXEOB/ 0x1 &UIC0 0xb 0x4
	119	/SERR/ 0x2 &UIC1 0x0 0x4
	120	/TXDE/ 0x3 &UIC1 0x1 0x4
	121	/RXDE/ 0x4 &UIC1 0x2 0x4>;
	122	interrupt-map-mask = <0xffffffff>;
ea20ff5d DG	123	};
	124
	125	POB0: opb {
ea20ff5d DG	126	compatible = "ibm,opb-440gp", "ibm,opb";
	127	#address-cells = <1>;
	128	#size-cells = <1>;
	129	/* Wish there was a nicer way of specifying a full 32-bit
	130	range */
71f34979 DG	131	ranges = <0x00000000 0x00000001 0x00000000 0x80000000
	132	0x80000000 0x00000001 0x80000000 0x80000000>;
	133	dcr-reg = <0x090 0x00b>;
ea20ff5d	134	interrupt-parent = <&UIC1>;
71f34979	135	interrupts = <0x7 0x4>;
ea20ff5d DG	136	clock-frequency = <0>; // Filled in by zImage
	137
	138	EBC0: ebc {
c72ea777	139	compatible = "ibm,ebc-440gp", "ibm,ebc";
71f34979	140	dcr-reg = <0x012 0x002>;
ea20ff5d DG	141	#address-cells = <2>;
	142	#size-cells = <1>;
	143	clock-frequency = <0>; // Filled in by zImage
b2ba34f3 DG	144	// ranges property is supplied by zImage
	145	// based on firmware's configuration of the
	146	// EBC bridge
71f34979	147	interrupts = <0x5 0x4>;
ea20ff5d DG	148	interrupt-parent = <&UIC1>;
ea20ff5d DG	149
c72ea777	150	small-flash@0,80000 {
2099172d	151	compatible = "jedec-flash";
ea20ff5d	152	bank-width = <1>;
71f34979	153	reg = <0x00000000 0x00080000 0x00080000>;
2099172d DG	154	#address-cells = <1>;
	155	#size-cells = <1>;
	156	partition@0 {
	157	label = "OpenBIOS";
71f34979	158	reg = <0x00000000 0x00080000>;
2099172d DG	159	read-only;
2099172d DG	160	};
ea20ff5d DG	161	};
ea20ff5d DG	162
22258fa4	163	nvram@1,0 {
ea20ff5d	164	/* NVRAM & RTC */
22258fa4	165	compatible = "ds1743-nvram";
71f34979 DG	166	#bytes = <0x2000>;
71f34979 DG	167	reg = <0x00000001 0x00000000 0x00002000>;
ea20ff5d DG	168	};
	169
	170	large-flash@2,0 {
2099172d	171	compatible = "jedec-flash";
ea20ff5d	172	bank-width = <1>;
71f34979	173	reg = <0x00000002 0x00000000 0x00400000>;
2099172d DG	174	#address-cells = <1>;
	175	#size-cells = <1>;
	176	partition@0 {
	177	label = "fs";
71f34979	178	reg = <0x00000000 0x00380000>;
2099172d DG	179	};
	180	partition@380000 {
	181	label = "firmware";
71f34979	182	reg = <0x00380000 0x00080000>;
2099172d	183	};
ea20ff5d DG	184	};
	185
	186	ir@3,0 {
71f34979	187	reg = <0x00000003 0x00000000 0x00000010>;
ea20ff5d DG	188	};
	189
	190	fpga@7,0 {
	191	compatible = "Ebony-FPGA";
71f34979 DG	192	reg = <0x00000007 0x00000000 0x00000010>;
71f34979 DG	193	virtual-reg = <0xe8300000>;
ea20ff5d DG	194	};
	195	};
	196
	197	UART0: serial@40000200 {
	198	device_type = "serial";
	199	compatible = "ns16550";
71f34979 DG	200	reg = <0x40000200 0x00000008>;
	201	virtual-reg = <0xe0000200>;
	202	clock-frequency = <11059200>;
	203	current-speed = <9600>;
ea20ff5d	204	interrupt-parent = <&UIC0>;
71f34979	205	interrupts = <0x0 0x4>;
ea20ff5d DG	206	};
	207
	208	UART1: serial@40000300 {
	209	device_type = "serial";
	210	compatible = "ns16550";
71f34979 DG	211	reg = <0x40000300 0x00000008>;
	212	virtual-reg = <0xe0000300>;
	213	clock-frequency = <11059200>;
	214	current-speed = <9600>;
ea20ff5d	215	interrupt-parent = <&UIC0>;
71f34979	216	interrupts = <0x1 0x4>;
ea20ff5d DG	217	};
	218
	219	IIC0: i2c@40000400 {
	220	/* FIXME */
ea20ff5d	221	compatible = "ibm,iic-440gp", "ibm,iic";
71f34979	222	reg = <0x40000400 0x00000014>;
ea20ff5d	223	interrupt-parent = <&UIC0>;
71f34979	224	interrupts = <0x2 0x4>;
ea20ff5d DG	225	};
	226	IIC1: i2c@40000500 {
	227	/* FIXME */
ea20ff5d	228	compatible = "ibm,iic-440gp", "ibm,iic";
71f34979	229	reg = <0x40000500 0x00000014>;
ea20ff5d	230	interrupt-parent = <&UIC0>;
71f34979	231	interrupts = <0x3 0x4>;
ea20ff5d DG	232	};
	233
	234	GPIO0: gpio@40000700 {
	235	/* FIXME */
ea20ff5d	236	compatible = "ibm,gpio-440gp";
71f34979	237	reg = <0x40000700 0x00000020>;
ea20ff5d DG	238	};
	239
	240	ZMII0: emac-zmii@40000780 {
ea20ff5d	241	compatible = "ibm,zmii-440gp", "ibm,zmii";
71f34979	242	reg = <0x40000780 0x0000000c>;
ea20ff5d DG	243	};
	244
	245	EMAC0: ethernet@40000800 {
ea20ff5d DG	246	device_type = "network";
	247	compatible = "ibm,emac-440gp", "ibm,emac";
	248	interrupt-parent = <&UIC1>;
71f34979 DG	249	interrupts = <0x1c 0x4 0x1d 0x4>;
71f34979 DG	250	reg = <0x40000800 0x00000070>;
ea20ff5d DG	251	local-mac-address = [000000000000]; // Filled in by zImage
	252	mal-device = <&MAL0>;
	253	mal-tx-channel = <0 1>;
	254	mal-rx-channel = <0>;
	255	cell-index = <0>;
71f34979 DG	256	max-frame-size = <1500>;
	257	rx-fifo-size = <4096>;
	258	tx-fifo-size = <2048>;
ea20ff5d	259	phy-mode = "rmii";
71f34979	260	phy-map = <0x00000001>;
ea20ff5d DG	261	zmii-device = <&ZMII0>;
	262	zmii-channel = <0>;
	263	};
	264	EMAC1: ethernet@40000900 {
ea20ff5d DG	265	device_type = "network";
	266	compatible = "ibm,emac-440gp", "ibm,emac";
	267	interrupt-parent = <&UIC1>;
71f34979 DG	268	interrupts = <0x1e 0x4 0x1f 0x4>;
71f34979 DG	269	reg = <0x40000900 0x00000070>;
ea20ff5d DG	270	local-mac-address = [000000000000]; // Filled in by zImage
	271	mal-device = <&MAL0>;
	272	mal-tx-channel = <2 3>;
	273	mal-rx-channel = <1>;
	274	cell-index = <1>;
71f34979 DG	275	max-frame-size = <1500>;
	276	rx-fifo-size = <4096>;
	277	tx-fifo-size = <2048>;
ea20ff5d	278	phy-mode = "rmii";
71f34979	279	phy-map = <0x00000001>;
ea20ff5d DG	280	zmii-device = <&ZMII0>;
	281	zmii-channel = <1>;
	282	};
	283
	284
	285	GPT0: gpt@40000a00 {
	286	/* FIXME */
71f34979	287	reg = <0x40000a00 0x000000d4>;
ea20ff5d	288	interrupt-parent = <&UIC0>;
71f34979	289	interrupts = <0x12 0x4 0x13 0x4 0x14 0x4 0x15 0x4 0x16 0x4>;
ea20ff5d DG	290	};
	291
	292	};
	293
69c07851	294	PCIX0: pci@20ec00000 {
ea20ff5d	295	device_type = "pci";
69c07851 BH	296	#interrupt-cells = <1>;
	297	#size-cells = <2>;
	298	#address-cells = <3>;
	299	compatible = "ibm,plb440gp-pcix", "ibm,plb-pcix";
	300	primary;
71f34979 DG	301	reg = <0x00000002 0x0ec00000 0x00000008 /* Config space access */
	302	0x00000000 0x00000000 0x00000000 /* no IACK cycles */
	303	0x00000002 0x0ed00000 0x00000004 /* Special cycles */
	304	0x00000002 0x0ec80000 0x000000f0 /* Internal registers */
	305	0x00000002 0x0ec80100 0x000000fc>; /* Internal messaging registers */
69c07851 BH	306
	307	/* Outbound ranges, one memory and one IO,
	308	* later cannot be changed
	309	*/
71f34979 DG	310	ranges = <0x02000000 0x00000000 0x80000000 0x00000003 0x80000000 0x00000000 0x80000000
71f34979 DG	311	0x01000000 0x00000000 0x00000000 0x00000002 0x08000000 0x00000000 0x00010000>;
69c07851 BH	312
69c07851 BH	313	/* Inbound 2GB range starting at 0 */
71f34979	314	dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
69c07851 BH	315
69c07851 BH	316	/* Ebony has all 4 IRQ pins tied together per slot */
71f34979	317	interrupt-map-mask = <0xf800 0x0 0x0 0x0>;
69c07851 BH	318	interrupt-map = <
69c07851 BH	319	/* IDSEL 1 */
71f34979	320	0x800 0x0 0x0 0x0 &UIC0 0x17 0x8
69c07851 BH	321
69c07851 BH	322	/* IDSEL 2 */
71f34979	323	0x1000 0x0 0x0 0x0 &UIC0 0x18 0x8
69c07851 BH	324
69c07851 BH	325	/* IDSEL 3 */
71f34979	326	0x1800 0x0 0x0 0x0 &UIC0 0x19 0x8
69c07851 BH	327
69c07851 BH	328	/* IDSEL 4 */
71f34979	329	0x2000 0x0 0x0 0x0 &UIC0 0x1a 0x8
69c07851	330	>;
ea20ff5d DG	331	};
	332	};
	333
	334	chosen {
	335	linux,stdout-path = "/plb/opb/serial@40000200";
ea20ff5d DG	336	};
ea20ff5d DG	337	};