Commit | Line | Data |
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8bc4a51d SR |
1 | /* |
2 | * Device Tree Source for AMCC Canyonlands (460EX) | |
3 | * | |
4 | * Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de> | |
5 | * | |
6 | * This file is licensed under the terms of the GNU General Public | |
7 | * License version 2. This program is licensed "as is" without | |
8 | * any warranty of any kind, whether express or implied. | |
9 | */ | |
10 | ||
71f34979 DG |
11 | /dts-v1/; |
12 | ||
8bc4a51d SR |
13 | / { |
14 | #address-cells = <2>; | |
15 | #size-cells = <1>; | |
16 | model = "amcc,canyonlands"; | |
17 | compatible = "amcc,canyonlands"; | |
71f34979 | 18 | dcr-parent = <&{/cpus/cpu@0}>; |
8bc4a51d SR |
19 | |
20 | aliases { | |
21 | ethernet0 = &EMAC0; | |
22 | ethernet1 = &EMAC1; | |
23 | serial0 = &UART0; | |
24 | serial1 = &UART1; | |
25 | }; | |
26 | ||
27 | cpus { | |
28 | #address-cells = <1>; | |
29 | #size-cells = <0>; | |
30 | ||
31 | cpu@0 { | |
32 | device_type = "cpu"; | |
33 | model = "PowerPC,460EX"; | |
71f34979 | 34 | reg = <0x00000000>; |
8bc4a51d SR |
35 | clock-frequency = <0>; /* Filled in by U-Boot */ |
36 | timebase-frequency = <0>; /* Filled in by U-Boot */ | |
71f34979 DG |
37 | i-cache-line-size = <32>; |
38 | d-cache-line-size = <32>; | |
39 | i-cache-size = <32768>; | |
40 | d-cache-size = <32768>; | |
8bc4a51d SR |
41 | dcr-controller; |
42 | dcr-access-method = "native"; | |
cd85400a | 43 | next-level-cache = <&L2C0>; |
8bc4a51d SR |
44 | }; |
45 | }; | |
46 | ||
47 | memory { | |
48 | device_type = "memory"; | |
71f34979 | 49 | reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */ |
8bc4a51d SR |
50 | }; |
51 | ||
52 | UIC0: interrupt-controller0 { | |
53 | compatible = "ibm,uic-460ex","ibm,uic"; | |
54 | interrupt-controller; | |
55 | cell-index = <0>; | |
71f34979 | 56 | dcr-reg = <0x0c0 0x009>; |
8bc4a51d SR |
57 | #address-cells = <0>; |
58 | #size-cells = <0>; | |
59 | #interrupt-cells = <2>; | |
60 | }; | |
61 | ||
62 | UIC1: interrupt-controller1 { | |
63 | compatible = "ibm,uic-460ex","ibm,uic"; | |
64 | interrupt-controller; | |
65 | cell-index = <1>; | |
71f34979 | 66 | dcr-reg = <0x0d0 0x009>; |
8bc4a51d SR |
67 | #address-cells = <0>; |
68 | #size-cells = <0>; | |
69 | #interrupt-cells = <2>; | |
71f34979 | 70 | interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ |
8bc4a51d SR |
71 | interrupt-parent = <&UIC0>; |
72 | }; | |
73 | ||
74 | UIC2: interrupt-controller2 { | |
75 | compatible = "ibm,uic-460ex","ibm,uic"; | |
76 | interrupt-controller; | |
77 | cell-index = <2>; | |
71f34979 | 78 | dcr-reg = <0x0e0 0x009>; |
8bc4a51d SR |
79 | #address-cells = <0>; |
80 | #size-cells = <0>; | |
81 | #interrupt-cells = <2>; | |
71f34979 | 82 | interrupts = <0xa 0x4 0xb 0x4>; /* cascade */ |
8bc4a51d SR |
83 | interrupt-parent = <&UIC0>; |
84 | }; | |
85 | ||
86 | UIC3: interrupt-controller3 { | |
87 | compatible = "ibm,uic-460ex","ibm,uic"; | |
88 | interrupt-controller; | |
89 | cell-index = <3>; | |
71f34979 | 90 | dcr-reg = <0x0f0 0x009>; |
8bc4a51d SR |
91 | #address-cells = <0>; |
92 | #size-cells = <0>; | |
93 | #interrupt-cells = <2>; | |
71f34979 | 94 | interrupts = <0x10 0x4 0x11 0x4>; /* cascade */ |
8bc4a51d SR |
95 | interrupt-parent = <&UIC0>; |
96 | }; | |
97 | ||
98 | SDR0: sdr { | |
99 | compatible = "ibm,sdr-460ex"; | |
71f34979 | 100 | dcr-reg = <0x00e 0x002>; |
8bc4a51d SR |
101 | }; |
102 | ||
103 | CPR0: cpr { | |
104 | compatible = "ibm,cpr-460ex"; | |
71f34979 | 105 | dcr-reg = <0x00c 0x002>; |
8bc4a51d SR |
106 | }; |
107 | ||
cd85400a SR |
108 | L2C0: l2c { |
109 | compatible = "ibm,l2-cache-460ex", "ibm,l2-cache"; | |
110 | dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */ | |
111 | 0x030 0x008>; /* L2 cache DCR's */ | |
112 | cache-line-size = <32>; /* 32 bytes */ | |
113 | cache-size = <262144>; /* L2, 256K */ | |
114 | interrupt-parent = <&UIC1>; | |
115 | interrupts = <11 1>; | |
116 | }; | |
117 | ||
8bc4a51d SR |
118 | plb { |
119 | compatible = "ibm,plb-460ex", "ibm,plb4"; | |
120 | #address-cells = <2>; | |
121 | #size-cells = <1>; | |
122 | ranges; | |
123 | clock-frequency = <0>; /* Filled in by U-Boot */ | |
124 | ||
125 | SDRAM0: sdram { | |
126 | compatible = "ibm,sdram-460ex", "ibm,sdram-405gp"; | |
71f34979 | 127 | dcr-reg = <0x010 0x002>; |
8bc4a51d SR |
128 | }; |
129 | ||
130 | MAL0: mcmal { | |
131 | compatible = "ibm,mcmal-460ex", "ibm,mcmal2"; | |
71f34979 | 132 | dcr-reg = <0x180 0x062>; |
8bc4a51d | 133 | num-tx-chans = <2>; |
71f34979 | 134 | num-rx-chans = <16>; |
8bc4a51d SR |
135 | #address-cells = <0>; |
136 | #size-cells = <0>; | |
137 | interrupt-parent = <&UIC2>; | |
71f34979 DG |
138 | interrupts = < /*TXEOB*/ 0x6 0x4 |
139 | /*RXEOB*/ 0x7 0x4 | |
140 | /*SERR*/ 0x3 0x4 | |
141 | /*TXDE*/ 0x4 0x4 | |
142 | /*RXDE*/ 0x5 0x4>; | |
8bc4a51d SR |
143 | }; |
144 | ||
145 | POB0: opb { | |
146 | compatible = "ibm,opb-460ex", "ibm,opb"; | |
147 | #address-cells = <1>; | |
148 | #size-cells = <1>; | |
71f34979 | 149 | ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>; |
8bc4a51d SR |
150 | clock-frequency = <0>; /* Filled in by U-Boot */ |
151 | ||
152 | EBC0: ebc { | |
153 | compatible = "ibm,ebc-460ex", "ibm,ebc"; | |
71f34979 | 154 | dcr-reg = <0x012 0x002>; |
8bc4a51d SR |
155 | #address-cells = <2>; |
156 | #size-cells = <1>; | |
157 | clock-frequency = <0>; /* Filled in by U-Boot */ | |
5020231b | 158 | /* ranges property is supplied by U-Boot */ |
71f34979 | 159 | interrupts = <0x6 0x4>; |
8bc4a51d | 160 | interrupt-parent = <&UIC1>; |
5020231b SR |
161 | |
162 | nor_flash@0,0 { | |
163 | compatible = "amd,s29gl512n", "cfi-flash"; | |
164 | bank-width = <2>; | |
71f34979 | 165 | reg = <0x00000000 0x00000000 0x04000000>; |
5020231b SR |
166 | #address-cells = <1>; |
167 | #size-cells = <1>; | |
168 | partition@0 { | |
169 | label = "kernel"; | |
71f34979 | 170 | reg = <0x00000000 0x001e0000>; |
5020231b SR |
171 | }; |
172 | partition@1e0000 { | |
173 | label = "dtb"; | |
71f34979 | 174 | reg = <0x001e0000 0x00020000>; |
5020231b SR |
175 | }; |
176 | partition@200000 { | |
177 | label = "ramdisk"; | |
71f34979 | 178 | reg = <0x00200000 0x01400000>; |
5020231b SR |
179 | }; |
180 | partition@1600000 { | |
181 | label = "jffs2"; | |
71f34979 | 182 | reg = <0x01600000 0x00400000>; |
5020231b SR |
183 | }; |
184 | partition@1a00000 { | |
185 | label = "user"; | |
71f34979 | 186 | reg = <0x01a00000 0x02560000>; |
5020231b SR |
187 | }; |
188 | partition@3f60000 { | |
189 | label = "env"; | |
71f34979 | 190 | reg = <0x03f60000 0x00040000>; |
5020231b SR |
191 | }; |
192 | partition@3fa0000 { | |
193 | label = "u-boot"; | |
71f34979 | 194 | reg = <0x03fa0000 0x00060000>; |
5020231b SR |
195 | }; |
196 | }; | |
8bc4a51d SR |
197 | }; |
198 | ||
199 | UART0: serial@ef600300 { | |
200 | device_type = "serial"; | |
201 | compatible = "ns16550"; | |
71f34979 DG |
202 | reg = <0xef600300 0x00000008>; |
203 | virtual-reg = <0xef600300>; | |
8bc4a51d SR |
204 | clock-frequency = <0>; /* Filled in by U-Boot */ |
205 | current-speed = <0>; /* Filled in by U-Boot */ | |
206 | interrupt-parent = <&UIC1>; | |
71f34979 | 207 | interrupts = <0x1 0x4>; |
8bc4a51d SR |
208 | }; |
209 | ||
210 | UART1: serial@ef600400 { | |
211 | device_type = "serial"; | |
212 | compatible = "ns16550"; | |
71f34979 DG |
213 | reg = <0xef600400 0x00000008>; |
214 | virtual-reg = <0xef600400>; | |
8bc4a51d SR |
215 | clock-frequency = <0>; /* Filled in by U-Boot */ |
216 | current-speed = <0>; /* Filled in by U-Boot */ | |
217 | interrupt-parent = <&UIC0>; | |
71f34979 | 218 | interrupts = <0x1 0x4>; |
8bc4a51d SR |
219 | }; |
220 | ||
221 | UART2: serial@ef600500 { | |
222 | device_type = "serial"; | |
223 | compatible = "ns16550"; | |
71f34979 DG |
224 | reg = <0xef600500 0x00000008>; |
225 | virtual-reg = <0xef600500>; | |
8bc4a51d SR |
226 | clock-frequency = <0>; /* Filled in by U-Boot */ |
227 | current-speed = <0>; /* Filled in by U-Boot */ | |
228 | interrupt-parent = <&UIC1>; | |
71f34979 | 229 | interrupts = <0x1d 0x4>; |
8bc4a51d SR |
230 | }; |
231 | ||
232 | UART3: serial@ef600600 { | |
233 | device_type = "serial"; | |
234 | compatible = "ns16550"; | |
71f34979 DG |
235 | reg = <0xef600600 0x00000008>; |
236 | virtual-reg = <0xef600600>; | |
8bc4a51d SR |
237 | clock-frequency = <0>; /* Filled in by U-Boot */ |
238 | current-speed = <0>; /* Filled in by U-Boot */ | |
239 | interrupt-parent = <&UIC1>; | |
71f34979 | 240 | interrupts = <0x1e 0x4>; |
8bc4a51d SR |
241 | }; |
242 | ||
243 | IIC0: i2c@ef600700 { | |
244 | compatible = "ibm,iic-460ex", "ibm,iic"; | |
71f34979 | 245 | reg = <0xef600700 0x00000014>; |
8bc4a51d | 246 | interrupt-parent = <&UIC0>; |
71f34979 | 247 | interrupts = <0x2 0x4>; |
8bc4a51d SR |
248 | }; |
249 | ||
250 | IIC1: i2c@ef600800 { | |
251 | compatible = "ibm,iic-460ex", "ibm,iic"; | |
71f34979 | 252 | reg = <0xef600800 0x00000014>; |
8bc4a51d | 253 | interrupt-parent = <&UIC0>; |
71f34979 | 254 | interrupts = <0x3 0x4>; |
8bc4a51d SR |
255 | }; |
256 | ||
257 | ZMII0: emac-zmii@ef600d00 { | |
258 | compatible = "ibm,zmii-460ex", "ibm,zmii"; | |
71f34979 | 259 | reg = <0xef600d00 0x0000000c>; |
8bc4a51d SR |
260 | }; |
261 | ||
262 | RGMII0: emac-rgmii@ef601500 { | |
263 | compatible = "ibm,rgmii-460ex", "ibm,rgmii"; | |
71f34979 | 264 | reg = <0xef601500 0x00000008>; |
8bc4a51d SR |
265 | has-mdio; |
266 | }; | |
267 | ||
a6190a84 SR |
268 | TAH0: emac-tah@ef601350 { |
269 | compatible = "ibm,tah-460ex", "ibm,tah"; | |
71f34979 | 270 | reg = <0xef601350 0x00000030>; |
a6190a84 SR |
271 | }; |
272 | ||
273 | TAH1: emac-tah@ef601450 { | |
274 | compatible = "ibm,tah-460ex", "ibm,tah"; | |
71f34979 | 275 | reg = <0xef601450 0x00000030>; |
a6190a84 SR |
276 | }; |
277 | ||
8bc4a51d SR |
278 | EMAC0: ethernet@ef600e00 { |
279 | device_type = "network"; | |
05781ccd | 280 | compatible = "ibm,emac-460ex", "ibm,emac4sync"; |
8bc4a51d | 281 | interrupt-parent = <&EMAC0>; |
71f34979 | 282 | interrupts = <0x0 0x1>; |
8bc4a51d SR |
283 | #interrupt-cells = <1>; |
284 | #address-cells = <0>; | |
285 | #size-cells = <0>; | |
71f34979 DG |
286 | interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4 |
287 | /*Wake*/ 0x1 &UIC2 0x14 0x4>; | |
05781ccd | 288 | reg = <0xef600e00 0x000000c4>; |
8bc4a51d SR |
289 | local-mac-address = [000000000000]; /* Filled in by U-Boot */ |
290 | mal-device = <&MAL0>; | |
291 | mal-tx-channel = <0>; | |
292 | mal-rx-channel = <0>; | |
293 | cell-index = <0>; | |
71f34979 DG |
294 | max-frame-size = <9000>; |
295 | rx-fifo-size = <4096>; | |
296 | tx-fifo-size = <2048>; | |
8bc4a51d | 297 | phy-mode = "rgmii"; |
71f34979 | 298 | phy-map = <0x00000000>; |
8bc4a51d SR |
299 | rgmii-device = <&RGMII0>; |
300 | rgmii-channel = <0>; | |
a6190a84 SR |
301 | tah-device = <&TAH0>; |
302 | tah-channel = <0>; | |
8bc4a51d SR |
303 | has-inverted-stacr-oc; |
304 | has-new-stacr-staopc; | |
305 | }; | |
306 | ||
307 | EMAC1: ethernet@ef600f00 { | |
308 | device_type = "network"; | |
05781ccd | 309 | compatible = "ibm,emac-460ex", "ibm,emac4sync"; |
8bc4a51d | 310 | interrupt-parent = <&EMAC1>; |
71f34979 | 311 | interrupts = <0x0 0x1>; |
8bc4a51d SR |
312 | #interrupt-cells = <1>; |
313 | #address-cells = <0>; | |
314 | #size-cells = <0>; | |
71f34979 DG |
315 | interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4 |
316 | /*Wake*/ 0x1 &UIC2 0x15 0x4>; | |
05781ccd | 317 | reg = <0xef600f00 0x000000c4>; |
8bc4a51d SR |
318 | local-mac-address = [000000000000]; /* Filled in by U-Boot */ |
319 | mal-device = <&MAL0>; | |
320 | mal-tx-channel = <1>; | |
321 | mal-rx-channel = <8>; | |
322 | cell-index = <1>; | |
71f34979 DG |
323 | max-frame-size = <9000>; |
324 | rx-fifo-size = <4096>; | |
325 | tx-fifo-size = <2048>; | |
8bc4a51d | 326 | phy-mode = "rgmii"; |
71f34979 | 327 | phy-map = <0x00000000>; |
8bc4a51d SR |
328 | rgmii-device = <&RGMII0>; |
329 | rgmii-channel = <1>; | |
a6190a84 SR |
330 | tah-device = <&TAH1>; |
331 | tah-channel = <1>; | |
8bc4a51d SR |
332 | has-inverted-stacr-oc; |
333 | has-new-stacr-staopc; | |
a6190a84 | 334 | mdio-device = <&EMAC0>; |
8bc4a51d SR |
335 | }; |
336 | }; | |
337 | ||
338 | PCIX0: pci@c0ec00000 { | |
339 | device_type = "pci"; | |
340 | #interrupt-cells = <1>; | |
341 | #size-cells = <2>; | |
342 | #address-cells = <3>; | |
343 | compatible = "ibm,plb-pcix-460ex", "ibm,plb-pcix"; | |
344 | primary; | |
345 | large-inbound-windows; | |
346 | enable-msi-hole; | |
71f34979 DG |
347 | reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */ |
348 | 0x00000000 0x00000000 0x00000000 /* no IACK cycles */ | |
349 | 0x0000000c 0x0ed00000 0x00000004 /* Special cycles */ | |
350 | 0x0000000c 0x0ec80000 0x00000100 /* Internal registers */ | |
351 | 0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */ | |
8bc4a51d SR |
352 | |
353 | /* Outbound ranges, one memory and one IO, | |
354 | * later cannot be changed | |
355 | */ | |
71f34979 | 356 | ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000 |
84d727a1 | 357 | 0x02000000 0x00000000 0x00000000 0x0000000c 0x0ee00000 0x00000000 0x00100000 |
71f34979 | 358 | 0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>; |
8bc4a51d SR |
359 | |
360 | /* Inbound 2GB range starting at 0 */ | |
71f34979 | 361 | dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; |
8bc4a51d SR |
362 | |
363 | /* This drives busses 0 to 0x3f */ | |
71f34979 | 364 | bus-range = <0x0 0x3f>; |
8bc4a51d SR |
365 | |
366 | /* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */ | |
71f34979 DG |
367 | interrupt-map-mask = <0x0 0x0 0x0 0x0>; |
368 | interrupt-map = < 0x0 0x0 0x0 0x0 &UIC1 0x0 0x8 >; | |
8bc4a51d SR |
369 | }; |
370 | ||
371 | PCIE0: pciex@d00000000 { | |
372 | device_type = "pci"; | |
373 | #interrupt-cells = <1>; | |
374 | #size-cells = <2>; | |
375 | #address-cells = <3>; | |
376 | compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex"; | |
377 | primary; | |
71f34979 DG |
378 | port = <0x0>; /* port number */ |
379 | reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */ | |
380 | 0x0000000c 0x08010000 0x00001000>; /* Registers */ | |
381 | dcr-reg = <0x100 0x020>; | |
382 | sdr-base = <0x300>; | |
8bc4a51d SR |
383 | |
384 | /* Outbound ranges, one memory and one IO, | |
385 | * later cannot be changed | |
386 | */ | |
71f34979 | 387 | ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000 |
84d727a1 | 388 | 0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000 |
71f34979 | 389 | 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>; |
8bc4a51d SR |
390 | |
391 | /* Inbound 2GB range starting at 0 */ | |
71f34979 | 392 | dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; |
8bc4a51d SR |
393 | |
394 | /* This drives busses 40 to 0x7f */ | |
71f34979 | 395 | bus-range = <0x40 0x7f>; |
8bc4a51d SR |
396 | |
397 | /* Legacy interrupts (note the weird polarity, the bridge seems | |
398 | * to invert PCIe legacy interrupts). | |
399 | * We are de-swizzling here because the numbers are actually for | |
400 | * port of the root complex virtual P2P bridge. But I want | |
401 | * to avoid putting a node for it in the tree, so the numbers | |
402 | * below are basically de-swizzled numbers. | |
403 | * The real slot is on idsel 0, so the swizzling is 1:1 | |
404 | */ | |
71f34979 | 405 | interrupt-map-mask = <0x0 0x0 0x0 0x7>; |
8bc4a51d | 406 | interrupt-map = < |
71f34979 DG |
407 | 0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */ |
408 | 0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */ | |
409 | 0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */ | |
410 | 0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>; | |
8bc4a51d SR |
411 | }; |
412 | ||
413 | PCIE1: pciex@d20000000 { | |
414 | device_type = "pci"; | |
415 | #interrupt-cells = <1>; | |
416 | #size-cells = <2>; | |
417 | #address-cells = <3>; | |
418 | compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex"; | |
419 | primary; | |
71f34979 DG |
420 | port = <0x1>; /* port number */ |
421 | reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */ | |
422 | 0x0000000c 0x08011000 0x00001000>; /* Registers */ | |
423 | dcr-reg = <0x120 0x020>; | |
424 | sdr-base = <0x340>; | |
8bc4a51d SR |
425 | |
426 | /* Outbound ranges, one memory and one IO, | |
427 | * later cannot be changed | |
428 | */ | |
71f34979 | 429 | ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000 |
84d727a1 | 430 | 0x02000000 0x00000000 0x00000000 0x0000000f 0x00100000 0x00000000 0x00100000 |
71f34979 | 431 | 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>; |
8bc4a51d SR |
432 | |
433 | /* Inbound 2GB range starting at 0 */ | |
71f34979 | 434 | dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; |
8bc4a51d SR |
435 | |
436 | /* This drives busses 80 to 0xbf */ | |
71f34979 | 437 | bus-range = <0x80 0xbf>; |
8bc4a51d SR |
438 | |
439 | /* Legacy interrupts (note the weird polarity, the bridge seems | |
440 | * to invert PCIe legacy interrupts). | |
441 | * We are de-swizzling here because the numbers are actually for | |
442 | * port of the root complex virtual P2P bridge. But I want | |
443 | * to avoid putting a node for it in the tree, so the numbers | |
444 | * below are basically de-swizzled numbers. | |
445 | * The real slot is on idsel 0, so the swizzling is 1:1 | |
446 | */ | |
71f34979 | 447 | interrupt-map-mask = <0x0 0x0 0x0 0x7>; |
8bc4a51d | 448 | interrupt-map = < |
71f34979 DG |
449 | 0x0 0x0 0x0 0x1 &UIC3 0x10 0x4 /* swizzled int A */ |
450 | 0x0 0x0 0x0 0x2 &UIC3 0x11 0x4 /* swizzled int B */ | |
451 | 0x0 0x0 0x0 0x3 &UIC3 0x12 0x4 /* swizzled int C */ | |
452 | 0x0 0x0 0x0 0x4 &UIC3 0x13 0x4 /* swizzled int D */>; | |
8bc4a51d SR |
453 | }; |
454 | }; | |
455 | }; |