[GitHub/moto-9609/android_kernel_motorola_exynos9610.git] / arch / parisc / include / asm / io.h

#ifndef _ASM_IO_H
#define _ASM_IO_H

#include <linux/types.h>
#include <asm/pgtable.h>

#define virt_to_phys(a) ((unsigned long)__pa(a))
#define phys_to_virt(a) __va(a)
#define virt_to_bus virt_to_phys
#define bus_to_virt phys_to_virt

static inline unsigned long isa_bus_to_virt(unsigned long addr) {
	BUG();
	return 0;
}

static inline unsigned long isa_virt_to_bus(void *addr) {
	BUG();
	return 0;
}

/*
 * Memory mapped I/O
 *
 * readX()/writeX() do byteswapping and take an ioremapped address
 * __raw_readX()/__raw_writeX() don't byteswap and take an ioremapped address.
 * gsc_*() don't byteswap and operate on physical addresses;
 *   eg dev->hpa or 0xfee00000.
 */

static inline unsigned char gsc_readb(unsigned long addr)
{
	long flags;
	unsigned char ret;

	__asm__ __volatile__(
	"	rsm	2,%0\n"
	"	ldbx	0(%2),%1\n"
	"	mtsm	%0\n"
	: "=&r" (flags), "=r" (ret) : "r" (addr) );

	return ret;
}

static inline unsigned short gsc_readw(unsigned long addr)
{
	long flags;
	unsigned short ret;

	__asm__ __volatile__(
	"	rsm	2,%0\n"
	"	ldhx	0(%2),%1\n"
	"	mtsm	%0\n"
	: "=&r" (flags), "=r" (ret) : "r" (addr) );

	return ret;
}

static inline unsigned int gsc_readl(unsigned long addr)
{
	u32 ret;

	__asm__ __volatile__(
	"	ldwax	0(%1),%0\n"
	: "=r" (ret) : "r" (addr) );

	return ret;
}

static inline unsigned long long gsc_readq(unsigned long addr)
{
	unsigned long long ret;

#ifdef CONFIG_64BIT
	__asm__ __volatile__(
	"	ldda	0(%1),%0\n"
	:  "=r" (ret) : "r" (addr) );
#else
	/* two reads may have side effects.. */
	ret = ((u64) gsc_readl(addr)) << 32;
	ret |= gsc_readl(addr+4);
#endif
	return ret;
}

static inline void gsc_writeb(unsigned char val, unsigned long addr)
{
	long flags;
	__asm__ __volatile__(
	"	rsm	2,%0\n"
	"	stbs	%1,0(%2)\n"
	"	mtsm	%0\n"
	: "=&r" (flags) :  "r" (val), "r" (addr) );
}

static inline void gsc_writew(unsigned short val, unsigned long addr)
{
	long flags;
	__asm__ __volatile__(
	"	rsm	2,%0\n"
	"	sths	%1,0(%2)\n"
	"	mtsm	%0\n"
	: "=&r" (flags) :  "r" (val), "r" (addr) );
}

static inline void gsc_writel(unsigned int val, unsigned long addr)
{
	__asm__ __volatile__(
	"	stwas	%0,0(%1)\n"
	: :  "r" (val), "r" (addr) );
}

static inline void gsc_writeq(unsigned long long val, unsigned long addr)
{
#ifdef CONFIG_64BIT
	__asm__ __volatile__(
	"	stda	%0,0(%1)\n"
	: :  "r" (val), "r" (addr) );
#else
	/* two writes may have side effects.. */
	gsc_writel(val >> 32, addr);
	gsc_writel(val, addr+4);
#endif
}

/*
 * The standard PCI ioremap interfaces
 */

extern void __iomem * __ioremap(unsigned long offset, unsigned long size, unsigned long flags);

/* Most machines react poorly to I/O-space being cacheable... Instead let's
 * define ioremap() in terms of ioremap_nocache().
 */
static inline void __iomem * ioremap(unsigned long offset, unsigned long size)
{
	return __ioremap(offset, size, _PAGE_NO_CACHE);
}
#define ioremap_nocache(off, sz)	ioremap((off), (sz))
#define ioremap_wc			ioremap_nocache
#define ioremap_uc			ioremap_nocache

extern void iounmap(const volatile void __iomem *addr);

static inline unsigned char __raw_readb(const volatile void __iomem *addr)
{
	return (*(volatile unsigned char __force *) (addr));
}
static inline unsigned short __raw_readw(const volatile void __iomem *addr)
{
	return *(volatile unsigned short __force *) addr;
}
static inline unsigned int __raw_readl(const volatile void __iomem *addr)
{
	return *(volatile unsigned int __force *) addr;
}
static inline unsigned long long __raw_readq(const volatile void __iomem *addr)
{
	return *(volatile unsigned long long __force *) addr;
}

static inline void __raw_writeb(unsigned char b, volatile void __iomem *addr)
{
	*(volatile unsigned char __force *) addr = b;
}
static inline void __raw_writew(unsigned short b, volatile void __iomem *addr)
{
	*(volatile unsigned short __force *) addr = b;
}
static inline void __raw_writel(unsigned int b, volatile void __iomem *addr)
{
	*(volatile unsigned int __force *) addr = b;
}
static inline void __raw_writeq(unsigned long long b, volatile void __iomem *addr)
{
	*(volatile unsigned long long __force *) addr = b;
}

static inline unsigned char readb(const volatile void __iomem *addr)
{
	return __raw_readb(addr);
}
static inline unsigned short readw(const volatile void __iomem *addr)
{
	return le16_to_cpu(__raw_readw(addr));
}
static inline unsigned int readl(const volatile void __iomem *addr)
{
	return le32_to_cpu(__raw_readl(addr));
}
static inline unsigned long long readq(const volatile void __iomem *addr)
{
	return le64_to_cpu(__raw_readq(addr));
}

static inline void writeb(unsigned char b, volatile void __iomem *addr)
{
	__raw_writeb(b, addr);
}
static inline void writew(unsigned short w, volatile void __iomem *addr)
{
	__raw_writew(cpu_to_le16(w), addr);
}
static inline void writel(unsigned int l, volatile void __iomem *addr)
{
	__raw_writel(cpu_to_le32(l), addr);
}
static inline void writeq(unsigned long long q, volatile void __iomem *addr)
{
	__raw_writeq(cpu_to_le64(q), addr);
}

#define	readb	readb
#define	readw	readw
#define	readl	readl
#define readq	readq
#define writeb	writeb
#define writew	writew
#define writel	writel
#define writeq	writeq

#define readb_relaxed(addr)	readb(addr)
#define readw_relaxed(addr)	readw(addr)
#define readl_relaxed(addr)	readl(addr)
#define readq_relaxed(addr)	readq(addr)
#define writeb_relaxed(b, addr)	writeb(b, addr)
#define writew_relaxed(w, addr)	writew(w, addr)
#define writel_relaxed(l, addr)	writel(l, addr)
#define writeq_relaxed(q, addr)	writeq(q, addr)

#define mmiowb() do { } while (0)

void memset_io(volatile void __iomem *addr, unsigned char val, int count);
void memcpy_fromio(void *dst, const volatile void __iomem *src, int count);
void memcpy_toio(volatile void __iomem *dst, const void *src, int count);

/* Port-space IO */

#define inb_p inb
#define inw_p inw
#define inl_p inl
#define outb_p outb
#define outw_p outw
#define outl_p outl

extern unsigned char eisa_in8(unsigned short port);
extern unsigned short eisa_in16(unsigned short port);
extern unsigned int eisa_in32(unsigned short port);
extern void eisa_out8(unsigned char data, unsigned short port);
extern void eisa_out16(unsigned short data, unsigned short port);
extern void eisa_out32(unsigned int data, unsigned short port);

#if defined(CONFIG_PCI)
extern unsigned char inb(int addr);
extern unsigned short inw(int addr);
extern unsigned int inl(int addr);

extern void outb(unsigned char b, int addr);
extern void outw(unsigned short b, int addr);
extern void outl(unsigned int b, int addr);
#elif defined(CONFIG_EISA)
#define inb eisa_in8
#define inw eisa_in16
#define inl eisa_in32
#define outb eisa_out8
#define outw eisa_out16
#define outl eisa_out32
#else
static inline char inb(unsigned long addr)
{
	BUG();
	return -1;
}

static inline short inw(unsigned long addr)
{
	BUG();
	return -1;
}

static inline int inl(unsigned long addr)
{
	BUG();
	return -1;
}

#define outb(x, y)	BUG()
#define outw(x, y)	BUG()
#define outl(x, y)	BUG()
#endif

/*
 * String versions of in/out ops:
 */
extern void insb (unsigned long port, void *dst, unsigned long count);
extern void insw (unsigned long port, void *dst, unsigned long count);
extern void insl (unsigned long port, void *dst, unsigned long count);
extern void outsb (unsigned long port, const void *src, unsigned long count);
extern void outsw (unsigned long port, const void *src, unsigned long count);
extern void outsl (unsigned long port, const void *src, unsigned long count);


/* IO Port space is :      BBiiii   where BB is HBA number. */
#define IO_SPACE_LIMIT 0x00ffffff

/* PA machines have an MM I/O space from 0xf0000000-0xffffffff in 32
 * bit mode and from 0xfffffffff0000000-0xfffffffffffffff in 64 bit
 * mode (essentially just sign extending.  This macro takes in a 32
 * bit I/O address (still with the leading f) and outputs the correct
 * value for either 32 or 64 bit mode */
#define F_EXTEND(x) ((unsigned long)((x) | (0xffffffff00000000ULL)))

#include <asm-generic/iomap.h>

/*
 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
 * access
 */
#define xlate_dev_mem_ptr(p)	__va(p)

/*
 * Convert a virtual cached pointer to an uncached pointer
 */
#define xlate_dev_kmem_ptr(p)	p

#endif
Commit	Line	Data
1da177e4 LT	1	#ifndef _ASM_IO_H
	2	#define _ASM_IO_H
	3
1da177e4 LT	4	#include <linux/types.h>
	5	#include <asm/pgtable.h>
	6
1da177e4 LT	7	#define virt_to_phys(a) ((unsigned long)__pa(a))
	8	#define phys_to_virt(a) __va(a)
	9	#define virt_to_bus virt_to_phys
	10	#define bus_to_virt phys_to_virt
	11
fabb8ff4 KM	12	static inline unsigned long isa_bus_to_virt(unsigned long addr) {
	13	BUG();
	14	return 0;
	15	}
	16
	17	static inline unsigned long isa_virt_to_bus(void *addr) {
	18	BUG();
	19	return 0;
	20	}
	21
1da177e4 LT	22	/*
	23	* Memory mapped I/O
	24	*
	25	* readX()/writeX() do byteswapping and take an ioremapped address
	26	* __raw_readX()/__raw_writeX() don't byteswap and take an ioremapped address.
	27	* gsc_*() don't byteswap and operate on physical addresses;
	28	* eg dev->hpa or 0xfee00000.
	29	*/
	30
1da177e4 LT	31	static inline unsigned char gsc_readb(unsigned long addr)
	32	{
	33	long flags;
	34	unsigned char ret;
	35
1da177e4 LT	36	__asm__ __volatile__(
	37	" rsm 2,%0\n"
	38	" ldbx 0(%2),%1\n"
	39	" mtsm %0\n"
	40	: "=&r" (flags), "=r" (ret) : "r" (addr) );
	41
	42	return ret;
	43	}
	44
	45	static inline unsigned short gsc_readw(unsigned long addr)
	46	{
	47	long flags;
	48	unsigned short ret;
	49
1da177e4 LT	50	__asm__ __volatile__(
	51	" rsm 2,%0\n"
	52	" ldhx 0(%2),%1\n"
	53	" mtsm %0\n"
	54	: "=&r" (flags), "=r" (ret) : "r" (addr) );
	55
	56	return ret;
	57	}
	58
	59	static inline unsigned int gsc_readl(unsigned long addr)
	60	{
	61	u32 ret;
	62
1da177e4 LT	63	__asm__ __volatile__(
	64	" ldwax 0(%1),%0\n"
	65	: "=r" (ret) : "r" (addr) );
	66
	67	return ret;
	68	}
	69
	70	static inline unsigned long long gsc_readq(unsigned long addr)
	71	{
	72	unsigned long long ret;
1da177e4	73
513e7ecd	74	#ifdef CONFIG_64BIT
1da177e4 LT	75	__asm__ __volatile__(
	76	" ldda 0(%1),%0\n"
	77	: "=r" (ret) : "r" (addr) );
	78	#else
	79	/* two reads may have side effects.. */
	80	ret = ((u64) gsc_readl(addr)) << 32;
	81	ret \|= gsc_readl(addr+4);
	82	#endif
	83	return ret;
	84	}
	85
	86	static inline void gsc_writeb(unsigned char val, unsigned long addr)
	87	{
	88	long flags;
1da177e4 LT	89	__asm__ __volatile__(
	90	" rsm 2,%0\n"
	91	" stbs %1,0(%2)\n"
	92	" mtsm %0\n"
	93	: "=&r" (flags) : "r" (val), "r" (addr) );
	94	}
	95
	96	static inline void gsc_writew(unsigned short val, unsigned long addr)
	97	{
	98	long flags;
1da177e4 LT	99	__asm__ __volatile__(
	100	" rsm 2,%0\n"
	101	" sths %1,0(%2)\n"
	102	" mtsm %0\n"
	103	: "=&r" (flags) : "r" (val), "r" (addr) );
	104	}
	105
	106	static inline void gsc_writel(unsigned int val, unsigned long addr)
	107	{
1da177e4 LT	108	__asm__ __volatile__(
	109	" stwas %0,0(%1)\n"
	110	: : "r" (val), "r" (addr) );
	111	}
	112
	113	static inline void gsc_writeq(unsigned long long val, unsigned long addr)
	114	{
513e7ecd	115	#ifdef CONFIG_64BIT
1da177e4 LT	116	__asm__ __volatile__(
	117	" stda %0,0(%1)\n"
	118	: : "r" (val), "r" (addr) );
	119	#else
	120	/* two writes may have side effects.. */
	121	gsc_writel(val >> 32, addr);
	122	gsc_writel(val, addr+4);
	123	#endif
	124	}
	125
	126	/*
	127	* The standard PCI ioremap interfaces
	128	*/
	129
	130	extern void __iomem * __ioremap(unsigned long offset, unsigned long size, unsigned long flags);
	131
1b52d7c2 KM	132	/* Most machines react poorly to I/O-space being cacheable... Instead let's
1b52d7c2 KM	133	* define ioremap() in terms of ioremap_nocache().
1da177e4	134	*/
f13cec84	135	static inline void __iomem * ioremap(unsigned long offset, unsigned long size)
1da177e4	136	{
1b52d7c2	137	return __ioremap(offset, size, _PAGE_NO_CACHE);
1da177e4	138	}
1b52d7c2	139	#define ioremap_nocache(off, sz) ioremap((off), (sz))
38d9029a GR	140	#define ioremap_wc ioremap_nocache
38d9029a GR	141	#define ioremap_uc ioremap_nocache
1da177e4	142
01232e93	143	extern void iounmap(const volatile void __iomem *addr);
1da177e4	144
1da177e4 LT	145	static inline unsigned char __raw_readb(const volatile void __iomem *addr)
	146	{
	147	return ((volatile unsigned char __force ) (addr));
	148	}
	149	static inline unsigned short __raw_readw(const volatile void __iomem *addr)
	150	{
	151	return (volatile unsigned short __force ) addr;
	152	}
	153	static inline unsigned int __raw_readl(const volatile void __iomem *addr)
	154	{
	155	return (volatile unsigned int __force ) addr;
	156	}
	157	static inline unsigned long long __raw_readq(const volatile void __iomem *addr)
	158	{
	159	return (volatile unsigned long long __force ) addr;
	160	}
	161
	162	static inline void __raw_writeb(unsigned char b, volatile void __iomem *addr)
	163	{
	164	(volatile unsigned char __force ) addr = b;
	165	}
	166	static inline void __raw_writew(unsigned short b, volatile void __iomem *addr)
	167	{
	168	(volatile unsigned short __force ) addr = b;
	169	}
	170	static inline void __raw_writel(unsigned int b, volatile void __iomem *addr)
	171	{
	172	(volatile unsigned int __force ) addr = b;
	173	}
	174	static inline void __raw_writeq(unsigned long long b, volatile void __iomem *addr)
	175	{
	176	(volatile unsigned long long __force ) addr = b;
	177	}
1da177e4	178
9dfe914d KM	179	static inline unsigned char readb(const volatile void __iomem *addr)
	180	{
	181	return __raw_readb(addr);
	182	}
	183	static inline unsigned short readw(const volatile void __iomem *addr)
	184	{
	185	return le16_to_cpu(__raw_readw(addr));
	186	}
	187	static inline unsigned int readl(const volatile void __iomem *addr)
	188	{
	189	return le32_to_cpu(__raw_readl(addr));
	190	}
	191	static inline unsigned long long readq(const volatile void __iomem *addr)
	192	{
	193	return le64_to_cpu(__raw_readq(addr));
	194	}
	195
	196	static inline void writeb(unsigned char b, volatile void __iomem *addr)
	197	{
	198	__raw_writeb(b, addr);
	199	}
	200	static inline void writew(unsigned short w, volatile void __iomem *addr)
	201	{
	202	__raw_writew(cpu_to_le16(w), addr);
	203	}
	204	static inline void writel(unsigned int l, volatile void __iomem *addr)
	205	{
	206	__raw_writel(cpu_to_le32(l), addr);
	207	}
	208	static inline void writeq(unsigned long long q, volatile void __iomem *addr)
	209	{
	210	__raw_writeq(cpu_to_le64(q), addr);
	211	}
1da177e4	212
0cb385e3 KM	213	#define readb readb
	214	#define readw readw
	215	#define readl readl
	216	#define readq readq
	217	#define writeb writeb
	218	#define writew writew
	219	#define writel writel
	220	#define writeq writeq
	221
2f083481 WD	222	#define readb_relaxed(addr) readb(addr)
	223	#define readw_relaxed(addr) readw(addr)
	224	#define readl_relaxed(addr) readl(addr)
	225	#define readq_relaxed(addr) readq(addr)
	226	#define writeb_relaxed(b, addr) writeb(b, addr)
	227	#define writew_relaxed(w, addr) writew(w, addr)
	228	#define writel_relaxed(l, addr) writel(l, addr)
	229	#define writeq_relaxed(q, addr) writeq(q, addr)
1da177e4 LT	230
	231	#define mmiowb() do { } while (0)
	232
	233	void memset_io(volatile void __iomem *addr, unsigned char val, int count);
	234	void memcpy_fromio(void dst, const volatile void __iomem src, int count);
	235	void memcpy_toio(volatile void __iomem dst, const void src, int count);
	236
1da177e4 LT	237	/* Port-space IO */
	238
	239	#define inb_p inb
	240	#define inw_p inw
	241	#define inl_p inl
	242	#define outb_p outb
	243	#define outw_p outw
	244	#define outl_p outl
	245
	246	extern unsigned char eisa_in8(unsigned short port);
	247	extern unsigned short eisa_in16(unsigned short port);
	248	extern unsigned int eisa_in32(unsigned short port);
	249	extern void eisa_out8(unsigned char data, unsigned short port);
	250	extern void eisa_out16(unsigned short data, unsigned short port);
	251	extern void eisa_out32(unsigned int data, unsigned short port);
	252
	253	#if defined(CONFIG_PCI)
	254	extern unsigned char inb(int addr);
	255	extern unsigned short inw(int addr);
	256	extern unsigned int inl(int addr);
	257
	258	extern void outb(unsigned char b, int addr);
	259	extern void outw(unsigned short b, int addr);
	260	extern void outl(unsigned int b, int addr);
	261	#elif defined(CONFIG_EISA)
	262	#define inb eisa_in8
	263	#define inw eisa_in16
	264	#define inl eisa_in32
	265	#define outb eisa_out8
	266	#define outw eisa_out16
	267	#define outl eisa_out32
	268	#else
	269	static inline char inb(unsigned long addr)
	270	{
	271	BUG();
	272	return -1;
	273	}
	274
	275	static inline short inw(unsigned long addr)
	276	{
	277	BUG();
	278	return -1;
	279	}
	280
	281	static inline int inl(unsigned long addr)
	282	{
	283	BUG();
	284	return -1;
	285	}
	286
	287	#define outb(x, y) BUG()
	288	#define outw(x, y) BUG()
	289	#define outl(x, y) BUG()
	290	#endif
	291
	292	/*
	293	* String versions of in/out ops:
	294	*/
	295	extern void insb (unsigned long port, void *dst, unsigned long count);
	296	extern void insw (unsigned long port, void *dst, unsigned long count);
	297	extern void insl (unsigned long port, void *dst, unsigned long count);
	298	extern void outsb (unsigned long port, const void *src, unsigned long count);
	299	extern void outsw (unsigned long port, const void *src, unsigned long count);
	300	extern void outsl (unsigned long port, const void *src, unsigned long count);
301
302
303	/* IO Port space is : BBiiii where BB is HBA number. */
304	#define IO_SPACE_LIMIT 0x00ffffff
305
1da177e4 LT	306	/* PA machines have an MM I/O space from 0xf0000000-0xffffffff in 32
	307	* bit mode and from 0xfffffffff0000000-0xfffffffffffffff in 64 bit
	308	* mode (essentially just sign extending. This macro takes in a 32
	309	* bit I/O address (still with the leading f) and outputs the correct
	310	* value for either 32 or 64 bit mode */
	311	#define F_EXTEND(x) ((unsigned long)((x) \| (0xffffffff00000000ULL)))
	312
	313	#include <asm-generic/iomap.h>
	314
	315	/*
	316	* Convert a physical pointer to a virtual kernel pointer for /dev/mem
	317	* access
	318	*/
	319	#define xlate_dev_mem_ptr(p) __va(p)
	320
	321	/*
	322	* Convert a virtual cached pointer to an uncached pointer
	323	*/
	324	#define xlate_dev_kmem_ptr(p) p
	325
	326	#endif