projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
| Commit | Line | Data |
|---|---|---|
| 7f386ac3 DH |
1 | /* MN10300 CPU cache invalidation routines, using direct tag flushing |
| 2 | * | |
| 3 | * Copyright (C) 2011 Red Hat, Inc. All Rights Reserved. | |
| 4 | * Written by David Howells (dhowells@redhat.com) | |
| 5 | * | |
| 6 | * This program is free software; you can redistribute it and/or | |
| 7 | * modify it under the terms of the GNU General Public Licence | |
| 8 | * as published by the Free Software Foundation; either version | |
| 9 | * 2 of the Licence, or (at your option) any later version. | |
| 10 | */ | |
| 11 | #include <linux/sys.h> | |
| 12 | #include <linux/linkage.h> | |
| 13 | #include <asm/smp.h> | |
| 14 | #include <asm/page.h> | |
| 15 | #include <asm/cache.h> | |
| 16 | #include <asm/irqflags.h> | |
| 17 | #include <asm/cacheflush.h> | |
| 18 | #include "cache.inc" | |
| 19 | ||
| 20 | .am33_2 | |
| 21 | ||
| 22 | ############################################################################### | |
| 23 | # | |
| 24 | # void debugger_local_cache_flushinv(void) | |
| 25 | # | |
| 26 | # Flush the entire data cache back to RAM and invalidate the icache | |
| 27 | # | |
| 28 | ############################################################################### | |
| 29 | ALIGN | |
| 30 | .globl debugger_local_cache_flushinv | |
| 31 | .type debugger_local_cache_flushinv,@function | |
| 32 | debugger_local_cache_flushinv: | |
| 33 | # | |
| 34 | # firstly flush the dcache | |
| 35 | # | |
| 36 | movhu (CHCTR),d0 | |
| 37 | btst CHCTR_DCEN|CHCTR_ICEN,d0 | |
| 38 | beq debugger_local_cache_flushinv_end | |
| 39 | ||
| 40 | btst CHCTR_DCEN,d0 | |
| 41 | beq debugger_local_cache_flushinv_no_dcache | |
| 42 | ||
| 43 | # read the addresses tagged in the cache's tag RAM and attempt to flush | |
| 44 | # those addresses specifically | |
| 45 | # - we rely on the hardware to filter out invalid tag entry addresses | |
| 46 | mov DCACHE_TAG(0,0),a0 # dcache tag RAM access address | |
| 47 | mov DCACHE_PURGE(0,0),a1 # dcache purge request address | |
| 48 | mov L1_CACHE_NWAYS*L1_CACHE_NENTRIES,e0 # total number of entries | |
| 49 | ||
| 50 | mn10300_local_dcache_flush_loop: | |
| 51 | mov (a0),d0 | |
| 52 | and L1_CACHE_TAG_MASK,d0 | |
| 53 | or L1_CACHE_TAG_VALID,d0 # retain valid entries in the | |
| 54 | # cache | |
| 55 | mov d0,(a1) # conditional purge | |
| 56 | ||
| 57 | add L1_CACHE_BYTES,a0 | |
| 58 | add L1_CACHE_BYTES,a1 | |
| 59 | add -1,e0 | |
| 60 | bne mn10300_local_dcache_flush_loop | |
| 61 | ||
| 62 | debugger_local_cache_flushinv_no_dcache: | |
| 63 | # | |
| 64 | # secondly, invalidate the icache if it is enabled | |
| 65 | # | |
| 66 | mov CHCTR,a0 | |
| 67 | movhu (a0),d0 | |
| 68 | btst CHCTR_ICEN,d0 | |
| 69 | beq debugger_local_cache_flushinv_end | |
| 70 | ||
| 71 | invalidate_icache 1 | |
| 72 | ||
| 73 | debugger_local_cache_flushinv_end: | |
| 74 | ret [],0 | |
| 75 | .size debugger_local_cache_flushinv,.-debugger_local_cache_flushinv | |
| 76 | ||
| 77 | ############################################################################### | |
| 78 | # | |
| 79 | # void debugger_local_cache_flushinv_one(u8 *addr) | |
| 80 | # | |
| 81 | # Invalidate one particular cacheline if it's in the icache | |
| 82 | # | |
| 83 | ############################################################################### | |
| 84 | ALIGN | |
| 85 | .globl debugger_local_cache_flushinv_one | |
| 86 | .type debugger_local_cache_flushinv_one,@function | |
| 87 | debugger_local_cache_flushinv_one: | |
| 88 | movhu (CHCTR),d1 | |
| 89 | btst CHCTR_DCEN|CHCTR_ICEN,d1 | |
| 90 | beq debugger_local_cache_flushinv_one_end | |
| 91 | btst CHCTR_DCEN,d1 | |
| 92 | beq debugger_local_cache_flushinv_one_icache | |
| 93 | ||
| 94 | # round cacheline addr down | |
| 95 | and L1_CACHE_TAG_MASK,d0 | |
| 96 | mov d0,a1 | |
| 97 | ||
| 98 | # determine the dcache purge control reg address | |
| 99 | mov DCACHE_PURGE(0,0),a0 | |
| 100 | and L1_CACHE_TAG_ENTRY,d0 | |
| 101 | add d0,a0 | |
| 102 | ||
| 103 | # retain valid entries in the cache | |
| 104 | or L1_CACHE_TAG_VALID,a1 | |
| 105 | ||
| 106 | # conditionally purge this line in all ways | |
| 107 | mov a1,(L1_CACHE_WAYDISP*0,a0) | |
| 108 | ||
| 109 | # now go and do the icache | |
| 110 | bra debugger_local_cache_flushinv_one_icache | |
| 111 | ||
| 112 | debugger_local_cache_flushinv_one_end: | |
| 113 | ret [],0 | |
| 114 | .size debugger_local_cache_flushinv_one,.-debugger_local_cache_flushinv_one |