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b920de1b DH |
1 | /* MN10300 Arch-specific initialisation |
2 | * | |
3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | |
4 | * Written by David Howells (dhowells@redhat.com) | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public Licence | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the Licence, or (at your option) any later version. | |
10 | */ | |
11 | #include <linux/errno.h> | |
12 | #include <linux/sched.h> | |
13 | #include <linux/kernel.h> | |
14 | #include <linux/mm.h> | |
15 | #include <linux/stddef.h> | |
16 | #include <linux/unistd.h> | |
17 | #include <linux/ptrace.h> | |
18 | #include <linux/slab.h> | |
19 | #include <linux/user.h> | |
b920de1b DH |
20 | #include <linux/tty.h> |
21 | #include <linux/ioport.h> | |
22 | #include <linux/delay.h> | |
23 | #include <linux/init.h> | |
24 | #include <linux/bootmem.h> | |
25 | #include <linux/seq_file.h> | |
26 | #include <asm/processor.h> | |
27 | #include <linux/console.h> | |
28 | #include <asm/uaccess.h> | |
29 | #include <asm/system.h> | |
30 | #include <asm/setup.h> | |
31 | #include <asm/io.h> | |
32 | #include <asm/smp.h> | |
33 | #include <asm/proc/proc.h> | |
34 | #include <asm/busctl-regs.h> | |
35 | #include <asm/fpu.h> | |
36 | #include <asm/sections.h> | |
37 | ||
38 | struct mn10300_cpuinfo boot_cpu_data; | |
39 | ||
40 | /* For PCI or other memory-mapped resources */ | |
41 | unsigned long pci_mem_start = 0x18000000; | |
42 | ||
43 | char redboot_command_line[COMMAND_LINE_SIZE] = | |
44 | "console=ttyS0,115200 root=/dev/mtdblock3 rw"; | |
45 | ||
46 | char __initdata redboot_platform_name[COMMAND_LINE_SIZE]; | |
47 | ||
48 | static struct resource code_resource = { | |
49 | .start = 0x100000, | |
50 | .end = 0, | |
51 | .name = "Kernel code", | |
52 | }; | |
53 | ||
54 | static struct resource data_resource = { | |
55 | .start = 0, | |
56 | .end = 0, | |
57 | .name = "Kernel data", | |
58 | }; | |
59 | ||
60 | static unsigned long __initdata phys_memory_base; | |
61 | static unsigned long __initdata phys_memory_end; | |
62 | static unsigned long __initdata memory_end; | |
63 | unsigned long memory_size; | |
64 | ||
65 | struct thread_info *__current_ti = &init_thread_union.thread_info; | |
66 | struct task_struct *__current = &init_task; | |
67 | ||
68 | #define mn10300_known_cpus 3 | |
69 | static const char *const mn10300_cputypes[] = { | |
70 | "am33v1", | |
71 | "am33v2", | |
72 | "am34v1", | |
73 | "unknown" | |
74 | }; | |
75 | ||
76 | /* | |
77 | * | |
78 | */ | |
79 | static void __init parse_mem_cmdline(char **cmdline_p) | |
80 | { | |
81 | char *from, *to, c; | |
82 | ||
83 | /* save unparsed command line copy for /proc/cmdline */ | |
84 | strcpy(boot_command_line, redboot_command_line); | |
85 | ||
86 | /* see if there's an explicit memory size option */ | |
87 | from = redboot_command_line; | |
88 | to = redboot_command_line; | |
89 | c = ' '; | |
90 | ||
91 | for (;;) { | |
92 | if (c == ' ' && !memcmp(from, "mem=", 4)) { | |
93 | if (to != redboot_command_line) | |
94 | to--; | |
95 | memory_size = memparse(from + 4, &from); | |
96 | } | |
97 | ||
98 | c = *(from++); | |
99 | if (!c) | |
100 | break; | |
101 | ||
102 | *(to++) = c; | |
103 | } | |
104 | ||
105 | *to = '\0'; | |
106 | *cmdline_p = redboot_command_line; | |
107 | ||
108 | if (memory_size == 0) | |
109 | panic("Memory size not known\n"); | |
110 | ||
111 | memory_end = (unsigned long) CONFIG_KERNEL_RAM_BASE_ADDRESS + | |
112 | memory_size; | |
113 | if (memory_end > phys_memory_end) | |
114 | memory_end = phys_memory_end; | |
115 | } | |
116 | ||
117 | /* | |
118 | * architecture specific setup | |
119 | */ | |
120 | void __init setup_arch(char **cmdline_p) | |
121 | { | |
122 | unsigned long bootmap_size; | |
123 | unsigned long kstart_pfn, start_pfn, free_pfn, end_pfn; | |
124 | ||
125 | cpu_init(); | |
126 | unit_setup(); | |
127 | parse_mem_cmdline(cmdline_p); | |
128 | ||
129 | init_mm.start_code = (unsigned long)&_text; | |
130 | init_mm.end_code = (unsigned long) &_etext; | |
131 | init_mm.end_data = (unsigned long) &_edata; | |
132 | init_mm.brk = (unsigned long) &_end; | |
133 | ||
134 | code_resource.start = virt_to_bus(&_text); | |
135 | code_resource.end = virt_to_bus(&_etext)-1; | |
136 | data_resource.start = virt_to_bus(&_etext); | |
137 | data_resource.end = virt_to_bus(&_edata)-1; | |
138 | ||
139 | #define PFN_UP(x) (((x) + PAGE_SIZE-1) >> PAGE_SHIFT) | |
140 | #define PFN_DOWN(x) ((x) >> PAGE_SHIFT) | |
141 | #define PFN_PHYS(x) ((x) << PAGE_SHIFT) | |
142 | ||
143 | start_pfn = (CONFIG_KERNEL_RAM_BASE_ADDRESS >> PAGE_SHIFT); | |
144 | kstart_pfn = PFN_UP(__pa(&_text)); | |
145 | free_pfn = PFN_UP(__pa(&_end)); | |
146 | end_pfn = PFN_DOWN(__pa(memory_end)); | |
147 | ||
148 | bootmap_size = init_bootmem_node(&contig_page_data, | |
149 | free_pfn, | |
150 | start_pfn, | |
151 | end_pfn); | |
152 | ||
153 | if (kstart_pfn > start_pfn) | |
154 | free_bootmem(PFN_PHYS(start_pfn), | |
155 | PFN_PHYS(kstart_pfn - start_pfn)); | |
156 | ||
157 | free_bootmem(PFN_PHYS(free_pfn), | |
158 | PFN_PHYS(end_pfn - free_pfn)); | |
159 | ||
160 | /* If interrupt vector table is in main ram, then we need to | |
161 | reserve the page it is occupying. */ | |
162 | if (CONFIG_INTERRUPT_VECTOR_BASE >= CONFIG_KERNEL_RAM_BASE_ADDRESS && | |
163 | CONFIG_INTERRUPT_VECTOR_BASE < memory_end) | |
164 | reserve_bootmem(CONFIG_INTERRUPT_VECTOR_BASE, 1, | |
165 | BOOTMEM_DEFAULT); | |
166 | ||
167 | reserve_bootmem(PAGE_ALIGN(PFN_PHYS(free_pfn)), bootmap_size, | |
168 | BOOTMEM_DEFAULT); | |
169 | ||
170 | #ifdef CONFIG_VT | |
171 | #if defined(CONFIG_VGA_CONSOLE) | |
172 | conswitchp = &vga_con; | |
173 | #elif defined(CONFIG_DUMMY_CONSOLE) | |
174 | conswitchp = &dummy_con; | |
175 | #endif | |
176 | #endif | |
177 | ||
178 | paging_init(); | |
179 | } | |
180 | ||
181 | /* | |
182 | * perform CPU initialisation | |
183 | */ | |
184 | void __init cpu_init(void) | |
185 | { | |
186 | unsigned long cpurev = CPUREV, type; | |
187 | unsigned long base, size; | |
188 | ||
189 | type = (CPUREV & CPUREV_TYPE) >> CPUREV_TYPE_S; | |
190 | if (type > mn10300_known_cpus) | |
191 | type = mn10300_known_cpus; | |
192 | ||
193 | printk(KERN_INFO "Matsushita %s, rev %ld\n", | |
194 | mn10300_cputypes[type], | |
195 | (cpurev & CPUREV_REVISION) >> CPUREV_REVISION_S); | |
196 | ||
197 | /* determine the memory size and base from the memory controller regs */ | |
198 | memory_size = 0; | |
199 | ||
200 | base = SDBASE(0); | |
201 | if (base & SDBASE_CE) { | |
202 | size = (base & SDBASE_CBAM) << SDBASE_CBAM_SHIFT; | |
203 | size = ~size + 1; | |
204 | base &= SDBASE_CBA; | |
205 | ||
206 | printk(KERN_INFO "SDRAM[0]: %luMb @%08lx\n", size >> 20, base); | |
207 | memory_size += size; | |
208 | phys_memory_base = base; | |
209 | } | |
210 | ||
211 | base = SDBASE(1); | |
212 | if (base & SDBASE_CE) { | |
213 | size = (base & SDBASE_CBAM) << SDBASE_CBAM_SHIFT; | |
214 | size = ~size + 1; | |
215 | base &= SDBASE_CBA; | |
216 | ||
217 | printk(KERN_INFO "SDRAM[1]: %luMb @%08lx\n", size >> 20, base); | |
218 | memory_size += size; | |
219 | if (phys_memory_base == 0) | |
220 | phys_memory_base = base; | |
221 | } | |
222 | ||
223 | phys_memory_end = phys_memory_base + memory_size; | |
224 | ||
225 | #ifdef CONFIG_FPU | |
226 | fpu_init_state(); | |
227 | #endif | |
228 | } | |
229 | ||
230 | /* | |
231 | * Get CPU information for use by the procfs. | |
232 | */ | |
233 | static int show_cpuinfo(struct seq_file *m, void *v) | |
234 | { | |
235 | unsigned long cpurev = CPUREV, type, icachesz, dcachesz; | |
236 | ||
237 | type = (CPUREV & CPUREV_TYPE) >> CPUREV_TYPE_S; | |
238 | if (type > mn10300_known_cpus) | |
239 | type = mn10300_known_cpus; | |
240 | ||
241 | icachesz = | |
242 | ((cpurev & CPUREV_ICWAY ) >> CPUREV_ICWAY_S) * | |
243 | ((cpurev & CPUREV_ICSIZE) >> CPUREV_ICSIZE_S) * | |
244 | 1024; | |
245 | ||
246 | dcachesz = | |
247 | ((cpurev & CPUREV_DCWAY ) >> CPUREV_DCWAY_S) * | |
248 | ((cpurev & CPUREV_DCSIZE) >> CPUREV_DCSIZE_S) * | |
249 | 1024; | |
250 | ||
251 | seq_printf(m, | |
252 | "processor : 0\n" | |
253 | "vendor_id : Matsushita\n" | |
254 | "cpu core : %s\n" | |
255 | "cpu rev : %lu\n" | |
256 | "model name : " PROCESSOR_MODEL_NAME "\n" | |
257 | "icache size: %lu\n" | |
258 | "dcache size: %lu\n", | |
259 | mn10300_cputypes[type], | |
260 | (cpurev & CPUREV_REVISION) >> CPUREV_REVISION_S, | |
261 | icachesz, | |
262 | dcachesz | |
263 | ); | |
264 | ||
265 | seq_printf(m, | |
266 | "ioclk speed: %lu.%02luMHz\n" | |
267 | "bogomips : %lu.%02lu\n\n", | |
268 | MN10300_IOCLK / 1000000, | |
269 | (MN10300_IOCLK / 10000) % 100, | |
270 | loops_per_jiffy / (500000 / HZ), | |
271 | (loops_per_jiffy / (5000 / HZ)) % 100 | |
272 | ); | |
273 | ||
274 | return 0; | |
275 | } | |
276 | ||
277 | static void *c_start(struct seq_file *m, loff_t *pos) | |
278 | { | |
279 | return *pos < NR_CPUS ? cpu_data + *pos : NULL; | |
280 | } | |
281 | ||
282 | static void *c_next(struct seq_file *m, void *v, loff_t *pos) | |
283 | { | |
284 | ++*pos; | |
285 | return c_start(m, pos); | |
286 | } | |
287 | ||
288 | static void c_stop(struct seq_file *m, void *v) | |
289 | { | |
290 | } | |
291 | ||
292 | struct seq_operations cpuinfo_op = { | |
293 | .start = c_start, | |
294 | .next = c_next, | |
295 | .stop = c_stop, | |
296 | .show = show_cpuinfo, | |
297 | }; |