[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / mips / sgi-ip32 / ip32-irq.c

/*
 * Code to handle IP32 IRQs
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2000 Harald Koerfgen
 * Copyright (C) 2001 Keith M Wesolowski
 */
#include <linux/init.h>
#include <linux/kernel_stat.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/bitops.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/random.h>
#include <linux/sched.h>

#include <asm/irq_cpu.h>
#include <asm/mipsregs.h>
#include <asm/signal.h>
#include <asm/time.h>
#include <asm/ip32/crime.h>
#include <asm/ip32/mace.h>
#include <asm/ip32/ip32_ints.h>

/* issue a PIO read to make sure no PIO writes are pending */
static void inline flush_crime_bus(void)
{
	crime->control;
}

static void inline flush_mace_bus(void)
{
	mace->perif.ctrl.misc;
}

/*
 * O2 irq map
 *
 * IP0 -> software (ignored)
 * IP1 -> software (ignored)
 * IP2 -> (irq0) C crime 1.1 all interrupts; crime 1.5 ???
 * IP3 -> (irq1) X unknown
 * IP4 -> (irq2) X unknown
 * IP5 -> (irq3) X unknown
 * IP6 -> (irq4) X unknown
 * IP7 -> (irq5) 7 CPU count/compare timer (system timer)
 *
 * crime: (C)
 *
 * CRIME_INT_STAT 31:0:
 *
 * 0  ->  8  Video in 1
 * 1  ->  9 Video in 2
 * 2  -> 10  Video out
 * 3  -> 11  Mace ethernet
 * 4  -> S  SuperIO sub-interrupt
 * 5  -> M  Miscellaneous sub-interrupt
 * 6  -> A  Audio sub-interrupt
 * 7  -> 15  PCI bridge errors
 * 8  -> 16  PCI SCSI aic7xxx 0
 * 9  -> 17 PCI SCSI aic7xxx 1
 * 10 -> 18 PCI slot 0
 * 11 -> 19 unused (PCI slot 1)
 * 12 -> 20 unused (PCI slot 2)
 * 13 -> 21 unused (PCI shared 0)
 * 14 -> 22 unused (PCI shared 1)
 * 15 -> 23 unused (PCI shared 2)
 * 16 -> 24 GBE0 (E)
 * 17 -> 25 GBE1 (E)
 * 18 -> 26 GBE2 (E)
 * 19 -> 27 GBE3 (E)
 * 20 -> 28 CPU errors
 * 21 -> 29 Memory errors
 * 22 -> 30 RE empty edge (E)
 * 23 -> 31 RE full edge (E)
 * 24 -> 32 RE idle edge (E)
 * 25 -> 33 RE empty level
 * 26 -> 34 RE full level
 * 27 -> 35 RE idle level
 * 28 -> 36 unused (software 0) (E)
 * 29 -> 37 unused (software 1) (E)
 * 30 -> 38 unused (software 2) - crime 1.5 CPU SysCorError (E)
 * 31 -> 39 VICE
 *
 * S, M, A: Use the MACE ISA interrupt register
 * MACE_ISA_INT_STAT 31:0
 *
 * 0-7 -> 40-47 Audio
 * 8 -> 48 RTC
 * 9 -> 49 Keyboard
 * 10 -> X Keyboard polled
 * 11 -> 51 Mouse
 * 12 -> X Mouse polled
 * 13-15 -> 53-55 Count/compare timers
 * 16-19 -> 56-59 Parallel (16 E)
 * 20-25 -> 60-62 Serial 1 (22 E)
 * 26-31 -> 66-71 Serial 2 (28 E)
 *
 * Note that this means IRQs 12-14, 50, and 52 do not exist.  This is a
 * different IRQ map than IRIX uses, but that's OK as Linux irq handling
 * is quite different anyway.
 */

/* Some initial interrupts to set up */
extern irqreturn_t crime_memerr_intr(int irq, void *dev_id);
extern irqreturn_t crime_cpuerr_intr(int irq, void *dev_id);

static struct irqaction memerr_irq = {
	.handler = crime_memerr_intr,
	.name = "CRIME memory error",
};

static struct irqaction cpuerr_irq = {
	.handler = crime_cpuerr_intr,
	.name = "CRIME CPU error",
};

/*
 * This is for pure CRIME interrupts - ie not MACE.  The advantage?
 * We get to split the register in half and do faster lookups.
 */

static uint64_t crime_mask;

static inline void crime_enable_irq(struct irq_data *d)
{
	unsigned int bit = d->irq - CRIME_IRQ_BASE;

	crime_mask |= 1 << bit;
	crime->imask = crime_mask;
}

static inline void crime_disable_irq(struct irq_data *d)
{
	unsigned int bit = d->irq - CRIME_IRQ_BASE;

	crime_mask &= ~(1 << bit);
	crime->imask = crime_mask;
	flush_crime_bus();
}

static struct irq_chip crime_level_interrupt = {
	.name		= "IP32 CRIME",
	.irq_mask	= crime_disable_irq,
	.irq_unmask	= crime_enable_irq,
};

static void crime_edge_mask_and_ack_irq(struct irq_data *d)
{
	unsigned int bit = d->irq - CRIME_IRQ_BASE;
	uint64_t crime_int;

	/* Edge triggered interrupts must be cleared. */
	crime_int = crime->hard_int;
	crime_int &= ~(1 << bit);
	crime->hard_int = crime_int;

	crime_disable_irq(d);
}

static struct irq_chip crime_edge_interrupt = {
	.name		= "IP32 CRIME",
	.irq_ack	= crime_edge_mask_and_ack_irq,
	.irq_mask	= crime_disable_irq,
	.irq_mask_ack	= crime_edge_mask_and_ack_irq,
	.irq_unmask	= crime_enable_irq,
};

/*
 * This is for MACE PCI interrupts.  We can decrease bus traffic by masking
 * as close to the source as possible.	This also means we can take the
 * next chunk of the CRIME register in one piece.
 */

static unsigned long macepci_mask;

static void enable_macepci_irq(struct irq_data *d)
{
	macepci_mask |= MACEPCI_CONTROL_INT(d->irq - MACEPCI_SCSI0_IRQ);
	mace->pci.control = macepci_mask;
	crime_mask |= 1 << (d->irq - CRIME_IRQ_BASE);
	crime->imask = crime_mask;
}

static void disable_macepci_irq(struct irq_data *d)
{
	crime_mask &= ~(1 << (d->irq - CRIME_IRQ_BASE));
	crime->imask = crime_mask;
	flush_crime_bus();
	macepci_mask &= ~MACEPCI_CONTROL_INT(d->irq - MACEPCI_SCSI0_IRQ);
	mace->pci.control = macepci_mask;
	flush_mace_bus();
}

static struct irq_chip ip32_macepci_interrupt = {
	.name = "IP32 MACE PCI",
	.irq_mask = disable_macepci_irq,
	.irq_unmask = enable_macepci_irq,
};

/* This is used for MACE ISA interrupts.  That means bits 4-6 in the
 * CRIME register.
 */

#define MACEISA_AUDIO_INT	(MACEISA_AUDIO_SW_INT |		\
				 MACEISA_AUDIO_SC_INT |		\
				 MACEISA_AUDIO1_DMAT_INT |	\
				 MACEISA_AUDIO1_OF_INT |	\
				 MACEISA_AUDIO2_DMAT_INT |	\
				 MACEISA_AUDIO2_MERR_INT |	\
				 MACEISA_AUDIO3_DMAT_INT |	\
				 MACEISA_AUDIO3_MERR_INT)
#define MACEISA_MISC_INT	(MACEISA_RTC_INT |		\
				 MACEISA_KEYB_INT |		\
				 MACEISA_KEYB_POLL_INT |	\
				 MACEISA_MOUSE_INT |		\
				 MACEISA_MOUSE_POLL_INT |	\
				 MACEISA_TIMER0_INT |		\
				 MACEISA_TIMER1_INT |		\
				 MACEISA_TIMER2_INT)
#define MACEISA_SUPERIO_INT	(MACEISA_PARALLEL_INT |		\
				 MACEISA_PAR_CTXA_INT |		\
				 MACEISA_PAR_CTXB_INT |		\
				 MACEISA_PAR_MERR_INT |		\
				 MACEISA_SERIAL1_INT |		\
				 MACEISA_SERIAL1_TDMAT_INT |	\
				 MACEISA_SERIAL1_TDMAPR_INT |	\
				 MACEISA_SERIAL1_TDMAME_INT |	\
				 MACEISA_SERIAL1_RDMAT_INT |	\
				 MACEISA_SERIAL1_RDMAOR_INT |	\
				 MACEISA_SERIAL2_INT |		\
				 MACEISA_SERIAL2_TDMAT_INT |	\
				 MACEISA_SERIAL2_TDMAPR_INT |	\
				 MACEISA_SERIAL2_TDMAME_INT |	\
				 MACEISA_SERIAL2_RDMAT_INT |	\
				 MACEISA_SERIAL2_RDMAOR_INT)

static unsigned long maceisa_mask;

static void enable_maceisa_irq(struct irq_data *d)
{
	unsigned int crime_int = 0;

	pr_debug("maceisa enable: %u\n", d->irq);

	switch (d->irq) {
	case MACEISA_AUDIO_SW_IRQ ... MACEISA_AUDIO3_MERR_IRQ:
		crime_int = MACE_AUDIO_INT;
		break;
	case MACEISA_RTC_IRQ ... MACEISA_TIMER2_IRQ:
		crime_int = MACE_MISC_INT;
		break;
	case MACEISA_PARALLEL_IRQ ... MACEISA_SERIAL2_RDMAOR_IRQ:
		crime_int = MACE_SUPERIO_INT;
		break;
	}
	pr_debug("crime_int %08x enabled\n", crime_int);
	crime_mask |= crime_int;
	crime->imask = crime_mask;
	maceisa_mask |= 1 << (d->irq - MACEISA_AUDIO_SW_IRQ);
	mace->perif.ctrl.imask = maceisa_mask;
}

static void disable_maceisa_irq(struct irq_data *d)
{
	unsigned int crime_int = 0;

	maceisa_mask &= ~(1 << (d->irq - MACEISA_AUDIO_SW_IRQ));
	if (!(maceisa_mask & MACEISA_AUDIO_INT))
		crime_int |= MACE_AUDIO_INT;
	if (!(maceisa_mask & MACEISA_MISC_INT))
		crime_int |= MACE_MISC_INT;
	if (!(maceisa_mask & MACEISA_SUPERIO_INT))
		crime_int |= MACE_SUPERIO_INT;
	crime_mask &= ~crime_int;
	crime->imask = crime_mask;
	flush_crime_bus();
	mace->perif.ctrl.imask = maceisa_mask;
	flush_mace_bus();
}

static void mask_and_ack_maceisa_irq(struct irq_data *d)
{
	unsigned long mace_int;

	/* edge triggered */
	mace_int = mace->perif.ctrl.istat;
	mace_int &= ~(1 << (d->irq - MACEISA_AUDIO_SW_IRQ));
	mace->perif.ctrl.istat = mace_int;

	disable_maceisa_irq(d);
}

static struct irq_chip ip32_maceisa_level_interrupt = {
	.name		= "IP32 MACE ISA",
	.irq_mask	= disable_maceisa_irq,
	.irq_unmask	= enable_maceisa_irq,
};

static struct irq_chip ip32_maceisa_edge_interrupt = {
	.name		= "IP32 MACE ISA",
	.irq_ack	= mask_and_ack_maceisa_irq,
	.irq_mask	= disable_maceisa_irq,
	.irq_mask_ack	= mask_and_ack_maceisa_irq,
	.irq_unmask	= enable_maceisa_irq,
};

/* This is used for regular non-ISA, non-PCI MACE interrupts.  That means
 * bits 0-3 and 7 in the CRIME register.
 */

static void enable_mace_irq(struct irq_data *d)
{
	unsigned int bit = d->irq - CRIME_IRQ_BASE;

	crime_mask |= (1 << bit);
	crime->imask = crime_mask;
}

static void disable_mace_irq(struct irq_data *d)
{
	unsigned int bit = d->irq - CRIME_IRQ_BASE;

	crime_mask &= ~(1 << bit);
	crime->imask = crime_mask;
	flush_crime_bus();
}

static struct irq_chip ip32_mace_interrupt = {
	.name = "IP32 MACE",
	.irq_mask = disable_mace_irq,
	.irq_unmask = enable_mace_irq,
};

static void ip32_unknown_interrupt(void)
{
	printk("Unknown interrupt occurred!\n");
	printk("cp0_status: %08x\n", read_c0_status());
	printk("cp0_cause: %08x\n", read_c0_cause());
	printk("CRIME intr mask: %016lx\n", crime->imask);
	printk("CRIME intr status: %016lx\n", crime->istat);
	printk("CRIME hardware intr register: %016lx\n", crime->hard_int);
	printk("MACE ISA intr mask: %08lx\n", mace->perif.ctrl.imask);
	printk("MACE ISA intr status: %08lx\n", mace->perif.ctrl.istat);
	printk("MACE PCI control register: %08x\n", mace->pci.control);

	printk("Register dump:\n");
	show_regs(get_irq_regs());

	printk("Please mail this report to linux-mips@linux-mips.org\n");
	printk("Spinning...");
	while(1) ;
}

/* CRIME 1.1 appears to deliver all interrupts to this one pin. */
/* change this to loop over all edge-triggered irqs, exception masked out ones */
static void ip32_irq0(void)
{
	uint64_t crime_int;
	int irq = 0;

	/*
	 * Sanity check interrupt numbering enum.
	 * MACE got 32 interrupts and there are 32 MACE ISA interrupts daisy
	 * chained.
	 */
	BUILD_BUG_ON(CRIME_VICE_IRQ - MACE_VID_IN1_IRQ != 31);
	BUILD_BUG_ON(MACEISA_SERIAL2_RDMAOR_IRQ - MACEISA_AUDIO_SW_IRQ != 31);

	crime_int = crime->istat & crime_mask;

	/* crime sometime delivers spurious interrupts, ignore them */
	if (unlikely(crime_int == 0))
		return;

	irq = MACE_VID_IN1_IRQ + __ffs(crime_int);

	if (crime_int & CRIME_MACEISA_INT_MASK) {
		unsigned long mace_int = mace->perif.ctrl.istat;
		irq = __ffs(mace_int & maceisa_mask) + MACEISA_AUDIO_SW_IRQ;
	}

	pr_debug("*irq %u*\n", irq);
	do_IRQ(irq);
}

static void ip32_irq1(void)
{
	ip32_unknown_interrupt();
}

static void ip32_irq2(void)
{
	ip32_unknown_interrupt();
}

static void ip32_irq3(void)
{
	ip32_unknown_interrupt();
}

static void ip32_irq4(void)
{
	ip32_unknown_interrupt();
}

static void ip32_irq5(void)
{
	do_IRQ(MIPS_CPU_IRQ_BASE + 7);
}

asmlinkage void plat_irq_dispatch(void)
{
	unsigned int pending = read_c0_status() & read_c0_cause();

	if (likely(pending & IE_IRQ0))
		ip32_irq0();
	else if (unlikely(pending & IE_IRQ1))
		ip32_irq1();
	else if (unlikely(pending & IE_IRQ2))
		ip32_irq2();
	else if (unlikely(pending & IE_IRQ3))
		ip32_irq3();
	else if (unlikely(pending & IE_IRQ4))
		ip32_irq4();
	else if (likely(pending & IE_IRQ5))
		ip32_irq5();
}

void __init arch_init_irq(void)
{
	unsigned int irq;

	/* Install our interrupt handler, then clear and disable all
	 * CRIME and MACE interrupts. */
	crime->imask = 0;
	crime->hard_int = 0;
	crime->soft_int = 0;
	mace->perif.ctrl.istat = 0;
	mace->perif.ctrl.imask = 0;

	mips_cpu_irq_init();
	for (irq = CRIME_IRQ_BASE; irq <= IP32_IRQ_MAX; irq++) {
		switch (irq) {
		case MACE_VID_IN1_IRQ ... MACE_PCI_BRIDGE_IRQ:
			irq_set_chip_and_handler_name(irq,
						      &ip32_mace_interrupt,
						      handle_level_irq,
						      "level");
			break;

		case MACEPCI_SCSI0_IRQ ...  MACEPCI_SHARED2_IRQ:
			irq_set_chip_and_handler_name(irq,
						      &ip32_macepci_interrupt,
						      handle_level_irq,
						      "level");
			break;

		case CRIME_CPUERR_IRQ:
		case CRIME_MEMERR_IRQ:
			irq_set_chip_and_handler_name(irq,
						      &crime_level_interrupt,
						      handle_level_irq,
						      "level");
			break;

		case CRIME_GBE0_IRQ ... CRIME_GBE3_IRQ:
		case CRIME_RE_EMPTY_E_IRQ ... CRIME_RE_IDLE_E_IRQ:
		case CRIME_SOFT0_IRQ ... CRIME_SOFT2_IRQ:
		case CRIME_VICE_IRQ:
			irq_set_chip_and_handler_name(irq,
						      &crime_edge_interrupt,
						      handle_edge_irq,
						      "edge");
			break;

		case MACEISA_PARALLEL_IRQ:
		case MACEISA_SERIAL1_TDMAPR_IRQ:
		case MACEISA_SERIAL2_TDMAPR_IRQ:
			irq_set_chip_and_handler_name(irq,
						      &ip32_maceisa_edge_interrupt,
						      handle_edge_irq,
						      "edge");
			break;

		default:
			irq_set_chip_and_handler_name(irq,
						      &ip32_maceisa_level_interrupt,
						      handle_level_irq,
						      "level");
			break;
		}
	}
	setup_irq(CRIME_MEMERR_IRQ, &memerr_irq);
	setup_irq(CRIME_CPUERR_IRQ, &cpuerr_irq);

#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
	change_c0_status(ST0_IM, ALLINTS);
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Code to handle IP32 IRQs
	3	*
	4	* This file is subject to the terms and conditions of the GNU General Public
	5	* License. See the file "COPYING" in the main directory of this archive
	6	* for more details.
	7	*
	8	* Copyright (C) 2000 Harald Koerfgen
	9	* Copyright (C) 2001 Keith M Wesolowski
	10	*/
	11	#include <linux/init.h>
	12	#include <linux/kernel_stat.h>
	13	#include <linux/types.h>
	14	#include <linux/interrupt.h>
	15	#include <linux/irq.h>
	16	#include <linux/bitops.h>
	17	#include <linux/kernel.h>
1da177e4 LT	18	#include <linux/mm.h>
	19	#include <linux/random.h>
	20	#include <linux/sched.h>
	21
dd67b155	22	#include <asm/irq_cpu.h>
1da177e4 LT	23	#include <asm/mipsregs.h>
1da177e4 LT	24	#include <asm/signal.h>
1da177e4 LT	25	#include <asm/time.h>
	26	#include <asm/ip32/crime.h>
	27	#include <asm/ip32/mace.h>
	28	#include <asm/ip32/ip32_ints.h>
	29
	30	/* issue a PIO read to make sure no PIO writes are pending */
	31	static void inline flush_crime_bus(void)
	32	{
b6d7c7a9	33	crime->control;
1da177e4 LT	34	}
	35
	36	static void inline flush_mace_bus(void)
	37	{
b6d7c7a9	38	mace->perif.ctrl.misc;
1da177e4 LT	39	}
1da177e4 LT	40
dd67b155 RB	41	/*
dd67b155 RB	42	* O2 irq map
1da177e4 LT	43	*
	44	* IP0 -> software (ignored)
	45	* IP1 -> software (ignored)
	46	* IP2 -> (irq0) C crime 1.1 all interrupts; crime 1.5 ???
	47	* IP3 -> (irq1) X unknown
	48	* IP4 -> (irq2) X unknown
	49	* IP5 -> (irq3) X unknown
	50	* IP6 -> (irq4) X unknown
dd67b155	51	* IP7 -> (irq5) 7 CPU count/compare timer (system timer)
1da177e4 LT	52	*
	53	* crime: (C)
	54	*
	55	* CRIME_INT_STAT 31:0:
	56	*
dd67b155 RB	57	* 0 -> 8 Video in 1
	58	* 1 -> 9 Video in 2
	59	* 2 -> 10 Video out
	60	* 3 -> 11 Mace ethernet
1da177e4 LT	61	* 4 -> S SuperIO sub-interrupt
	62	* 5 -> M Miscellaneous sub-interrupt
	63	* 6 -> A Audio sub-interrupt
dd67b155 RB	64	* 7 -> 15 PCI bridge errors
	65	* 8 -> 16 PCI SCSI aic7xxx 0
	66	* 9 -> 17 PCI SCSI aic7xxx 1
	67	* 10 -> 18 PCI slot 0
	68	* 11 -> 19 unused (PCI slot 1)
	69	* 12 -> 20 unused (PCI slot 2)
	70	* 13 -> 21 unused (PCI shared 0)
	71	* 14 -> 22 unused (PCI shared 1)
	72	* 15 -> 23 unused (PCI shared 2)
	73	* 16 -> 24 GBE0 (E)
	74	* 17 -> 25 GBE1 (E)
	75	* 18 -> 26 GBE2 (E)
	76	* 19 -> 27 GBE3 (E)
	77	* 20 -> 28 CPU errors
	78	* 21 -> 29 Memory errors
	79	* 22 -> 30 RE empty edge (E)
	80	* 23 -> 31 RE full edge (E)
	81	* 24 -> 32 RE idle edge (E)
	82	* 25 -> 33 RE empty level
	83	* 26 -> 34 RE full level
	84	* 27 -> 35 RE idle level
	85	* 28 -> 36 unused (software 0) (E)
	86	* 29 -> 37 unused (software 1) (E)
	87	* 30 -> 38 unused (software 2) - crime 1.5 CPU SysCorError (E)
	88	* 31 -> 39 VICE
1da177e4 LT	89	*
	90	* S, M, A: Use the MACE ISA interrupt register
	91	* MACE_ISA_INT_STAT 31:0
	92	*
dd67b155 RB	93	* 0-7 -> 40-47 Audio
	94	* 8 -> 48 RTC
	95	* 9 -> 49 Keyboard
1da177e4	96	* 10 -> X Keyboard polled
dd67b155	97	* 11 -> 51 Mouse
1da177e4	98	* 12 -> X Mouse polled
dd67b155 RB	99	* 13-15 -> 53-55 Count/compare timers
	100	* 16-19 -> 56-59 Parallel (16 E)
	101	* 20-25 -> 60-62 Serial 1 (22 E)
	102	* 26-31 -> 66-71 Serial 2 (28 E)
1da177e4	103	*
dd67b155	104	* Note that this means IRQs 12-14, 50, and 52 do not exist. This is a
1da177e4 LT	105	* different IRQ map than IRIX uses, but that's OK as Linux irq handling
	106	* is quite different anyway.
	107	*/
	108
1da177e4	109	/* Some initial interrupts to set up */
937a8015 RB	110	extern irqreturn_t crime_memerr_intr(int irq, void *dev_id);
937a8015 RB	111	extern irqreturn_t crime_cpuerr_intr(int irq, void *dev_id);
1da177e4	112
ae537387	113	static struct irqaction memerr_irq = {
4e45171c	114	.handler = crime_memerr_intr,
4e45171c TG	115	.name = "CRIME memory error",
4e45171c TG	116	};
8a13ecd7	117
ae537387	118	static struct irqaction cpuerr_irq = {
4e45171c	119	.handler = crime_cpuerr_intr,
4e45171c TG	120	.name = "CRIME CPU error",
4e45171c TG	121	};
1da177e4	122
1da177e4 LT	123	/*
	124	* This is for pure CRIME interrupts - ie not MACE. The advantage?
	125	* We get to split the register in half and do faster lookups.
	126	*/
	127
	128	static uint64_t crime_mask;
	129
4d2796f8	130	static inline void crime_enable_irq(struct irq_data *d)
1da177e4	131	{
4d2796f8	132	unsigned int bit = d->irq - CRIME_IRQ_BASE;
8a13ecd7 RB	133
8a13ecd7 RB	134	crime_mask \|= 1 << bit;
1da177e4	135	crime->imask = crime_mask;
1da177e4 LT	136	}
1da177e4 LT	137
4d2796f8	138	static inline void crime_disable_irq(struct irq_data *d)
1da177e4	139	{
4d2796f8	140	unsigned int bit = d->irq - CRIME_IRQ_BASE;
8a13ecd7 RB	141
8a13ecd7 RB	142	crime_mask &= ~(1 << bit);
1da177e4 LT	143	crime->imask = crime_mask;
1da177e4 LT	144	flush_crime_bus();
1da177e4 LT	145	}
1da177e4 LT	146
8a13ecd7 RB	147	static struct irq_chip crime_level_interrupt = {
8a13ecd7 RB	148	.name = "IP32 CRIME",
4d2796f8 TG	149	.irq_mask = crime_disable_irq,
4d2796f8 TG	150	.irq_unmask = crime_enable_irq,
8a13ecd7 RB	151	};
8a13ecd7 RB	152
4d2796f8	153	static void crime_edge_mask_and_ack_irq(struct irq_data *d)
1da177e4	154	{
4d2796f8	155	unsigned int bit = d->irq - CRIME_IRQ_BASE;
8a13ecd7 RB	156	uint64_t crime_int;
8a13ecd7 RB	157
1da177e4	158	/* Edge triggered interrupts must be cleared. */
8a13ecd7 RB	159	crime_int = crime->hard_int;
	160	crime_int &= ~(1 << bit);
	161	crime->hard_int = crime_int;
	162
4d2796f8	163	crime_disable_irq(d);
1da177e4 LT	164	}
1da177e4 LT	165
8a13ecd7 RB	166	static struct irq_chip crime_edge_interrupt = {
8a13ecd7 RB	167	.name = "IP32 CRIME",
4d2796f8 TG	168	.irq_ack = crime_edge_mask_and_ack_irq,
	169	.irq_mask = crime_disable_irq,
	170	.irq_mask_ack = crime_edge_mask_and_ack_irq,
	171	.irq_unmask = crime_enable_irq,
1da177e4 LT	172	};
	173
	174	/*
	175	* This is for MACE PCI interrupts. We can decrease bus traffic by masking
70342287	176	* as close to the source as possible. This also means we can take the
1da177e4 LT	177	* next chunk of the CRIME register in one piece.
	178	*/
	179
	180	static unsigned long macepci_mask;
	181
4d2796f8	182	static void enable_macepci_irq(struct irq_data *d)
1da177e4	183	{
4d2796f8	184	macepci_mask \|= MACEPCI_CONTROL_INT(d->irq - MACEPCI_SCSI0_IRQ);
1da177e4	185	mace->pci.control = macepci_mask;
4d2796f8	186	crime_mask \|= 1 << (d->irq - CRIME_IRQ_BASE);
1da177e4	187	crime->imask = crime_mask;
1da177e4 LT	188	}
1da177e4 LT	189
4d2796f8	190	static void disable_macepci_irq(struct irq_data *d)
1da177e4	191	{
4d2796f8	192	crime_mask &= ~(1 << (d->irq - CRIME_IRQ_BASE));
1da177e4 LT	193	crime->imask = crime_mask;
1da177e4 LT	194	flush_crime_bus();
4d2796f8	195	macepci_mask &= ~MACEPCI_CONTROL_INT(d->irq - MACEPCI_SCSI0_IRQ);
1da177e4 LT	196	mace->pci.control = macepci_mask;
1da177e4 LT	197	flush_mace_bus();
1da177e4 LT	198	}
1da177e4 LT	199
94dee171	200	static struct irq_chip ip32_macepci_interrupt = {
70d21cde	201	.name = "IP32 MACE PCI",
4d2796f8 TG	202	.irq_mask = disable_macepci_irq,
4d2796f8 TG	203	.irq_unmask = enable_macepci_irq,
1da177e4 LT	204	};
	205
	206	/* This is used for MACE ISA interrupts. That means bits 4-6 in the
	207	* CRIME register.
	208	*/
	209
	210	#define MACEISA_AUDIO_INT (MACEISA_AUDIO_SW_INT \| \
	211	MACEISA_AUDIO_SC_INT \| \
	212	MACEISA_AUDIO1_DMAT_INT \| \
	213	MACEISA_AUDIO1_OF_INT \| \
	214	MACEISA_AUDIO2_DMAT_INT \| \
	215	MACEISA_AUDIO2_MERR_INT \| \
	216	MACEISA_AUDIO3_DMAT_INT \| \
	217	MACEISA_AUDIO3_MERR_INT)
	218	#define MACEISA_MISC_INT (MACEISA_RTC_INT \| \
	219	MACEISA_KEYB_INT \| \
	220	MACEISA_KEYB_POLL_INT \| \
	221	MACEISA_MOUSE_INT \| \
	222	MACEISA_MOUSE_POLL_INT \| \
cfbae5d3 TS	223	MACEISA_TIMER0_INT \| \
	224	MACEISA_TIMER1_INT \| \
	225	MACEISA_TIMER2_INT)
1da177e4 LT	226	#define MACEISA_SUPERIO_INT (MACEISA_PARALLEL_INT \| \
	227	MACEISA_PAR_CTXA_INT \| \
	228	MACEISA_PAR_CTXB_INT \| \
	229	MACEISA_PAR_MERR_INT \| \
	230	MACEISA_SERIAL1_INT \| \
	231	MACEISA_SERIAL1_TDMAT_INT \| \
	232	MACEISA_SERIAL1_TDMAPR_INT \| \
	233	MACEISA_SERIAL1_TDMAME_INT \| \
	234	MACEISA_SERIAL1_RDMAT_INT \| \
	235	MACEISA_SERIAL1_RDMAOR_INT \| \
	236	MACEISA_SERIAL2_INT \| \
	237	MACEISA_SERIAL2_TDMAT_INT \| \
	238	MACEISA_SERIAL2_TDMAPR_INT \| \
	239	MACEISA_SERIAL2_TDMAME_INT \| \
	240	MACEISA_SERIAL2_RDMAT_INT \| \
	241	MACEISA_SERIAL2_RDMAOR_INT)
	242
	243	static unsigned long maceisa_mask;
	244
4d2796f8	245	static void enable_maceisa_irq(struct irq_data *d)
1da177e4 LT	246	{
1da177e4 LT	247	unsigned int crime_int = 0;
1da177e4	248
4d2796f8	249	pr_debug("maceisa enable: %u\n", d->irq);
1da177e4	250
4d2796f8	251	switch (d->irq) {
1da177e4 LT	252	case MACEISA_AUDIO_SW_IRQ ... MACEISA_AUDIO3_MERR_IRQ:
	253	crime_int = MACE_AUDIO_INT;
	254	break;
cfbae5d3	255	case MACEISA_RTC_IRQ ... MACEISA_TIMER2_IRQ:
1da177e4 LT	256	crime_int = MACE_MISC_INT;
	257	break;
	258	case MACEISA_PARALLEL_IRQ ... MACEISA_SERIAL2_RDMAOR_IRQ:
	259	crime_int = MACE_SUPERIO_INT;
	260	break;
	261	}
8a13ecd7	262	pr_debug("crime_int %08x enabled\n", crime_int);
1da177e4 LT	263	crime_mask \|= crime_int;
1da177e4 LT	264	crime->imask = crime_mask;
4d2796f8	265	maceisa_mask \|= 1 << (d->irq - MACEISA_AUDIO_SW_IRQ);
1da177e4	266	mace->perif.ctrl.imask = maceisa_mask;
1da177e4 LT	267	}
1da177e4 LT	268
4d2796f8	269	static void disable_maceisa_irq(struct irq_data *d)
1da177e4 LT	270	{
1da177e4 LT	271	unsigned int crime_int = 0;
1da177e4	272
4d2796f8	273	maceisa_mask &= ~(1 << (d->irq - MACEISA_AUDIO_SW_IRQ));
70342287	274	if (!(maceisa_mask & MACEISA_AUDIO_INT))
1da177e4	275	crime_int \|= MACE_AUDIO_INT;
70342287	276	if (!(maceisa_mask & MACEISA_MISC_INT))
1da177e4	277	crime_int \|= MACE_MISC_INT;
70342287	278	if (!(maceisa_mask & MACEISA_SUPERIO_INT))
1da177e4 LT	279	crime_int \|= MACE_SUPERIO_INT;
	280	crime_mask &= ~crime_int;
	281	crime->imask = crime_mask;
	282	flush_crime_bus();
	283	mace->perif.ctrl.imask = maceisa_mask;
	284	flush_mace_bus();
1da177e4 LT	285	}
1da177e4 LT	286
4d2796f8	287	static void mask_and_ack_maceisa_irq(struct irq_data *d)
1da177e4	288	{
1603b5ac	289	unsigned long mace_int;
1da177e4	290
c87e0909 RB	291	/* edge triggered */
c87e0909 RB	292	mace_int = mace->perif.ctrl.istat;
4d2796f8	293	mace_int &= ~(1 << (d->irq - MACEISA_AUDIO_SW_IRQ));
c87e0909 RB	294	mace->perif.ctrl.istat = mace_int;
c87e0909 RB	295
4d2796f8	296	disable_maceisa_irq(d);
1da177e4 LT	297	}
1da177e4 LT	298
c87e0909 RB	299	static struct irq_chip ip32_maceisa_level_interrupt = {
c87e0909 RB	300	.name = "IP32 MACE ISA",
4d2796f8 TG	301	.irq_mask = disable_maceisa_irq,
4d2796f8 TG	302	.irq_unmask = enable_maceisa_irq,
c87e0909 RB	303	};
	304
	305	static struct irq_chip ip32_maceisa_edge_interrupt = {
8a13ecd7	306	.name = "IP32 MACE ISA",
4d2796f8 TG	307	.irq_ack = mask_and_ack_maceisa_irq,
	308	.irq_mask = disable_maceisa_irq,
	309	.irq_mask_ack = mask_and_ack_maceisa_irq,
	310	.irq_unmask = enable_maceisa_irq,
1da177e4 LT	311	};
	312
	313	/* This is used for regular non-ISA, non-PCI MACE interrupts. That means
	314	* bits 0-3 and 7 in the CRIME register.
	315	*/
	316
4d2796f8	317	static void enable_mace_irq(struct irq_data *d)
1da177e4	318	{
4d2796f8	319	unsigned int bit = d->irq - CRIME_IRQ_BASE;
98ce4721 RB	320
98ce4721 RB	321	crime_mask \|= (1 << bit);
1da177e4	322	crime->imask = crime_mask;
1da177e4 LT	323	}
1da177e4 LT	324
4d2796f8	325	static void disable_mace_irq(struct irq_data *d)
1da177e4	326	{
4d2796f8	327	unsigned int bit = d->irq - CRIME_IRQ_BASE;
98ce4721 RB	328
98ce4721 RB	329	crime_mask &= ~(1 << bit);
1da177e4 LT	330	crime->imask = crime_mask;
1da177e4 LT	331	flush_crime_bus();
1da177e4 LT	332	}
1da177e4 LT	333
94dee171	334	static struct irq_chip ip32_mace_interrupt = {
70d21cde	335	.name = "IP32 MACE",
4d2796f8 TG	336	.irq_mask = disable_mace_irq,
4d2796f8 TG	337	.irq_unmask = enable_mace_irq,
1da177e4 LT	338	};
1da177e4 LT	339
937a8015	340	static void ip32_unknown_interrupt(void)
1da177e4	341	{
49a89efb RB	342	printk("Unknown interrupt occurred!\n");
	343	printk("cp0_status: %08x\n", read_c0_status());
	344	printk("cp0_cause: %08x\n", read_c0_cause());
	345	printk("CRIME intr mask: %016lx\n", crime->imask);
	346	printk("CRIME intr status: %016lx\n", crime->istat);
	347	printk("CRIME hardware intr register: %016lx\n", crime->hard_int);
	348	printk("MACE ISA intr mask: %08lx\n", mace->perif.ctrl.imask);
	349	printk("MACE ISA intr status: %08lx\n", mace->perif.ctrl.istat);
	350	printk("MACE PCI control register: %08x\n", mace->pci.control);
1da177e4 LT	351
1da177e4 LT	352	printk("Register dump:\n");
937a8015	353	show_regs(get_irq_regs());
1da177e4 LT	354
	355	printk("Please mail this report to linux-mips@linux-mips.org\n");
	356	printk("Spinning...");
	357	while(1) ;
	358	}
	359
	360	/* CRIME 1.1 appears to deliver all interrupts to this one pin. */
	361	/* change this to loop over all edge-triggered irqs, exception masked out ones */
937a8015	362	static void ip32_irq0(void)
1da177e4 LT	363	{
	364	uint64_t crime_int;
	365	int irq = 0;
	366
dd67b155 RB	367	/*
	368	* Sanity check interrupt numbering enum.
	369	* MACE got 32 interrupts and there are 32 MACE ISA interrupts daisy
	370	* chained.
	371	*/
	372	BUILD_BUG_ON(CRIME_VICE_IRQ - MACE_VID_IN1_IRQ != 31);
	373	BUILD_BUG_ON(MACEISA_SERIAL2_RDMAOR_IRQ - MACEISA_AUDIO_SW_IRQ != 31);
	374
1da177e4	375	crime_int = crime->istat & crime_mask;
1faf7f25 TB	376
	377	/* crime sometime delivers spurious interrupts, ignore them */
	378	if (unlikely(crime_int == 0))
	379	return;
	380
dd67b155	381	irq = MACE_VID_IN1_IRQ + __ffs(crime_int);
1da177e4 LT	382
	383	if (crime_int & CRIME_MACEISA_INT_MASK) {
	384	unsigned long mace_int = mace->perif.ctrl.istat;
dd67b155	385	irq = __ffs(mace_int & maceisa_mask) + MACEISA_AUDIO_SW_IRQ;
1da177e4	386	}
dd67b155	387
8a13ecd7	388	pr_debug("irq %u\n", irq);
937a8015	389	do_IRQ(irq);
1da177e4 LT	390	}
1da177e4 LT	391
937a8015	392	static void ip32_irq1(void)
1da177e4	393	{
937a8015	394	ip32_unknown_interrupt();
1da177e4 LT	395	}
1da177e4 LT	396
937a8015	397	static void ip32_irq2(void)
1da177e4	398	{
937a8015	399	ip32_unknown_interrupt();
1da177e4 LT	400	}
1da177e4 LT	401
937a8015	402	static void ip32_irq3(void)
1da177e4	403	{
937a8015	404	ip32_unknown_interrupt();
1da177e4 LT	405	}
1da177e4 LT	406
937a8015	407	static void ip32_irq4(void)
1da177e4	408	{
937a8015	409	ip32_unknown_interrupt();
1da177e4 LT	410	}
1da177e4 LT	411
937a8015	412	static void ip32_irq5(void)
1da177e4	413	{
dd67b155	414	do_IRQ(MIPS_CPU_IRQ_BASE + 7);
1da177e4 LT	415	}
1da177e4 LT	416
937a8015	417	asmlinkage void plat_irq_dispatch(void)
e4ac58af	418	{
119537c0	419	unsigned int pending = read_c0_status() & read_c0_cause();
e4ac58af RB	420
e4ac58af RB	421	if (likely(pending & IE_IRQ0))
937a8015	422	ip32_irq0();
e4ac58af	423	else if (unlikely(pending & IE_IRQ1))
937a8015	424	ip32_irq1();
e4ac58af	425	else if (unlikely(pending & IE_IRQ2))
937a8015	426	ip32_irq2();
e4ac58af	427	else if (unlikely(pending & IE_IRQ3))
937a8015	428	ip32_irq3();
e4ac58af	429	else if (unlikely(pending & IE_IRQ4))
937a8015	430	ip32_irq4();
e4ac58af	431	else if (likely(pending & IE_IRQ5))
937a8015	432	ip32_irq5();
e4ac58af RB	433	}
e4ac58af RB	434
1da177e4 LT	435	void __init arch_init_irq(void)
	436	{
	437	unsigned int irq;
	438
	439	/* Install our interrupt handler, then clear and disable all
	440	* CRIME and MACE interrupts. */
	441	crime->imask = 0;
	442	crime->hard_int = 0;
	443	crime->soft_int = 0;
	444	mace->perif.ctrl.istat = 0;
	445	mace->perif.ctrl.imask = 0;
1da177e4	446
dd67b155	447	mips_cpu_irq_init();
98ce4721	448	for (irq = CRIME_IRQ_BASE; irq <= IP32_IRQ_MAX; irq++) {
dd67b155 RB	449	switch (irq) {
dd67b155 RB	450	case MACE_VID_IN1_IRQ ... MACE_PCI_BRIDGE_IRQ:
e4ec7989 TG	451	irq_set_chip_and_handler_name(irq,
	452	&ip32_mace_interrupt,
	453	handle_level_irq,
	454	"level");
dd67b155	455	break;
c87e0909	456
dd67b155	457	case MACEPCI_SCSI0_IRQ ... MACEPCI_SHARED2_IRQ:
e4ec7989 TG	458	irq_set_chip_and_handler_name(irq,
	459	&ip32_macepci_interrupt,
	460	handle_level_irq,
	461	"level");
8a13ecd7	462	break;
c87e0909	463
8a13ecd7 RB	464	case CRIME_CPUERR_IRQ:
8a13ecd7 RB	465	case CRIME_MEMERR_IRQ:
e4ec7989 TG	466	irq_set_chip_and_handler_name(irq,
	467	&crime_level_interrupt,
	468	handle_level_irq,
	469	"level");
dd67b155	470	break;
c87e0909	471
2fe06260	472	case CRIME_GBE0_IRQ ... CRIME_GBE3_IRQ:
8a13ecd7 RB	473	case CRIME_RE_EMPTY_E_IRQ ... CRIME_RE_IDLE_E_IRQ:
8a13ecd7 RB	474	case CRIME_SOFT0_IRQ ... CRIME_SOFT2_IRQ:
8a13ecd7	475	case CRIME_VICE_IRQ:
e4ec7989 TG	476	irq_set_chip_and_handler_name(irq,
	477	&crime_edge_interrupt,
	478	handle_edge_irq,
	479	"edge");
c87e0909 RB	480	break;
	481
	482	case MACEISA_PARALLEL_IRQ:
	483	case MACEISA_SERIAL1_TDMAPR_IRQ:
	484	case MACEISA_SERIAL2_TDMAPR_IRQ:
e4ec7989 TG	485	irq_set_chip_and_handler_name(irq,
	486	&ip32_maceisa_edge_interrupt,
	487	handle_edge_irq,
	488	"edge");
dd67b155	489	break;
c87e0909	490
dd67b155	491	default:
e4ec7989 TG	492	irq_set_chip_and_handler_name(irq,
	493	&ip32_maceisa_level_interrupt,
	494	handle_level_irq,
	495	"level");
8a13ecd7	496	break;
dd67b155	497	}
1da177e4 LT	498	}
	499	setup_irq(CRIME_MEMERR_IRQ, &memerr_irq);
	500	setup_irq(CRIME_CPUERR_IRQ, &cpuerr_irq);
	501
	502	#define ALLINTS (IE_IRQ0 \| IE_IRQ1 \| IE_IRQ2 \| IE_IRQ3 \| IE_IRQ4 \| IE_IRQ5)
	503	change_c0_status(ST0_IM, ALLINTS);
	504	}