[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / mips / sgi-ip32 / ip32-irq.c

/*
 * Code to handle IP32 IRQs
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2000 Harald Koerfgen
 * Copyright (C) 2001 Keith M Wesolowski
 */
#include <linux/init.h>
#include <linux/kernel_stat.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/bitops.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/mm.h>
#include <linux/random.h>
#include <linux/sched.h>

#include <asm/mipsregs.h>
#include <asm/signal.h>
#include <asm/system.h>
#include <asm/time.h>
#include <asm/ip32/crime.h>
#include <asm/ip32/mace.h>
#include <asm/ip32/ip32_ints.h>

/* issue a PIO read to make sure no PIO writes are pending */
static void inline flush_crime_bus(void)
{
	crime->control;
}

static void inline flush_mace_bus(void)
{
	mace->perif.ctrl.misc;
}

#undef DEBUG_IRQ
#ifdef DEBUG_IRQ
#define DBG(x...) printk(x)
#else
#define DBG(x...)
#endif

/* O2 irq map
 *
 * IP0 -> software (ignored)
 * IP1 -> software (ignored)
 * IP2 -> (irq0) C crime 1.1 all interrupts; crime 1.5 ???
 * IP3 -> (irq1) X unknown
 * IP4 -> (irq2) X unknown
 * IP5 -> (irq3) X unknown
 * IP6 -> (irq4) X unknown
 * IP7 -> (irq5) 0 CPU count/compare timer (system timer)
 *
 * crime: (C)
 *
 * CRIME_INT_STAT 31:0:
 *
 * 0  -> 1  Video in 1
 * 1  -> 2  Video in 2
 * 2  -> 3  Video out
 * 3  -> 4  Mace ethernet
 * 4  -> S  SuperIO sub-interrupt
 * 5  -> M  Miscellaneous sub-interrupt
 * 6  -> A  Audio sub-interrupt
 * 7  -> 8  PCI bridge errors
 * 8  -> 9  PCI SCSI aic7xxx 0
 * 9  -> 10 PCI SCSI aic7xxx 1
 * 10 -> 11 PCI slot 0
 * 11 -> 12 unused (PCI slot 1)
 * 12 -> 13 unused (PCI slot 2)
 * 13 -> 14 unused (PCI shared 0)
 * 14 -> 15 unused (PCI shared 1)
 * 15 -> 16 unused (PCI shared 2)
 * 16 -> 17 GBE0 (E)
 * 17 -> 18 GBE1 (E)
 * 18 -> 19 GBE2 (E)
 * 19 -> 20 GBE3 (E)
 * 20 -> 21 CPU errors
 * 21 -> 22 Memory errors
 * 22 -> 23 RE empty edge (E)
 * 23 -> 24 RE full edge (E)
 * 24 -> 25 RE idle edge (E)
 * 25 -> 26 RE empty level
 * 26 -> 27 RE full level
 * 27 -> 28 RE idle level
 * 28 -> 29 unused (software 0) (E)
 * 29 -> 30 unused (software 1) (E)
 * 30 -> 31 unused (software 2) - crime 1.5 CPU SysCorError (E)
 * 31 -> 32 VICE
 *
 * S, M, A: Use the MACE ISA interrupt register
 * MACE_ISA_INT_STAT 31:0
 *
 * 0-7 -> 33-40 Audio
 * 8 -> 41 RTC
 * 9 -> 42 Keyboard
 * 10 -> X Keyboard polled
 * 11 -> 44 Mouse
 * 12 -> X Mouse polled
 * 13-15 -> 46-48 Count/compare timers
 * 16-19 -> 49-52 Parallel (16 E)
 * 20-25 -> 53-58 Serial 1 (22 E)
 * 26-31 -> 59-64 Serial 2 (28 E)
 *
 * Note that this means IRQs 5-7, 43, and 45 do not exist.  This is a
 * different IRQ map than IRIX uses, but that's OK as Linux irq handling
 * is quite different anyway.
 */

/* Some initial interrupts to set up */
extern irqreturn_t crime_memerr_intr(int irq, void *dev_id);
extern irqreturn_t crime_cpuerr_intr(int irq, void *dev_id);

struct irqaction memerr_irq = { crime_memerr_intr, IRQF_DISABLED,
			CPU_MASK_NONE, "CRIME memory error", NULL, NULL };
struct irqaction cpuerr_irq = { crime_cpuerr_intr, IRQF_DISABLED,
			CPU_MASK_NONE, "CRIME CPU error", NULL, NULL };

/*
 * For interrupts wired from a single device to the CPU.  Only the clock
 * uses this it seems, which is IRQ 0 and IP7.
 */

static void enable_cpu_irq(unsigned int irq)
{
	set_c0_status(STATUSF_IP7);
}

static void disable_cpu_irq(unsigned int irq)
{
	clear_c0_status(STATUSF_IP7);
}

static void end_cpu_irq(unsigned int irq)
{
	if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
		enable_cpu_irq (irq);
}

static struct irq_chip ip32_cpu_interrupt = {
	.name = "IP32 CPU",
	.ack = disable_cpu_irq,
	.mask = disable_cpu_irq,
	.mask_ack = disable_cpu_irq,
	.unmask = enable_cpu_irq,
	.end = end_cpu_irq,
};

/*
 * This is for pure CRIME interrupts - ie not MACE.  The advantage?
 * We get to split the register in half and do faster lookups.
 */

static uint64_t crime_mask;

static void enable_crime_irq(unsigned int irq)
{
	crime_mask |= 1 << (irq - 1);
	crime->imask = crime_mask;
}

static void disable_crime_irq(unsigned int irq)
{
	crime_mask &= ~(1 << (irq - 1));
	crime->imask = crime_mask;
	flush_crime_bus();
}

static void mask_and_ack_crime_irq(unsigned int irq)
{
	/* Edge triggered interrupts must be cleared. */
	if ((irq >= CRIME_GBE0_IRQ && irq <= CRIME_GBE3_IRQ)
	    || (irq >= CRIME_RE_EMPTY_E_IRQ && irq <= CRIME_RE_IDLE_E_IRQ)
	    || (irq >= CRIME_SOFT0_IRQ && irq <= CRIME_SOFT2_IRQ)) {
	        uint64_t crime_int;
		crime_int = crime->hard_int;
		crime_int &= ~(1 << (irq - 1));
		crime->hard_int = crime_int;
	}
	disable_crime_irq(irq);
}

static void end_crime_irq(unsigned int irq)
{
	if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
		enable_crime_irq(irq);
}

static struct irq_chip ip32_crime_interrupt = {
	.name = "IP32 CRIME",
	.ack = mask_and_ack_crime_irq,
	.mask = disable_crime_irq,
	.mask_ack = mask_and_ack_crime_irq,
	.unmask = enable_crime_irq,
	.end = end_crime_irq,
};

/*
 * This is for MACE PCI interrupts.  We can decrease bus traffic by masking
 * as close to the source as possible.  This also means we can take the
 * next chunk of the CRIME register in one piece.
 */

static unsigned long macepci_mask;

static void enable_macepci_irq(unsigned int irq)
{
	macepci_mask |= MACEPCI_CONTROL_INT(irq - 9);
	mace->pci.control = macepci_mask;
	crime_mask |= 1 << (irq - 1);
	crime->imask = crime_mask;
}

static void disable_macepci_irq(unsigned int irq)
{
	crime_mask &= ~(1 << (irq - 1));
	crime->imask = crime_mask;
	flush_crime_bus();
	macepci_mask &= ~MACEPCI_CONTROL_INT(irq - 9);
	mace->pci.control = macepci_mask;
	flush_mace_bus();
}

static void end_macepci_irq(unsigned int irq)
{
	if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
		enable_macepci_irq(irq);
}

static struct irq_chip ip32_macepci_interrupt = {
	.name = "IP32 MACE PCI",
	.ack = disable_macepci_irq,
	.mask = disable_macepci_irq,
	.mask_ack = disable_macepci_irq,
	.unmask = enable_macepci_irq,
	.end = end_macepci_irq,
};

/* This is used for MACE ISA interrupts.  That means bits 4-6 in the
 * CRIME register.
 */

#define MACEISA_AUDIO_INT	(MACEISA_AUDIO_SW_INT |		\
				 MACEISA_AUDIO_SC_INT |		\
				 MACEISA_AUDIO1_DMAT_INT |	\
				 MACEISA_AUDIO1_OF_INT |	\
				 MACEISA_AUDIO2_DMAT_INT |	\
				 MACEISA_AUDIO2_MERR_INT |	\
				 MACEISA_AUDIO3_DMAT_INT |	\
				 MACEISA_AUDIO3_MERR_INT)
#define MACEISA_MISC_INT	(MACEISA_RTC_INT |		\
				 MACEISA_KEYB_INT |		\
				 MACEISA_KEYB_POLL_INT |	\
				 MACEISA_MOUSE_INT |		\
				 MACEISA_MOUSE_POLL_INT |	\
				 MACEISA_TIMER0_INT |		\
				 MACEISA_TIMER1_INT |		\
				 MACEISA_TIMER2_INT)
#define MACEISA_SUPERIO_INT	(MACEISA_PARALLEL_INT |		\
				 MACEISA_PAR_CTXA_INT |		\
				 MACEISA_PAR_CTXB_INT |		\
				 MACEISA_PAR_MERR_INT |		\
				 MACEISA_SERIAL1_INT |		\
				 MACEISA_SERIAL1_TDMAT_INT |	\
				 MACEISA_SERIAL1_TDMAPR_INT |	\
				 MACEISA_SERIAL1_TDMAME_INT |	\
				 MACEISA_SERIAL1_RDMAT_INT |	\
				 MACEISA_SERIAL1_RDMAOR_INT |	\
				 MACEISA_SERIAL2_INT |		\
				 MACEISA_SERIAL2_TDMAT_INT |	\
				 MACEISA_SERIAL2_TDMAPR_INT |	\
				 MACEISA_SERIAL2_TDMAME_INT |	\
				 MACEISA_SERIAL2_RDMAT_INT |	\
				 MACEISA_SERIAL2_RDMAOR_INT)

static unsigned long maceisa_mask;

static void enable_maceisa_irq (unsigned int irq)
{
	unsigned int crime_int = 0;

	DBG ("maceisa enable: %u\n", irq);

	switch (irq) {
	case MACEISA_AUDIO_SW_IRQ ... MACEISA_AUDIO3_MERR_IRQ:
		crime_int = MACE_AUDIO_INT;
		break;
	case MACEISA_RTC_IRQ ... MACEISA_TIMER2_IRQ:
		crime_int = MACE_MISC_INT;
		break;
	case MACEISA_PARALLEL_IRQ ... MACEISA_SERIAL2_RDMAOR_IRQ:
		crime_int = MACE_SUPERIO_INT;
		break;
	}
	DBG ("crime_int %08x enabled\n", crime_int);
	crime_mask |= crime_int;
	crime->imask = crime_mask;
	maceisa_mask |= 1 << (irq - 33);
	mace->perif.ctrl.imask = maceisa_mask;
}

static void disable_maceisa_irq(unsigned int irq)
{
	unsigned int crime_int = 0;

	maceisa_mask &= ~(1 << (irq - 33));
        if(!(maceisa_mask & MACEISA_AUDIO_INT))
		crime_int |= MACE_AUDIO_INT;
        if(!(maceisa_mask & MACEISA_MISC_INT))
		crime_int |= MACE_MISC_INT;
        if(!(maceisa_mask & MACEISA_SUPERIO_INT))
		crime_int |= MACE_SUPERIO_INT;
	crime_mask &= ~crime_int;
	crime->imask = crime_mask;
	flush_crime_bus();
	mace->perif.ctrl.imask = maceisa_mask;
	flush_mace_bus();
}

static void mask_and_ack_maceisa_irq(unsigned int irq)
{
	unsigned long mace_int;

	switch (irq) {
	case MACEISA_PARALLEL_IRQ:
	case MACEISA_SERIAL1_TDMAPR_IRQ:
	case MACEISA_SERIAL2_TDMAPR_IRQ:
		/* edge triggered */
		mace_int = mace->perif.ctrl.istat;
		mace_int &= ~(1 << (irq - 33));
		mace->perif.ctrl.istat = mace_int;
		break;
	}
	disable_maceisa_irq(irq);
}

static void end_maceisa_irq(unsigned irq)
{
	if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
		enable_maceisa_irq(irq);
}

static struct irq_chip ip32_maceisa_interrupt = {
	.name = "IP32 MACE ISA",
	.ack = mask_and_ack_maceisa_irq,
	.mask = disable_maceisa_irq,
	.mask_ack = mask_and_ack_maceisa_irq,
	.unmask = enable_maceisa_irq,
	.end = end_maceisa_irq,
};

/* This is used for regular non-ISA, non-PCI MACE interrupts.  That means
 * bits 0-3 and 7 in the CRIME register.
 */

static void enable_mace_irq(unsigned int irq)
{
	crime_mask |= 1 << (irq - 1);
	crime->imask = crime_mask;
}

static void disable_mace_irq(unsigned int irq)
{
	crime_mask &= ~(1 << (irq - 1));
	crime->imask = crime_mask;
	flush_crime_bus();
}

static void end_mace_irq(unsigned int irq)
{
	if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
		enable_mace_irq(irq);
}

static struct irq_chip ip32_mace_interrupt = {
	.name = "IP32 MACE",
	.ack = disable_mace_irq,
	.mask = disable_mace_irq,
	.mask_ack = disable_mace_irq,
	.unmask = enable_mace_irq,
	.end = end_mace_irq,
};

static void ip32_unknown_interrupt(void)
{
	printk ("Unknown interrupt occurred!\n");
	printk ("cp0_status: %08x\n", read_c0_status());
	printk ("cp0_cause: %08x\n", read_c0_cause());
	printk ("CRIME intr mask: %016lx\n", crime->imask);
	printk ("CRIME intr status: %016lx\n", crime->istat);
	printk ("CRIME hardware intr register: %016lx\n", crime->hard_int);
	printk ("MACE ISA intr mask: %08lx\n", mace->perif.ctrl.imask);
	printk ("MACE ISA intr status: %08lx\n", mace->perif.ctrl.istat);
	printk ("MACE PCI control register: %08x\n", mace->pci.control);

	printk("Register dump:\n");
	show_regs(get_irq_regs());

	printk("Please mail this report to linux-mips@linux-mips.org\n");
	printk("Spinning...");
	while(1) ;
}

/* CRIME 1.1 appears to deliver all interrupts to this one pin. */
/* change this to loop over all edge-triggered irqs, exception masked out ones */
static void ip32_irq0(void)
{
	uint64_t crime_int;
	int irq = 0;

	crime_int = crime->istat & crime_mask;
	irq = __ffs(crime_int);
	crime_int = 1 << irq;

	if (crime_int & CRIME_MACEISA_INT_MASK) {
		unsigned long mace_int = mace->perif.ctrl.istat;
		irq = __ffs(mace_int & maceisa_mask) + 32;
	}
	irq++;
	DBG("*irq %u*\n", irq);
	do_IRQ(irq);
}

static void ip32_irq1(void)
{
	ip32_unknown_interrupt();
}

static void ip32_irq2(void)
{
	ip32_unknown_interrupt();
}

static void ip32_irq3(void)
{
	ip32_unknown_interrupt();
}

static void ip32_irq4(void)
{
	ip32_unknown_interrupt();
}

static void ip32_irq5(void)
{
	ll_timer_interrupt(IP32_R4K_TIMER_IRQ);
}

asmlinkage void plat_irq_dispatch(void)
{
	unsigned int pending = read_c0_status() & read_c0_cause();

	if (likely(pending & IE_IRQ0))
		ip32_irq0();
	else if (unlikely(pending & IE_IRQ1))
		ip32_irq1();
	else if (unlikely(pending & IE_IRQ2))
		ip32_irq2();
	else if (unlikely(pending & IE_IRQ3))
		ip32_irq3();
	else if (unlikely(pending & IE_IRQ4))
		ip32_irq4();
	else if (likely(pending & IE_IRQ5))
		ip32_irq5();
}

void __init arch_init_irq(void)
{
	unsigned int irq;

	/* Install our interrupt handler, then clear and disable all
	 * CRIME and MACE interrupts. */
	crime->imask = 0;
	crime->hard_int = 0;
	crime->soft_int = 0;
	mace->perif.ctrl.istat = 0;
	mace->perif.ctrl.imask = 0;

	for (irq = 0; irq <= IP32_IRQ_MAX; irq++) {
		struct irq_chip *controller;

		if (irq == IP32_R4K_TIMER_IRQ)
			controller = &ip32_cpu_interrupt;
		else if (irq <= MACE_PCI_BRIDGE_IRQ && irq >= MACE_VID_IN1_IRQ)
			controller = &ip32_mace_interrupt;
		else if (irq <= MACEPCI_SHARED2_IRQ && irq >= MACEPCI_SCSI0_IRQ)
			controller = &ip32_macepci_interrupt;
		else if (irq <= CRIME_VICE_IRQ && irq >= CRIME_GBE0_IRQ)
			controller = &ip32_crime_interrupt;
		else
			controller = &ip32_maceisa_interrupt;

		set_irq_chip(irq, controller);
	}
	setup_irq(CRIME_MEMERR_IRQ, &memerr_irq);
	setup_irq(CRIME_CPUERR_IRQ, &cpuerr_irq);

#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
	change_c0_status(ST0_IM, ALLINTS);
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Code to handle IP32 IRQs
	3	*
	4	* This file is subject to the terms and conditions of the GNU General Public
	5	* License. See the file "COPYING" in the main directory of this archive
	6	* for more details.
	7	*
	8	* Copyright (C) 2000 Harald Koerfgen
	9	* Copyright (C) 2001 Keith M Wesolowski
	10	*/
	11	#include <linux/init.h>
	12	#include <linux/kernel_stat.h>
	13	#include <linux/types.h>
	14	#include <linux/interrupt.h>
	15	#include <linux/irq.h>
	16	#include <linux/bitops.h>
	17	#include <linux/kernel.h>
	18	#include <linux/slab.h>
	19	#include <linux/mm.h>
	20	#include <linux/random.h>
	21	#include <linux/sched.h>
	22
	23	#include <asm/mipsregs.h>
	24	#include <asm/signal.h>
	25	#include <asm/system.h>
	26	#include <asm/time.h>
	27	#include <asm/ip32/crime.h>
	28	#include <asm/ip32/mace.h>
	29	#include <asm/ip32/ip32_ints.h>
	30
	31	/* issue a PIO read to make sure no PIO writes are pending */
	32	static void inline flush_crime_bus(void)
	33	{
b6d7c7a9	34	crime->control;
1da177e4 LT	35	}
	36
	37	static void inline flush_mace_bus(void)
	38	{
b6d7c7a9	39	mace->perif.ctrl.misc;
1da177e4 LT	40	}
	41
	42	#undef DEBUG_IRQ
	43	#ifdef DEBUG_IRQ
	44	#define DBG(x...) printk(x)
	45	#else
	46	#define DBG(x...)
	47	#endif
	48
	49	/* O2 irq map
	50	*
	51	* IP0 -> software (ignored)
	52	* IP1 -> software (ignored)
	53	* IP2 -> (irq0) C crime 1.1 all interrupts; crime 1.5 ???
	54	* IP3 -> (irq1) X unknown
	55	* IP4 -> (irq2) X unknown
	56	* IP5 -> (irq3) X unknown
	57	* IP6 -> (irq4) X unknown
	58	* IP7 -> (irq5) 0 CPU count/compare timer (system timer)
	59	*
	60	* crime: (C)
	61	*
	62	* CRIME_INT_STAT 31:0:
	63	*
	64	* 0 -> 1 Video in 1
	65	* 1 -> 2 Video in 2
	66	* 2 -> 3 Video out
	67	* 3 -> 4 Mace ethernet
	68	* 4 -> S SuperIO sub-interrupt
	69	* 5 -> M Miscellaneous sub-interrupt
	70	* 6 -> A Audio sub-interrupt
	71	* 7 -> 8 PCI bridge errors
	72	* 8 -> 9 PCI SCSI aic7xxx 0
	73	* 9 -> 10 PCI SCSI aic7xxx 1
	74	* 10 -> 11 PCI slot 0
	75	* 11 -> 12 unused (PCI slot 1)
	76	* 12 -> 13 unused (PCI slot 2)
	77	* 13 -> 14 unused (PCI shared 0)
	78	* 14 -> 15 unused (PCI shared 1)
	79	* 15 -> 16 unused (PCI shared 2)
	80	* 16 -> 17 GBE0 (E)
	81	* 17 -> 18 GBE1 (E)
	82	* 18 -> 19 GBE2 (E)
	83	* 19 -> 20 GBE3 (E)
	84	* 20 -> 21 CPU errors
	85	* 21 -> 22 Memory errors
	86	* 22 -> 23 RE empty edge (E)
	87	* 23 -> 24 RE full edge (E)
	88	* 24 -> 25 RE idle edge (E)
	89	* 25 -> 26 RE empty level
	90	* 26 -> 27 RE full level
	91	* 27 -> 28 RE idle level
	92	* 28 -> 29 unused (software 0) (E)
	93	* 29 -> 30 unused (software 1) (E)
	94	* 30 -> 31 unused (software 2) - crime 1.5 CPU SysCorError (E)
	95	* 31 -> 32 VICE
	96	*
	97	* S, M, A: Use the MACE ISA interrupt register
	98	* MACE_ISA_INT_STAT 31:0
	99	*
	100	* 0-7 -> 33-40 Audio
	101	* 8 -> 41 RTC
	102	* 9 -> 42 Keyboard
	103	* 10 -> X Keyboard polled
104	* 11 -> 44 Mouse
105	* 12 -> X Mouse polled
106	* 13-15 -> 46-48 Count/compare timers
107	* 16-19 -> 49-52 Parallel (16 E)
108	* 20-25 -> 53-58 Serial 1 (22 E)
109	* 26-31 -> 59-64 Serial 2 (28 E)
110	*
111	* Note that this means IRQs 5-7, 43, and 45 do not exist. This is a
112	* different IRQ map than IRIX uses, but that's OK as Linux irq handling
113	* is quite different anyway.
114	*/
115
1da177e4	116	/* Some initial interrupts to set up */
937a8015 RB	117	extern irqreturn_t crime_memerr_intr(int irq, void *dev_id);
937a8015 RB	118	extern irqreturn_t crime_cpuerr_intr(int irq, void *dev_id);
1da177e4	119
f40298fd	120	struct irqaction memerr_irq = { crime_memerr_intr, IRQF_DISABLED,
1da177e4	121	CPU_MASK_NONE, "CRIME memory error", NULL, NULL };
f40298fd	122	struct irqaction cpuerr_irq = { crime_cpuerr_intr, IRQF_DISABLED,
1da177e4 LT	123	CPU_MASK_NONE, "CRIME CPU error", NULL, NULL };
1da177e4 LT	124
1da177e4 LT	125	/*
	126	* For interrupts wired from a single device to the CPU. Only the clock
	127	* uses this it seems, which is IRQ 0 and IP7.
	128	*/
	129
	130	static void enable_cpu_irq(unsigned int irq)
	131	{
	132	set_c0_status(STATUSF_IP7);
	133	}
	134
1da177e4 LT	135	static void disable_cpu_irq(unsigned int irq)
	136	{
	137	clear_c0_status(STATUSF_IP7);
	138	}
	139
	140	static void end_cpu_irq(unsigned int irq)
	141	{
	142	if (!(irq_desc[irq].status & (IRQ_DISABLED \| IRQ_INPROGRESS)))
	143	enable_cpu_irq (irq);
	144	}
	145
94dee171	146	static struct irq_chip ip32_cpu_interrupt = {
70d21cde	147	.name = "IP32 CPU",
1603b5ac AN	148	.ack = disable_cpu_irq,
	149	.mask = disable_cpu_irq,
	150	.mask_ack = disable_cpu_irq,
	151	.unmask = enable_cpu_irq,
8ab00b9a	152	.end = end_cpu_irq,
1da177e4 LT	153	};
	154
	155	/*
	156	* This is for pure CRIME interrupts - ie not MACE. The advantage?
	157	* We get to split the register in half and do faster lookups.
	158	*/
	159
	160	static uint64_t crime_mask;
	161
	162	static void enable_crime_irq(unsigned int irq)
	163	{
1da177e4 LT	164	crime_mask \|= 1 << (irq - 1);
1da177e4 LT	165	crime->imask = crime_mask;
1da177e4 LT	166	}
	167
	168	static void disable_crime_irq(unsigned int irq)
	169	{
1da177e4 LT	170	crime_mask &= ~(1 << (irq - 1));
	171	crime->imask = crime_mask;
	172	flush_crime_bus();
1da177e4 LT	173	}
	174
	175	static void mask_and_ack_crime_irq(unsigned int irq)
	176	{
1da177e4 LT	177	/* Edge triggered interrupts must be cleared. */
	178	if ((irq >= CRIME_GBE0_IRQ && irq <= CRIME_GBE3_IRQ)
	179	\|\| (irq >= CRIME_RE_EMPTY_E_IRQ && irq <= CRIME_RE_IDLE_E_IRQ)
	180	\|\| (irq >= CRIME_SOFT0_IRQ && irq <= CRIME_SOFT2_IRQ)) {
	181	uint64_t crime_int;
1da177e4 LT	182	crime_int = crime->hard_int;
	183	crime_int &= ~(1 << (irq - 1));
	184	crime->hard_int = crime_int;
1da177e4 LT	185	}
	186	disable_crime_irq(irq);
	187	}
	188
	189	static void end_crime_irq(unsigned int irq)
	190	{
	191	if (!(irq_desc[irq].status & (IRQ_DISABLED \| IRQ_INPROGRESS)))
	192	enable_crime_irq(irq);
	193	}
	194
94dee171	195	static struct irq_chip ip32_crime_interrupt = {
70d21cde	196	.name = "IP32 CRIME",
8ab00b9a	197	.ack = mask_and_ack_crime_irq,
1603b5ac AN	198	.mask = disable_crime_irq,
	199	.mask_ack = mask_and_ack_crime_irq,
	200	.unmask = enable_crime_irq,
8ab00b9a	201	.end = end_crime_irq,
1da177e4 LT	202	};
	203
	204	/*
	205	* This is for MACE PCI interrupts. We can decrease bus traffic by masking
	206	* as close to the source as possible. This also means we can take the
	207	* next chunk of the CRIME register in one piece.
	208	*/
	209
	210	static unsigned long macepci_mask;
	211
	212	static void enable_macepci_irq(unsigned int irq)
	213	{
1da177e4 LT	214	macepci_mask \|= MACEPCI_CONTROL_INT(irq - 9);
	215	mace->pci.control = macepci_mask;
	216	crime_mask \|= 1 << (irq - 1);
	217	crime->imask = crime_mask;
1da177e4 LT	218	}
	219
	220	static void disable_macepci_irq(unsigned int irq)
	221	{
1da177e4 LT	222	crime_mask &= ~(1 << (irq - 1));
	223	crime->imask = crime_mask;
	224	flush_crime_bus();
	225	macepci_mask &= ~MACEPCI_CONTROL_INT(irq - 9);
	226	mace->pci.control = macepci_mask;
	227	flush_mace_bus();
1da177e4 LT	228	}
	229
	230	static void end_macepci_irq(unsigned int irq)
	231	{
	232	if (!(irq_desc[irq].status & (IRQ_DISABLED\|IRQ_INPROGRESS)))
	233	enable_macepci_irq(irq);
	234	}
	235
94dee171	236	static struct irq_chip ip32_macepci_interrupt = {
70d21cde	237	.name = "IP32 MACE PCI",
1603b5ac AN	238	.ack = disable_macepci_irq,
	239	.mask = disable_macepci_irq,
	240	.mask_ack = disable_macepci_irq,
	241	.unmask = enable_macepci_irq,
8ab00b9a	242	.end = end_macepci_irq,
1da177e4 LT	243	};
	244
	245	/* This is used for MACE ISA interrupts. That means bits 4-6 in the
	246	* CRIME register.
	247	*/
	248
	249	#define MACEISA_AUDIO_INT (MACEISA_AUDIO_SW_INT \| \
	250	MACEISA_AUDIO_SC_INT \| \
	251	MACEISA_AUDIO1_DMAT_INT \| \
	252	MACEISA_AUDIO1_OF_INT \| \
	253	MACEISA_AUDIO2_DMAT_INT \| \
	254	MACEISA_AUDIO2_MERR_INT \| \
	255	MACEISA_AUDIO3_DMAT_INT \| \
	256	MACEISA_AUDIO3_MERR_INT)
	257	#define MACEISA_MISC_INT (MACEISA_RTC_INT \| \
	258	MACEISA_KEYB_INT \| \
	259	MACEISA_KEYB_POLL_INT \| \
	260	MACEISA_MOUSE_INT \| \
	261	MACEISA_MOUSE_POLL_INT \| \
cfbae5d3 TS	262	MACEISA_TIMER0_INT \| \
	263	MACEISA_TIMER1_INT \| \
	264	MACEISA_TIMER2_INT)
1da177e4 LT	265	#define MACEISA_SUPERIO_INT (MACEISA_PARALLEL_INT \| \
	266	MACEISA_PAR_CTXA_INT \| \
	267	MACEISA_PAR_CTXB_INT \| \
	268	MACEISA_PAR_MERR_INT \| \
	269	MACEISA_SERIAL1_INT \| \
	270	MACEISA_SERIAL1_TDMAT_INT \| \
	271	MACEISA_SERIAL1_TDMAPR_INT \| \
	272	MACEISA_SERIAL1_TDMAME_INT \| \
	273	MACEISA_SERIAL1_RDMAT_INT \| \
	274	MACEISA_SERIAL1_RDMAOR_INT \| \
	275	MACEISA_SERIAL2_INT \| \
	276	MACEISA_SERIAL2_TDMAT_INT \| \
	277	MACEISA_SERIAL2_TDMAPR_INT \| \
	278	MACEISA_SERIAL2_TDMAME_INT \| \
	279	MACEISA_SERIAL2_RDMAT_INT \| \
	280	MACEISA_SERIAL2_RDMAOR_INT)
	281
	282	static unsigned long maceisa_mask;
	283
	284	static void enable_maceisa_irq (unsigned int irq)
	285	{
	286	unsigned int crime_int = 0;
1da177e4 LT	287
	288	DBG ("maceisa enable: %u\n", irq);
	289
	290	switch (irq) {
	291	case MACEISA_AUDIO_SW_IRQ ... MACEISA_AUDIO3_MERR_IRQ:
	292	crime_int = MACE_AUDIO_INT;
	293	break;
cfbae5d3	294	case MACEISA_RTC_IRQ ... MACEISA_TIMER2_IRQ:
1da177e4 LT	295	crime_int = MACE_MISC_INT;
	296	break;
	297	case MACEISA_PARALLEL_IRQ ... MACEISA_SERIAL2_RDMAOR_IRQ:
	298	crime_int = MACE_SUPERIO_INT;
	299	break;
	300	}
	301	DBG ("crime_int %08x enabled\n", crime_int);
1da177e4 LT	302	crime_mask \|= crime_int;
	303	crime->imask = crime_mask;
	304	maceisa_mask \|= 1 << (irq - 33);
	305	mace->perif.ctrl.imask = maceisa_mask;
1da177e4 LT	306	}
	307
	308	static void disable_maceisa_irq(unsigned int irq)
	309	{
	310	unsigned int crime_int = 0;
1da177e4	311
1da177e4 LT	312	maceisa_mask &= ~(1 << (irq - 33));
	313	if(!(maceisa_mask & MACEISA_AUDIO_INT))
	314	crime_int \|= MACE_AUDIO_INT;
	315	if(!(maceisa_mask & MACEISA_MISC_INT))
	316	crime_int \|= MACE_MISC_INT;
	317	if(!(maceisa_mask & MACEISA_SUPERIO_INT))
	318	crime_int \|= MACE_SUPERIO_INT;
	319	crime_mask &= ~crime_int;
	320	crime->imask = crime_mask;
	321	flush_crime_bus();
	322	mace->perif.ctrl.imask = maceisa_mask;
	323	flush_mace_bus();
1da177e4 LT	324	}
	325
	326	static void mask_and_ack_maceisa_irq(unsigned int irq)
	327	{
1603b5ac	328	unsigned long mace_int;
1da177e4 LT	329
	330	switch (irq) {
	331	case MACEISA_PARALLEL_IRQ:
	332	case MACEISA_SERIAL1_TDMAPR_IRQ:
	333	case MACEISA_SERIAL2_TDMAPR_IRQ:
	334	/* edge triggered */
1da177e4 LT	335	mace_int = mace->perif.ctrl.istat;
	336	mace_int &= ~(1 << (irq - 33));
	337	mace->perif.ctrl.istat = mace_int;
1da177e4 LT	338	break;
	339	}
	340	disable_maceisa_irq(irq);
	341	}
	342
	343	static void end_maceisa_irq(unsigned irq)
	344	{
	345	if (!(irq_desc[irq].status & (IRQ_DISABLED \| IRQ_INPROGRESS)))
	346	enable_maceisa_irq(irq);
	347	}
	348
94dee171	349	static struct irq_chip ip32_maceisa_interrupt = {
70d21cde	350	.name = "IP32 MACE ISA",
8ab00b9a	351	.ack = mask_and_ack_maceisa_irq,
1603b5ac AN	352	.mask = disable_maceisa_irq,
	353	.mask_ack = mask_and_ack_maceisa_irq,
	354	.unmask = enable_maceisa_irq,
8ab00b9a	355	.end = end_maceisa_irq,
1da177e4 LT	356	};
	357
	358	/* This is used for regular non-ISA, non-PCI MACE interrupts. That means
	359	* bits 0-3 and 7 in the CRIME register.
	360	*/
	361
	362	static void enable_mace_irq(unsigned int irq)
	363	{
1da177e4 LT	364	crime_mask \|= 1 << (irq - 1);
1da177e4 LT	365	crime->imask = crime_mask;
1da177e4 LT	366	}
	367
	368	static void disable_mace_irq(unsigned int irq)
	369	{
1da177e4 LT	370	crime_mask &= ~(1 << (irq - 1));
	371	crime->imask = crime_mask;
	372	flush_crime_bus();
1da177e4 LT	373	}
	374
	375	static void end_mace_irq(unsigned int irq)
	376	{
	377	if (!(irq_desc[irq].status & (IRQ_DISABLED\|IRQ_INPROGRESS)))
	378	enable_mace_irq(irq);
	379	}
	380
94dee171	381	static struct irq_chip ip32_mace_interrupt = {
70d21cde	382	.name = "IP32 MACE",
1603b5ac AN	383	.ack = disable_mace_irq,
	384	.mask = disable_mace_irq,
	385	.mask_ack = disable_mace_irq,
	386	.unmask = enable_mace_irq,
8ab00b9a	387	.end = end_mace_irq,
1da177e4 LT	388	};
1da177e4 LT	389
937a8015	390	static void ip32_unknown_interrupt(void)
1da177e4 LT	391	{
	392	printk ("Unknown interrupt occurred!\n");
	393	printk ("cp0_status: %08x\n", read_c0_status());
	394	printk ("cp0_cause: %08x\n", read_c0_cause());
	395	printk ("CRIME intr mask: %016lx\n", crime->imask);
	396	printk ("CRIME intr status: %016lx\n", crime->istat);
	397	printk ("CRIME hardware intr register: %016lx\n", crime->hard_int);
	398	printk ("MACE ISA intr mask: %08lx\n", mace->perif.ctrl.imask);
	399	printk ("MACE ISA intr status: %08lx\n", mace->perif.ctrl.istat);
	400	printk ("MACE PCI control register: %08x\n", mace->pci.control);
	401
	402	printk("Register dump:\n");
937a8015	403	show_regs(get_irq_regs());
1da177e4 LT	404
	405	printk("Please mail this report to linux-mips@linux-mips.org\n");
	406	printk("Spinning...");
	407	while(1) ;
	408	}
	409
	410	/* CRIME 1.1 appears to deliver all interrupts to this one pin. */
	411	/* change this to loop over all edge-triggered irqs, exception masked out ones */
937a8015	412	static void ip32_irq0(void)
1da177e4 LT	413	{
	414	uint64_t crime_int;
	415	int irq = 0;
	416
	417	crime_int = crime->istat & crime_mask;
6f8782c4 AN	418	irq = __ffs(crime_int);
6f8782c4 AN	419	crime_int = 1 << irq;
1da177e4 LT	420
	421	if (crime_int & CRIME_MACEISA_INT_MASK) {
	422	unsigned long mace_int = mace->perif.ctrl.istat;
6f8782c4	423	irq = __ffs(mace_int & maceisa_mask) + 32;
1da177e4	424	}
6f8782c4	425	irq++;
1da177e4	426	DBG("irq %u\n", irq);
937a8015	427	do_IRQ(irq);
1da177e4 LT	428	}
1da177e4 LT	429
937a8015	430	static void ip32_irq1(void)
1da177e4	431	{
937a8015	432	ip32_unknown_interrupt();
1da177e4 LT	433	}
1da177e4 LT	434
937a8015	435	static void ip32_irq2(void)
1da177e4	436	{
937a8015	437	ip32_unknown_interrupt();
1da177e4 LT	438	}
1da177e4 LT	439
937a8015	440	static void ip32_irq3(void)
1da177e4	441	{
937a8015	442	ip32_unknown_interrupt();
1da177e4 LT	443	}
1da177e4 LT	444
937a8015	445	static void ip32_irq4(void)
1da177e4	446	{
937a8015	447	ip32_unknown_interrupt();
1da177e4 LT	448	}
1da177e4 LT	449
937a8015	450	static void ip32_irq5(void)
1da177e4	451	{
937a8015	452	ll_timer_interrupt(IP32_R4K_TIMER_IRQ);
1da177e4 LT	453	}
1da177e4 LT	454
937a8015	455	asmlinkage void plat_irq_dispatch(void)
e4ac58af	456	{
119537c0	457	unsigned int pending = read_c0_status() & read_c0_cause();
e4ac58af RB	458
e4ac58af RB	459	if (likely(pending & IE_IRQ0))
937a8015	460	ip32_irq0();
e4ac58af	461	else if (unlikely(pending & IE_IRQ1))
937a8015	462	ip32_irq1();
e4ac58af	463	else if (unlikely(pending & IE_IRQ2))
937a8015	464	ip32_irq2();
e4ac58af	465	else if (unlikely(pending & IE_IRQ3))
937a8015	466	ip32_irq3();
e4ac58af	467	else if (unlikely(pending & IE_IRQ4))
937a8015	468	ip32_irq4();
e4ac58af	469	else if (likely(pending & IE_IRQ5))
937a8015	470	ip32_irq5();
e4ac58af RB	471	}
e4ac58af RB	472
1da177e4 LT	473	void __init arch_init_irq(void)
	474	{
	475	unsigned int irq;
	476
	477	/* Install our interrupt handler, then clear and disable all
	478	* CRIME and MACE interrupts. */
	479	crime->imask = 0;
	480	crime->hard_int = 0;
	481	crime->soft_int = 0;
	482	mace->perif.ctrl.istat = 0;
	483	mace->perif.ctrl.imask = 0;
1da177e4 LT	484
1da177e4 LT	485	for (irq = 0; irq <= IP32_IRQ_MAX; irq++) {
94dee171	486	struct irq_chip *controller;
1da177e4 LT	487
	488	if (irq == IP32_R4K_TIMER_IRQ)
	489	controller = &ip32_cpu_interrupt;
	490	else if (irq <= MACE_PCI_BRIDGE_IRQ && irq >= MACE_VID_IN1_IRQ)
	491	controller = &ip32_mace_interrupt;
	492	else if (irq <= MACEPCI_SHARED2_IRQ && irq >= MACEPCI_SCSI0_IRQ)
	493	controller = &ip32_macepci_interrupt;
	494	else if (irq <= CRIME_VICE_IRQ && irq >= CRIME_GBE0_IRQ)
	495	controller = &ip32_crime_interrupt;
	496	else
	497	controller = &ip32_maceisa_interrupt;
	498
1603b5ac	499	set_irq_chip(irq, controller);
1da177e4 LT	500	}
	501	setup_irq(CRIME_MEMERR_IRQ, &memerr_irq);
	502	setup_irq(CRIME_CPUERR_IRQ, &cpuerr_irq);
	503
	504	#define ALLINTS (IE_IRQ0 \| IE_IRQ1 \| IE_IRQ2 \| IE_IRQ3 \| IE_IRQ4 \| IE_IRQ5)
	505	change_c0_status(ST0_IM, ALLINTS);
	506	}