[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / mips / sgi-ip27 / ip27-irq.c

/*
 * ip27-irq.c: Highlevel interrupt handling for IP27 architecture.
 *
 * Copyright (C) 1999, 2000 Ralf Baechle (ralf@gnu.org)
 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
 * Copyright (C) 1999 - 2001 Kanoj Sarcar
 */

#undef DEBUG

#include <linux/init.h>
#include <linux/irq.h>
#include <linux/errno.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/timex.h>
#include <linux/smp.h>
#include <linux/random.h>
#include <linux/kernel.h>
#include <linux/kernel_stat.h>
#include <linux/delay.h>
#include <linux/bitops.h>

#include <asm/bootinfo.h>
#include <asm/io.h>
#include <asm/mipsregs.h>
#include <asm/system.h>

#include <asm/processor.h>
#include <asm/pci/bridge.h>
#include <asm/sn/addrs.h>
#include <asm/sn/agent.h>
#include <asm/sn/arch.h>
#include <asm/sn/hub.h>
#include <asm/sn/intr.h>

/*
 * Linux has a controller-independent x86 interrupt architecture.
 * every controller has a 'controller-template', that is used
 * by the main code to do the right thing. Each driver-visible
 * interrupt source is transparently wired to the appropriate
 * controller. Thus drivers need not be aware of the
 * interrupt-controller.
 *
 * Various interrupt controllers we handle: 8259 PIC, SMP IO-APIC,
 * PIIX4's internal 8259 PIC and SGI's Visual Workstation Cobalt (IO-)APIC.
 * (IO-APICs assumed to be messaging to Pentium local-APICs)
 *
 * the code is designed to be easily extended with new/different
 * interrupt controllers, without having to do assembly magic.
 */

extern asmlinkage void ip27_irq(void);

extern struct bridge_controller *irq_to_bridge[];
extern int irq_to_slot[];

/*
 * use these macros to get the encoded nasid and widget id
 * from the irq value
 */
#define IRQ_TO_BRIDGE(i)		irq_to_bridge[(i)]
#define	SLOT_FROM_PCI_IRQ(i)		irq_to_slot[i]

static inline int alloc_level(int cpu, int irq)
{
	struct hub_data *hub = hub_data(cpu_to_node(cpu));
	struct slice_data *si = cpu_data[cpu].data;
	int level;

	level = find_first_zero_bit(hub->irq_alloc_mask, LEVELS_PER_SLICE);
	if (level >= LEVELS_PER_SLICE)
		panic("Cpu %d flooded with devices\n", cpu);

	__set_bit(level, hub->irq_alloc_mask);
	si->level_to_irq[level] = irq;

	return level;
}

static inline int find_level(cpuid_t *cpunum, int irq)
{
	int cpu, i;

	for_each_online_cpu(cpu) {
		struct slice_data *si = cpu_data[cpu].data;

		for (i = BASE_PCI_IRQ; i < LEVELS_PER_SLICE; i++)
			if (si->level_to_irq[i] == irq) {
				*cpunum = cpu;

				return i;
			}
	}

	panic("Could not identify cpu/level for irq %d\n", irq);
}

/*
 * Find first bit set
 */
static int ms1bit(unsigned long x)
{
	int b = 0, s;

	s = 16; if (x >> 16 == 0) s = 0; b += s; x >>= s;
	s =  8; if (x >>  8 == 0) s = 0; b += s; x >>= s;
	s =  4; if (x >>  4 == 0) s = 0; b += s; x >>= s;
	s =  2; if (x >>  2 == 0) s = 0; b += s; x >>= s;
	s =  1; if (x >>  1 == 0) s = 0; b += s;

	return b;
}

/*
 * This code is unnecessarily complex, because we do IRQF_DISABLED
 * intr enabling. Basically, once we grab the set of intrs we need
 * to service, we must mask _all_ these interrupts; firstly, to make
 * sure the same intr does not intr again, causing recursion that
 * can lead to stack overflow. Secondly, we can not just mask the
 * one intr we are do_IRQing, because the non-masked intrs in the
 * first set might intr again, causing multiple servicings of the
 * same intr. This effect is mostly seen for intercpu intrs.
 * Kanoj 05.13.00
 */

static void ip27_do_irq_mask0(void)
{
	int irq, swlevel;
	hubreg_t pend0, mask0;
	cpuid_t cpu = smp_processor_id();
	int pi_int_mask0 =
		(cputoslice(cpu) == 0) ?  PI_INT_MASK0_A : PI_INT_MASK0_B;

	/* copied from Irix intpend0() */
	pend0 = LOCAL_HUB_L(PI_INT_PEND0);
	mask0 = LOCAL_HUB_L(pi_int_mask0);

	pend0 &= mask0;		/* Pick intrs we should look at */
	if (!pend0)
		return;

	swlevel = ms1bit(pend0);
#ifdef CONFIG_SMP
	if (pend0 & (1UL << CPU_RESCHED_A_IRQ)) {
		LOCAL_HUB_CLR_INTR(CPU_RESCHED_A_IRQ);
	} else if (pend0 & (1UL << CPU_RESCHED_B_IRQ)) {
		LOCAL_HUB_CLR_INTR(CPU_RESCHED_B_IRQ);
	} else if (pend0 & (1UL << CPU_CALL_A_IRQ)) {
		LOCAL_HUB_CLR_INTR(CPU_CALL_A_IRQ);
		smp_call_function_interrupt();
	} else if (pend0 & (1UL << CPU_CALL_B_IRQ)) {
		LOCAL_HUB_CLR_INTR(CPU_CALL_B_IRQ);
		smp_call_function_interrupt();
	} else
#endif
	{
		/* "map" swlevel to irq */
		struct slice_data *si = cpu_data[cpu].data;

		irq = si->level_to_irq[swlevel];
		do_IRQ(irq);
	}

	LOCAL_HUB_L(PI_INT_PEND0);
}

static void ip27_do_irq_mask1(void)
{
	int irq, swlevel;
	hubreg_t pend1, mask1;
	cpuid_t cpu = smp_processor_id();
	int pi_int_mask1 = (cputoslice(cpu) == 0) ?  PI_INT_MASK1_A : PI_INT_MASK1_B;
	struct slice_data *si = cpu_data[cpu].data;

	/* copied from Irix intpend0() */
	pend1 = LOCAL_HUB_L(PI_INT_PEND1);
	mask1 = LOCAL_HUB_L(pi_int_mask1);

	pend1 &= mask1;		/* Pick intrs we should look at */
	if (!pend1)
		return;

	swlevel = ms1bit(pend1);
	/* "map" swlevel to irq */
	irq = si->level_to_irq[swlevel];
	LOCAL_HUB_CLR_INTR(swlevel);
	do_IRQ(irq);

	LOCAL_HUB_L(PI_INT_PEND1);
}

static void ip27_prof_timer(void)
{
	panic("CPU %d got a profiling interrupt", smp_processor_id());
}

static void ip27_hub_error(void)
{
	panic("CPU %d got a hub error interrupt", smp_processor_id());
}

static int intr_connect_level(int cpu, int bit)
{
	nasid_t nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu));
	struct slice_data *si = cpu_data[cpu].data;

	set_bit(bit, si->irq_enable_mask);

	if (!cputoslice(cpu)) {
		REMOTE_HUB_S(nasid, PI_INT_MASK0_A, si->irq_enable_mask[0]);
		REMOTE_HUB_S(nasid, PI_INT_MASK1_A, si->irq_enable_mask[1]);
	} else {
		REMOTE_HUB_S(nasid, PI_INT_MASK0_B, si->irq_enable_mask[0]);
		REMOTE_HUB_S(nasid, PI_INT_MASK1_B, si->irq_enable_mask[1]);
	}

	return 0;
}

static int intr_disconnect_level(int cpu, int bit)
{
	nasid_t nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu));
	struct slice_data *si = cpu_data[cpu].data;

	clear_bit(bit, si->irq_enable_mask);

	if (!cputoslice(cpu)) {
		REMOTE_HUB_S(nasid, PI_INT_MASK0_A, si->irq_enable_mask[0]);
		REMOTE_HUB_S(nasid, PI_INT_MASK1_A, si->irq_enable_mask[1]);
	} else {
		REMOTE_HUB_S(nasid, PI_INT_MASK0_B, si->irq_enable_mask[0]);
		REMOTE_HUB_S(nasid, PI_INT_MASK1_B, si->irq_enable_mask[1]);
	}

	return 0;
}

/* Startup one of the (PCI ...) IRQs routes over a bridge.  */
static unsigned int startup_bridge_irq(struct irq_data *d)
{
	struct bridge_controller *bc;
	bridgereg_t device;
	bridge_t *bridge;
	int pin, swlevel;
	cpuid_t cpu;

	pin = SLOT_FROM_PCI_IRQ(d->irq);
	bc = IRQ_TO_BRIDGE(d->irq);
	bridge = bc->base;

	pr_debug("bridge_startup(): irq= 0x%x  pin=%d\n", d->irq, pin);
	/*
	 * "map" irq to a swlevel greater than 6 since the first 6 bits
	 * of INT_PEND0 are taken
	 */
	swlevel = find_level(&cpu, d->irq);
	bridge->b_int_addr[pin].addr = (0x20000 | swlevel | (bc->nasid << 8));
	bridge->b_int_enable |= (1 << pin);
	bridge->b_int_enable |= 0x7ffffe00;	/* more stuff in int_enable */

	/*
	 * Enable sending of an interrupt clear packt to the hub on a high to
	 * low transition of the interrupt pin.
	 *
	 * IRIX sets additional bits in the address which are documented as
	 * reserved in the bridge docs.
	 */
	bridge->b_int_mode |= (1UL << pin);

	/*
	 * We assume the bridge to have a 1:1 mapping between devices
	 * (slots) and intr pins.
	 */
	device = bridge->b_int_device;
	device &= ~(7 << (pin*3));
	device |= (pin << (pin*3));
	bridge->b_int_device = device;

        bridge->b_wid_tflush;

	intr_connect_level(cpu, swlevel);

        return 0;       /* Never anything pending.  */
}

/* Shutdown one of the (PCI ...) IRQs routes over a bridge.  */
static void shutdown_bridge_irq(struct irq_data *d)
{
	struct bridge_controller *bc = IRQ_TO_BRIDGE(d->irq);
	bridge_t *bridge = bc->base;
	int pin, swlevel;
	cpuid_t cpu;

	pr_debug("bridge_shutdown: irq 0x%x\n", d->irq);
	pin = SLOT_FROM_PCI_IRQ(d->irq);

	/*
	 * map irq to a swlevel greater than 6 since the first 6 bits
	 * of INT_PEND0 are taken
	 */
	swlevel = find_level(&cpu, d->irq);
	intr_disconnect_level(cpu, swlevel);

	bridge->b_int_enable &= ~(1 << pin);
	bridge->b_wid_tflush;
}

static inline void enable_bridge_irq(struct irq_data *d)
{
	cpuid_t cpu;
	int swlevel;

	swlevel = find_level(&cpu, d->irq);	/* Criminal offence */
	intr_connect_level(cpu, swlevel);
}

static inline void disable_bridge_irq(struct irq_data *d)
{
	cpuid_t cpu;
	int swlevel;

	swlevel = find_level(&cpu, d->irq);	/* Criminal offence */
	intr_disconnect_level(cpu, swlevel);
}

static struct irq_chip bridge_irq_type = {
	.name		= "bridge",
	.irq_startup	= startup_bridge_irq,
	.irq_shutdown	= shutdown_bridge_irq,
	.irq_mask	= disable_bridge_irq,
	.irq_unmask	= enable_bridge_irq,
};

void __devinit register_bridge_irq(unsigned int irq)
{
	irq_set_chip_and_handler(irq, &bridge_irq_type, handle_level_irq);
}

int __devinit request_bridge_irq(struct bridge_controller *bc)
{
	int irq = allocate_irqno();
	int swlevel, cpu;
	nasid_t nasid;

	if (irq < 0)
		return irq;

	/*
	 * "map" irq to a swlevel greater than 6 since the first 6 bits
	 * of INT_PEND0 are taken
	 */
	cpu = bc->irq_cpu;
	swlevel = alloc_level(cpu, irq);
	if (unlikely(swlevel < 0)) {
		free_irqno(irq);

		return -EAGAIN;
	}

	/* Make sure it's not already pending when we connect it. */
	nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu));
	REMOTE_HUB_CLR_INTR(nasid, swlevel);

	intr_connect_level(cpu, swlevel);

	register_bridge_irq(irq);

	return irq;
}

asmlinkage void plat_irq_dispatch(void)
{
	unsigned long pending = read_c0_cause() & read_c0_status();
	extern unsigned int rt_timer_irq;

	if (pending & CAUSEF_IP4)
		do_IRQ(rt_timer_irq);
	else if (pending & CAUSEF_IP2)	/* PI_INT_PEND_0 or CC_PEND_{A|B} */
		ip27_do_irq_mask0();
	else if (pending & CAUSEF_IP3)	/* PI_INT_PEND_1 */
		ip27_do_irq_mask1();
	else if (pending & CAUSEF_IP5)
		ip27_prof_timer();
	else if (pending & CAUSEF_IP6)
		ip27_hub_error();
}

void __init arch_init_irq(void)
{
}

void install_ipi(void)
{
	int slice = LOCAL_HUB_L(PI_CPU_NUM);
	int cpu = smp_processor_id();
	struct slice_data *si = cpu_data[cpu].data;
	struct hub_data *hub = hub_data(cpu_to_node(cpu));
	int resched, call;

	resched = CPU_RESCHED_A_IRQ + slice;
	__set_bit(resched, hub->irq_alloc_mask);
	__set_bit(resched, si->irq_enable_mask);
	LOCAL_HUB_CLR_INTR(resched);

	call = CPU_CALL_A_IRQ + slice;
	__set_bit(call, hub->irq_alloc_mask);
	__set_bit(call, si->irq_enable_mask);
	LOCAL_HUB_CLR_INTR(call);

	if (slice == 0) {
		LOCAL_HUB_S(PI_INT_MASK0_A, si->irq_enable_mask[0]);
		LOCAL_HUB_S(PI_INT_MASK1_A, si->irq_enable_mask[1]);
	} else {
		LOCAL_HUB_S(PI_INT_MASK0_B, si->irq_enable_mask[0]);
		LOCAL_HUB_S(PI_INT_MASK1_B, si->irq_enable_mask[1]);
	}
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* ip27-irq.c: Highlevel interrupt handling for IP27 architecture.
	3	*
	4	* Copyright (C) 1999, 2000 Ralf Baechle (ralf@gnu.org)
	5	* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
	6	* Copyright (C) 1999 - 2001 Kanoj Sarcar
	7	*/
d3ffd085 RB	8
	9	#undef DEBUG
	10
1da177e4 LT	11	#include <linux/init.h>
	12	#include <linux/irq.h>
	13	#include <linux/errno.h>
	14	#include <linux/signal.h>
	15	#include <linux/sched.h>
	16	#include <linux/types.h>
	17	#include <linux/interrupt.h>
	18	#include <linux/ioport.h>
1da177e4	19	#include <linux/timex.h>
631330f5	20	#include <linux/smp.h>
1da177e4	21	#include <linux/random.h>
d3ffd085	22	#include <linux/kernel.h>
1da177e4 LT	23	#include <linux/kernel_stat.h>
	24	#include <linux/delay.h>
	25	#include <linux/bitops.h>
	26
	27	#include <asm/bootinfo.h>
	28	#include <asm/io.h>
	29	#include <asm/mipsregs.h>
	30	#include <asm/system.h>
	31
1da177e4 LT	32	#include <asm/processor.h>
	33	#include <asm/pci/bridge.h>
	34	#include <asm/sn/addrs.h>
	35	#include <asm/sn/agent.h>
	36	#include <asm/sn/arch.h>
	37	#include <asm/sn/hub.h>
	38	#include <asm/sn/intr.h>
	39
1da177e4 LT	40	/*
	41	* Linux has a controller-independent x86 interrupt architecture.
	42	* every controller has a 'controller-template', that is used
	43	* by the main code to do the right thing. Each driver-visible
25985edc	44	* interrupt source is transparently wired to the appropriate
1da177e4 LT	45	* controller. Thus drivers need not be aware of the
	46	* interrupt-controller.
	47	*
	48	* Various interrupt controllers we handle: 8259 PIC, SMP IO-APIC,
	49	* PIIX4's internal 8259 PIC and SGI's Visual Workstation Cobalt (IO-)APIC.
	50	* (IO-APICs assumed to be messaging to Pentium local-APICs)
	51	*
	52	* the code is designed to be easily extended with new/different
	53	* interrupt controllers, without having to do assembly magic.
	54	*/
	55
	56	extern asmlinkage void ip27_irq(void);
	57
	58	extern struct bridge_controller *irq_to_bridge[];
	59	extern int irq_to_slot[];
	60
	61	/*
	62	* use these macros to get the encoded nasid and widget id
	63	* from the irq value
	64	*/
	65	#define IRQ_TO_BRIDGE(i) irq_to_bridge[(i)]
	66	#define SLOT_FROM_PCI_IRQ(i) irq_to_slot[i]
	67
	68	static inline int alloc_level(int cpu, int irq)
	69	{
4f12bfe5	70	struct hub_data *hub = hub_data(cpu_to_node(cpu));
1da177e4	71	struct slice_data *si = cpu_data[cpu].data;
4f12bfe5	72	int level;
1da177e4	73
4f12bfe5	74	level = find_first_zero_bit(hub->irq_alloc_mask, LEVELS_PER_SLICE);
1da177e4 LT	75	if (level >= LEVELS_PER_SLICE)
	76	panic("Cpu %d flooded with devices\n", cpu);
	77
4f12bfe5	78	__set_bit(level, hub->irq_alloc_mask);
1da177e4 LT	79	si->level_to_irq[level] = irq;
	80
	81	return level;
	82	}
	83
	84	static inline int find_level(cpuid_t *cpunum, int irq)
	85	{
	86	int cpu, i;
	87
394e3902	88	for_each_online_cpu(cpu) {
1da177e4 LT	89	struct slice_data *si = cpu_data[cpu].data;
1da177e4 LT	90
1da177e4 LT	91	for (i = BASE_PCI_IRQ; i < LEVELS_PER_SLICE; i++)
	92	if (si->level_to_irq[i] == irq) {
	93	*cpunum = cpu;
	94
	95	return i;
	96	}
	97	}
	98
	99	panic("Could not identify cpu/level for irq %d\n", irq);
	100	}
	101
	102	/*
	103	* Find first bit set
	104	*/
	105	static int ms1bit(unsigned long x)
	106	{
	107	int b = 0, s;
	108
	109	s = 16; if (x >> 16 == 0) s = 0; b += s; x >>= s;
	110	s = 8; if (x >> 8 == 0) s = 0; b += s; x >>= s;
	111	s = 4; if (x >> 4 == 0) s = 0; b += s; x >>= s;
	112	s = 2; if (x >> 2 == 0) s = 0; b += s; x >>= s;
	113	s = 1; if (x >> 1 == 0) s = 0; b += s;
	114
	115	return b;
	116	}
	117
	118	/*
f40298fd	119	* This code is unnecessarily complex, because we do IRQF_DISABLED
1da177e4 LT	120	* intr enabling. Basically, once we grab the set of intrs we need
	121	* to service, we must mask _all_ these interrupts; firstly, to make
	122	* sure the same intr does not intr again, causing recursion that
	123	* can lead to stack overflow. Secondly, we can not just mask the
	124	* one intr we are do_IRQing, because the non-masked intrs in the
	125	* first set might intr again, causing multiple servicings of the
	126	* same intr. This effect is mostly seen for intercpu intrs.
	127	* Kanoj 05.13.00
	128	*/
	129
937a8015	130	static void ip27_do_irq_mask0(void)
1da177e4 LT	131	{
	132	int irq, swlevel;
	133	hubreg_t pend0, mask0;
	134	cpuid_t cpu = smp_processor_id();
	135	int pi_int_mask0 =
	136	(cputoslice(cpu) == 0) ? PI_INT_MASK0_A : PI_INT_MASK0_B;
	137
	138	/* copied from Irix intpend0() */
	139	pend0 = LOCAL_HUB_L(PI_INT_PEND0);
	140	mask0 = LOCAL_HUB_L(pi_int_mask0);
	141
	142	pend0 &= mask0; /* Pick intrs we should look at */
	143	if (!pend0)
	144	return;
	145
	146	swlevel = ms1bit(pend0);
	147	#ifdef CONFIG_SMP
	148	if (pend0 & (1UL << CPU_RESCHED_A_IRQ)) {
	149	LOCAL_HUB_CLR_INTR(CPU_RESCHED_A_IRQ);
	150	} else if (pend0 & (1UL << CPU_RESCHED_B_IRQ)) {
	151	LOCAL_HUB_CLR_INTR(CPU_RESCHED_B_IRQ);
	152	} else if (pend0 & (1UL << CPU_CALL_A_IRQ)) {
	153	LOCAL_HUB_CLR_INTR(CPU_CALL_A_IRQ);
	154	smp_call_function_interrupt();
	155	} else if (pend0 & (1UL << CPU_CALL_B_IRQ)) {
	156	LOCAL_HUB_CLR_INTR(CPU_CALL_B_IRQ);
	157	smp_call_function_interrupt();
	158	} else
	159	#endif
	160	{
	161	/* "map" swlevel to irq */
	162	struct slice_data *si = cpu_data[cpu].data;
	163
	164	irq = si->level_to_irq[swlevel];
937a8015	165	do_IRQ(irq);
1da177e4 LT	166	}
	167
	168	LOCAL_HUB_L(PI_INT_PEND0);
	169	}
	170
937a8015	171	static void ip27_do_irq_mask1(void)
1da177e4 LT	172	{
	173	int irq, swlevel;
	174	hubreg_t pend1, mask1;
	175	cpuid_t cpu = smp_processor_id();
	176	int pi_int_mask1 = (cputoslice(cpu) == 0) ? PI_INT_MASK1_A : PI_INT_MASK1_B;
	177	struct slice_data *si = cpu_data[cpu].data;
	178
	179	/* copied from Irix intpend0() */
	180	pend1 = LOCAL_HUB_L(PI_INT_PEND1);
	181	mask1 = LOCAL_HUB_L(pi_int_mask1);
	182
	183	pend1 &= mask1; /* Pick intrs we should look at */
	184	if (!pend1)
	185	return;
	186
	187	swlevel = ms1bit(pend1);
	188	/* "map" swlevel to irq */
	189	irq = si->level_to_irq[swlevel];
	190	LOCAL_HUB_CLR_INTR(swlevel);
937a8015	191	do_IRQ(irq);
1da177e4 LT	192
	193	LOCAL_HUB_L(PI_INT_PEND1);
	194	}
	195
937a8015	196	static void ip27_prof_timer(void)
1da177e4 LT	197	{
	198	panic("CPU %d got a profiling interrupt", smp_processor_id());
	199	}
	200
937a8015	201	static void ip27_hub_error(void)
1da177e4 LT	202	{
	203	panic("CPU %d got a hub error interrupt", smp_processor_id());
	204	}
	205
	206	static int intr_connect_level(int cpu, int bit)
	207	{
	208	nasid_t nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu));
	209	struct slice_data *si = cpu_data[cpu].data;
	210
4f12bfe5	211	set_bit(bit, si->irq_enable_mask);
1da177e4 LT	212
	213	if (!cputoslice(cpu)) {
	214	REMOTE_HUB_S(nasid, PI_INT_MASK0_A, si->irq_enable_mask[0]);
	215	REMOTE_HUB_S(nasid, PI_INT_MASK1_A, si->irq_enable_mask[1]);
	216	} else {
	217	REMOTE_HUB_S(nasid, PI_INT_MASK0_B, si->irq_enable_mask[0]);
	218	REMOTE_HUB_S(nasid, PI_INT_MASK1_B, si->irq_enable_mask[1]);
	219	}
	220
	221	return 0;
	222	}
	223
	224	static int intr_disconnect_level(int cpu, int bit)
	225	{
	226	nasid_t nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu));
	227	struct slice_data *si = cpu_data[cpu].data;
	228
4f12bfe5	229	clear_bit(bit, si->irq_enable_mask);
1da177e4 LT	230
	231	if (!cputoslice(cpu)) {
	232	REMOTE_HUB_S(nasid, PI_INT_MASK0_A, si->irq_enable_mask[0]);
	233	REMOTE_HUB_S(nasid, PI_INT_MASK1_A, si->irq_enable_mask[1]);
	234	} else {
	235	REMOTE_HUB_S(nasid, PI_INT_MASK0_B, si->irq_enable_mask[0]);
	236	REMOTE_HUB_S(nasid, PI_INT_MASK1_B, si->irq_enable_mask[1]);
	237	}
	238
	239	return 0;
	240	}
	241
	242	/* Startup one of the (PCI ...) IRQs routes over a bridge. */
301218df	243	static unsigned int startup_bridge_irq(struct irq_data *d)
1da177e4 LT	244	{
	245	struct bridge_controller *bc;
	246	bridgereg_t device;
	247	bridge_t *bridge;
	248	int pin, swlevel;
	249	cpuid_t cpu;
	250
301218df TG	251	pin = SLOT_FROM_PCI_IRQ(d->irq);
301218df TG	252	bc = IRQ_TO_BRIDGE(d->irq);
1da177e4 LT	253	bridge = bc->base;
1da177e4 LT	254
301218df	255	pr_debug("bridge_startup(): irq= 0x%x pin=%d\n", d->irq, pin);
1da177e4 LT	256	/*
	257	* "map" irq to a swlevel greater than 6 since the first 6 bits
	258	* of INT_PEND0 are taken
	259	*/
301218df	260	swlevel = find_level(&cpu, d->irq);
1da177e4 LT	261	bridge->b_int_addr[pin].addr = (0x20000 \| swlevel \| (bc->nasid << 8));
	262	bridge->b_int_enable \|= (1 << pin);
	263	bridge->b_int_enable \|= 0x7ffffe00; /* more stuff in int_enable */
	264
	265	/*
	266	* Enable sending of an interrupt clear packt to the hub on a high to
	267	* low transition of the interrupt pin.
	268	*
	269	* IRIX sets additional bits in the address which are documented as
	270	* reserved in the bridge docs.
	271	*/
	272	bridge->b_int_mode \|= (1UL << pin);
	273
	274	/*
	275	* We assume the bridge to have a 1:1 mapping between devices
	276	* (slots) and intr pins.
	277	*/
	278	device = bridge->b_int_device;
	279	device &= ~(7 << (pin*3));
	280	device \|= (pin << (pin*3));
	281	bridge->b_int_device = device;
	282
	283	bridge->b_wid_tflush;
	284
84ced306 RB	285	intr_connect_level(cpu, swlevel);
84ced306 RB	286
1da177e4 LT	287	return 0; /* Never anything pending. */
	288	}
	289
	290	/* Shutdown one of the (PCI ...) IRQs routes over a bridge. */
301218df	291	static void shutdown_bridge_irq(struct irq_data *d)
1da177e4	292	{
301218df	293	struct bridge_controller *bc = IRQ_TO_BRIDGE(d->irq);
1da177e4	294	bridge_t *bridge = bc->base;
1da177e4 LT	295	int pin, swlevel;
	296	cpuid_t cpu;
	297
301218df TG	298	pr_debug("bridge_shutdown: irq 0x%x\n", d->irq);
301218df TG	299	pin = SLOT_FROM_PCI_IRQ(d->irq);
1da177e4 LT	300
	301	/*
	302	* map irq to a swlevel greater than 6 since the first 6 bits
	303	* of INT_PEND0 are taken
	304	*/
301218df	305	swlevel = find_level(&cpu, d->irq);
1da177e4 LT	306	intr_disconnect_level(cpu, swlevel);
1da177e4 LT	307
1da177e4 LT	308	bridge->b_int_enable &= ~(1 << pin);
	309	bridge->b_wid_tflush;
	310	}
	311
301218df	312	static inline void enable_bridge_irq(struct irq_data *d)
1da177e4 LT	313	{
	314	cpuid_t cpu;
	315	int swlevel;
	316
301218df	317	swlevel = find_level(&cpu, d->irq); /* Criminal offence */
1da177e4 LT	318	intr_connect_level(cpu, swlevel);
	319	}
	320
301218df	321	static inline void disable_bridge_irq(struct irq_data *d)
1da177e4 LT	322	{
	323	cpuid_t cpu;
	324	int swlevel;
	325
301218df	326	swlevel = find_level(&cpu, d->irq); /* Criminal offence */
1da177e4 LT	327	intr_disconnect_level(cpu, swlevel);
	328	}
	329
94dee171	330	static struct irq_chip bridge_irq_type = {
70d21cde	331	.name = "bridge",
301218df TG	332	.irq_startup = startup_bridge_irq,
	333	.irq_shutdown = shutdown_bridge_irq,
	334	.irq_mask = disable_bridge_irq,
	335	.irq_unmask = enable_bridge_irq,
1da177e4 LT	336	};
1da177e4 LT	337
1da177e4 LT	338	void __devinit register_bridge_irq(unsigned int irq)
1da177e4 LT	339	{
e4ec7989	340	irq_set_chip_and_handler(irq, &bridge_irq_type, handle_level_irq);
1da177e4 LT	341	}
	342
	343	int __devinit request_bridge_irq(struct bridge_controller *bc)
	344	{
	345	int irq = allocate_irqno();
	346	int swlevel, cpu;
	347	nasid_t nasid;
	348
	349	if (irq < 0)
	350	return irq;
	351
	352	/*
	353	* "map" irq to a swlevel greater than 6 since the first 6 bits
	354	* of INT_PEND0 are taken
	355	*/
	356	cpu = bc->irq_cpu;
	357	swlevel = alloc_level(cpu, irq);
	358	if (unlikely(swlevel < 0)) {
	359	free_irqno(irq);
	360
	361	return -EAGAIN;
	362	}
	363
	364	/* Make sure it's not already pending when we connect it. */
	365	nasid = COMPACT_TO_NASID_NODEID(cpu_to_node(cpu));
	366	REMOTE_HUB_CLR_INTR(nasid, swlevel);
	367
	368	intr_connect_level(cpu, swlevel);
	369
	370	register_bridge_irq(irq);
	371
	372	return irq;
	373	}
	374
937a8015	375	asmlinkage void plat_irq_dispatch(void)
e4ac58af RB	376	{
e4ac58af RB	377	unsigned long pending = read_c0_cause() & read_c0_status();
e887b245	378	extern unsigned int rt_timer_irq;
e4ac58af RB	379
e4ac58af RB	380	if (pending & CAUSEF_IP4)
e887b245	381	do_IRQ(rt_timer_irq);
e4ac58af	382	else if (pending & CAUSEF_IP2) /* PI_INT_PEND_0 or CC_PEND_{A\|B} */
937a8015	383	ip27_do_irq_mask0();
e4ac58af	384	else if (pending & CAUSEF_IP3) /* PI_INT_PEND_1 */
937a8015	385	ip27_do_irq_mask1();
e4ac58af	386	else if (pending & CAUSEF_IP5)
937a8015	387	ip27_prof_timer();
e4ac58af	388	else if (pending & CAUSEF_IP6)
937a8015	389	ip27_hub_error();
e4ac58af RB	390	}
e4ac58af RB	391
1da177e4 LT	392	void __init arch_init_irq(void)
1da177e4 LT	393	{
1da177e4 LT	394	}
	395
	396	void install_ipi(void)
	397	{
	398	int slice = LOCAL_HUB_L(PI_CPU_NUM);
	399	int cpu = smp_processor_id();
	400	struct slice_data *si = cpu_data[cpu].data;
4f12bfe5 RB	401	struct hub_data *hub = hub_data(cpu_to_node(cpu));
	402	int resched, call;
	403
	404	resched = CPU_RESCHED_A_IRQ + slice;
	405	__set_bit(resched, hub->irq_alloc_mask);
	406	__set_bit(resched, si->irq_enable_mask);
	407	LOCAL_HUB_CLR_INTR(resched);
	408
	409	call = CPU_CALL_A_IRQ + slice;
	410	__set_bit(call, hub->irq_alloc_mask);
	411	__set_bit(call, si->irq_enable_mask);
	412	LOCAL_HUB_CLR_INTR(call);
1da177e4 LT	413
1da177e4 LT	414	if (slice == 0) {
4f12bfe5 RB	415	LOCAL_HUB_S(PI_INT_MASK0_A, si->irq_enable_mask[0]);
4f12bfe5 RB	416	LOCAL_HUB_S(PI_INT_MASK1_A, si->irq_enable_mask[1]);
1da177e4	417	} else {
4f12bfe5 RB	418	LOCAL_HUB_S(PI_INT_MASK0_B, si->irq_enable_mask[0]);
4f12bfe5 RB	419	LOCAL_HUB_S(PI_INT_MASK1_B, si->irq_enable_mask[1]);
1da177e4 LT	420	}
1da177e4 LT	421	}