[GitHub/exynos8895/android_kernel_samsung_universal8895.git] / arch / mips / rb532 / devices.c

/*
 *  RouterBoard 500 Platform devices
 *
 *  Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
 *  Copyright (C) 2007 Florian Fainelli <florian@openwrt.org>
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 *  GNU General Public License for more details.
 */
#include <linux/kernel.h>
#include <linux/export.h>
#include <linux/init.h>
#include <linux/ctype.h>
#include <linux/string.h>
#include <linux/platform_device.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/gpio_keys.h>
#include <linux/input.h>
#include <linux/serial_8250.h>

#include <asm/bootinfo.h>

#include <asm/mach-rc32434/rc32434.h>
#include <asm/mach-rc32434/dma.h>
#include <asm/mach-rc32434/dma_v.h>
#include <asm/mach-rc32434/eth.h>
#include <asm/mach-rc32434/rb.h>
#include <asm/mach-rc32434/integ.h>
#include <asm/mach-rc32434/gpio.h>
#include <asm/mach-rc32434/irq.h>

#define ETH0_RX_DMA_ADDR  (DMA0_BASE_ADDR + 0 * DMA_CHAN_OFFSET)
#define ETH0_TX_DMA_ADDR  (DMA0_BASE_ADDR + 1 * DMA_CHAN_OFFSET)

extern unsigned int idt_cpu_freq;

static struct mpmc_device dev3;

void set_latch_u5(unsigned char or_mask, unsigned char nand_mask)
{
	unsigned long flags;

	spin_lock_irqsave(&dev3.lock, flags);

	dev3.state = (dev3.state | or_mask) & ~nand_mask;
	writeb(dev3.state, dev3.base);

	spin_unlock_irqrestore(&dev3.lock, flags);
}
EXPORT_SYMBOL(set_latch_u5);

unsigned char get_latch_u5(void)
{
	return dev3.state;
}
EXPORT_SYMBOL(get_latch_u5);

static struct resource korina_dev0_res[] = {
	{
		.name = "korina_regs",
		.start = ETH0_BASE_ADDR,
		.end = ETH0_BASE_ADDR + sizeof(struct eth_regs),
		.flags = IORESOURCE_MEM,
	 }, {
		.name = "korina_rx",
		.start = ETH0_DMA_RX_IRQ,
		.end = ETH0_DMA_RX_IRQ,
		.flags = IORESOURCE_IRQ
	}, {
		.name = "korina_tx",
		.start = ETH0_DMA_TX_IRQ,
		.end = ETH0_DMA_TX_IRQ,
		.flags = IORESOURCE_IRQ
	}, {
		.name = "korina_ovr",
		.start = ETH0_RX_OVR_IRQ,
		.end = ETH0_RX_OVR_IRQ,
		.flags = IORESOURCE_IRQ
	}, {
		.name = "korina_und",
		.start = ETH0_TX_UND_IRQ,
		.end = ETH0_TX_UND_IRQ,
		.flags = IORESOURCE_IRQ
	}, {
		.name = "korina_dma_rx",
		.start = ETH0_RX_DMA_ADDR,
		.end = ETH0_RX_DMA_ADDR + DMA_CHAN_OFFSET - 1,
		.flags = IORESOURCE_MEM,
	 }, {
		.name = "korina_dma_tx",
		.start = ETH0_TX_DMA_ADDR,
		.end = ETH0_TX_DMA_ADDR + DMA_CHAN_OFFSET - 1,
		.flags = IORESOURCE_MEM,
	 }
};

static struct korina_device korina_dev0_data = {
	.name = "korina0",
	.mac = {0xde, 0xca, 0xff, 0xc0, 0xff, 0xee}
};

static struct platform_device korina_dev0 = {
	.id = -1,
	.name = "korina",
	.resource = korina_dev0_res,
	.num_resources = ARRAY_SIZE(korina_dev0_res),
};

static struct resource cf_slot0_res[] = {
	{
		.name = "cf_membase",
		.flags = IORESOURCE_MEM
	}, {
		.name = "cf_irq",
		.start = (8 + 4 * 32 + CF_GPIO_NUM),	/* 149 */
		.end = (8 + 4 * 32 + CF_GPIO_NUM),
		.flags = IORESOURCE_IRQ
	}
};

static struct cf_device cf_slot0_data = {
	.gpio_pin = CF_GPIO_NUM
};

static struct platform_device cf_slot0 = {
	.id = -1,
	.name = "pata-rb532-cf",
	.dev.platform_data = &cf_slot0_data,
	.resource = cf_slot0_res,
	.num_resources = ARRAY_SIZE(cf_slot0_res),
};

/* Resources and device for NAND */
static int rb532_dev_ready(struct mtd_info *mtd)
{
	return gpio_get_value(GPIO_RDY);
}

static void rb532_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
	struct nand_chip *chip = mtd->priv;
	unsigned char orbits, nandbits;

	if (ctrl & NAND_CTRL_CHANGE) {
		orbits = (ctrl & NAND_CLE) << 1;
		orbits |= (ctrl & NAND_ALE) >> 1;

		nandbits = (~ctrl & NAND_CLE) << 1;
		nandbits |= (~ctrl & NAND_ALE) >> 1;

		set_latch_u5(orbits, nandbits);
	}
	if (cmd != NAND_CMD_NONE)
		writeb(cmd, chip->IO_ADDR_W);
}

static struct resource nand_slot0_res[] = {
	[0] = {
		.name = "nand_membase",
		.flags = IORESOURCE_MEM
	}
};

static struct platform_nand_data rb532_nand_data = {
	.ctrl.dev_ready = rb532_dev_ready,
	.ctrl.cmd_ctrl	= rb532_cmd_ctrl,
};

static struct platform_device nand_slot0 = {
	.name = "gen_nand",
	.id = -1,
	.resource = nand_slot0_res,
	.num_resources = ARRAY_SIZE(nand_slot0_res),
	.dev.platform_data = &rb532_nand_data,
};

static struct mtd_partition rb532_partition_info[] = {
	{
		.name = "Routerboard NAND boot",
		.offset = 0,
		.size = 4 * 1024 * 1024,
	}, {
		.name = "rootfs",
		.offset = MTDPART_OFS_NXTBLK,
		.size = MTDPART_SIZ_FULL,
	}
};

static struct platform_device rb532_led = {
	.name = "rb532-led",
	.id = -1,
};

static struct platform_device rb532_button = {
	.name	= "rb532-button",
	.id	= -1,
};

static struct resource rb532_wdt_res[] = {
	{
		.name = "rb532_wdt_res",
		.start = INTEG0_BASE_ADDR,
		.end = INTEG0_BASE_ADDR + sizeof(struct integ),
		.flags = IORESOURCE_MEM,
	}
};

static struct platform_device rb532_wdt = {
	.name		= "rc32434_wdt",
	.id		= -1,
	.resource	= rb532_wdt_res,
	.num_resources	= ARRAY_SIZE(rb532_wdt_res),
};

static struct plat_serial8250_port rb532_uart_res[] = {
	{
		.membase	= (char *)KSEG1ADDR(REGBASE + UART0BASE),
		.irq		= UART0_IRQ,
		.regshift	= 2,
		.iotype		= UPIO_MEM,
		.flags		= UPF_BOOT_AUTOCONF,
	},
	{
		.flags		= 0,
	}
};

static struct platform_device rb532_uart = {
	.name		   = "serial8250",
	.id		   = PLAT8250_DEV_PLATFORM,
	.dev.platform_data = &rb532_uart_res,
};

static struct platform_device *rb532_devs[] = {
	&korina_dev0,
	&nand_slot0,
	&cf_slot0,
	&rb532_led,
	&rb532_button,
	&rb532_uart,
	&rb532_wdt
};

static void __init parse_mac_addr(char *macstr)
{
	int i, h, l;

	for (i = 0; i < 6; i++) {
		if (i != 5 && *(macstr + 2) != ':')
			return;

		h = hex_to_bin(*macstr++);
		if (h == -1)
			return;

		l = hex_to_bin(*macstr++);
		if (l == -1)
			return;

		macstr++;
		korina_dev0_data.mac[i] = (h << 4) + l;
	}
}


/* NAND definitions */
#define NAND_CHIP_DELAY 25

static void __init rb532_nand_setup(void)
{
	switch (mips_machtype) {
	case MACH_MIKROTIK_RB532A:
		set_latch_u5(LO_FOFF | LO_CEX,
				LO_ULED | LO_ALE | LO_CLE | LO_WPX);
		break;
	default:
		set_latch_u5(LO_WPX | LO_FOFF | LO_CEX,
				LO_ULED | LO_ALE | LO_CLE);
		break;
	}

	/* Setup NAND specific settings */
	rb532_nand_data.chip.nr_chips = 1;
	rb532_nand_data.chip.nr_partitions = ARRAY_SIZE(rb532_partition_info);
	rb532_nand_data.chip.partitions = rb532_partition_info;
	rb532_nand_data.chip.chip_delay = NAND_CHIP_DELAY;
}


static int __init plat_setup_devices(void)
{
	/* Look for the CF card reader */
	if (!readl(IDT434_REG_BASE + DEV1MASK))
		rb532_devs[2] = NULL;	/* disable cf_slot0 at index 2 */
	else {
		cf_slot0_res[0].start =
		    readl(IDT434_REG_BASE + DEV1BASE);
		cf_slot0_res[0].end = cf_slot0_res[0].start + 0x1000;
	}

	/* Read the NAND resources from the device controller */
	nand_slot0_res[0].start = readl(IDT434_REG_BASE + DEV2BASE);
	nand_slot0_res[0].end = nand_slot0_res[0].start + 0x1000;

	/* Read and map device controller 3 */
	dev3.base = ioremap_nocache(readl(IDT434_REG_BASE + DEV3BASE), 1);

	if (!dev3.base) {
		printk(KERN_ERR "rb532: cannot remap device controller 3\n");
		return -ENXIO;
	}

	/* Initialise the NAND device */
	rb532_nand_setup();

	/* set the uart clock to the current cpu frequency */
	rb532_uart_res[0].uartclk = idt_cpu_freq;

	dev_set_drvdata(&korina_dev0.dev, &korina_dev0_data);

	return platform_add_devices(rb532_devs, ARRAY_SIZE(rb532_devs));
}

static int __init setup_kmac(char *s)
{
	printk(KERN_INFO "korina mac = %s\n", s);
	parse_mac_addr(s);
	return 0;
}

__setup("kmac=", setup_kmac);

arch_initcall(plat_setup_devices);
Commit	Line	Data
73b4390f RB	1	/*
	2	* RouterBoard 500 Platform devices
	3	*
	4	* Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
	5	* Copyright (C) 2007 Florian Fainelli <florian@openwrt.org>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*/
	17	#include <linux/kernel.h>
f9ded569	18	#include <linux/export.h>
73b4390f RB	19	#include <linux/init.h>
	20	#include <linux/ctype.h>
	21	#include <linux/string.h>
	22	#include <linux/platform_device.h>
	23	#include <linux/mtd/nand.h>
	24	#include <linux/mtd/mtd.h>
	25	#include <linux/mtd/partitions.h>
	26	#include <linux/gpio_keys.h>
	27	#include <linux/input.h>
1452fc7d	28	#include <linux/serial_8250.h>
73b4390f RB	29
	30	#include <asm/bootinfo.h>
	31
	32	#include <asm/mach-rc32434/rc32434.h>
	33	#include <asm/mach-rc32434/dma.h>
	34	#include <asm/mach-rc32434/dma_v.h>
	35	#include <asm/mach-rc32434/eth.h>
	36	#include <asm/mach-rc32434/rb.h>
	37	#include <asm/mach-rc32434/integ.h>
	38	#include <asm/mach-rc32434/gpio.h>
3cd4e067	39	#include <asm/mach-rc32434/irq.h>
73b4390f RB	40
	41	#define ETH0_RX_DMA_ADDR (DMA0_BASE_ADDR + 0 * DMA_CHAN_OFFSET)
	42	#define ETH0_TX_DMA_ADDR (DMA0_BASE_ADDR + 1 * DMA_CHAN_OFFSET)
	43
1452fc7d PS	44	extern unsigned int idt_cpu_freq;
1452fc7d PS	45
36f2db4b PS	46	static struct mpmc_device dev3;
	47
	48	void set_latch_u5(unsigned char or_mask, unsigned char nand_mask)
	49	{
	50	unsigned long flags;
	51
	52	spin_lock_irqsave(&dev3.lock, flags);
	53
	54	dev3.state = (dev3.state \| or_mask) & ~nand_mask;
	55	writeb(dev3.state, dev3.base);
	56
	57	spin_unlock_irqrestore(&dev3.lock, flags);
	58	}
	59	EXPORT_SYMBOL(set_latch_u5);
	60
	61	unsigned char get_latch_u5(void)
	62	{
	63	return dev3.state;
	64	}
	65	EXPORT_SYMBOL(get_latch_u5);
	66
73b4390f RB	67	static struct resource korina_dev0_res[] = {
	68	{
	69	.name = "korina_regs",
	70	.start = ETH0_BASE_ADDR,
	71	.end = ETH0_BASE_ADDR + sizeof(struct eth_regs),
	72	.flags = IORESOURCE_MEM,
	73	}, {
	74	.name = "korina_rx",
	75	.start = ETH0_DMA_RX_IRQ,
	76	.end = ETH0_DMA_RX_IRQ,
	77	.flags = IORESOURCE_IRQ
	78	}, {
	79	.name = "korina_tx",
	80	.start = ETH0_DMA_TX_IRQ,
	81	.end = ETH0_DMA_TX_IRQ,
	82	.flags = IORESOURCE_IRQ
	83	}, {
	84	.name = "korina_ovr",
	85	.start = ETH0_RX_OVR_IRQ,
	86	.end = ETH0_RX_OVR_IRQ,
	87	.flags = IORESOURCE_IRQ
	88	}, {
	89	.name = "korina_und",
	90	.start = ETH0_TX_UND_IRQ,
	91	.end = ETH0_TX_UND_IRQ,
	92	.flags = IORESOURCE_IRQ
	93	}, {
	94	.name = "korina_dma_rx",
	95	.start = ETH0_RX_DMA_ADDR,
	96	.end = ETH0_RX_DMA_ADDR + DMA_CHAN_OFFSET - 1,
	97	.flags = IORESOURCE_MEM,
	98	}, {
	99	.name = "korina_dma_tx",
	100	.start = ETH0_TX_DMA_ADDR,
	101	.end = ETH0_TX_DMA_ADDR + DMA_CHAN_OFFSET - 1,
	102	.flags = IORESOURCE_MEM,
	103	}
	104	};
	105
	106	static struct korina_device korina_dev0_data = {
	107	.name = "korina0",
	108	.mac = {0xde, 0xca, 0xff, 0xc0, 0xff, 0xee}
	109	};
	110
	111	static struct platform_device korina_dev0 = {
b6e2f58a	112	.id = -1,
73b4390f	113	.name = "korina",
73b4390f RB	114	.resource = korina_dev0_res,
	115	.num_resources = ARRAY_SIZE(korina_dev0_res),
	116	};
	117
73b4390f RB	118	static struct resource cf_slot0_res[] = {
	119	{
	120	.name = "cf_membase",
	121	.flags = IORESOURCE_MEM
	122	}, {
	123	.name = "cf_irq",
	124	.start = (8 + 4 * 32 + CF_GPIO_NUM), /* 149 */
	125	.end = (8 + 4 * 32 + CF_GPIO_NUM),
	126	.flags = IORESOURCE_IRQ
	127	}
	128	};
	129
	130	static struct cf_device cf_slot0_data = {
3cd4e067	131	.gpio_pin = CF_GPIO_NUM
73b4390f RB	132	};
	133
	134	static struct platform_device cf_slot0 = {
b6e2f58a	135	.id = -1,
73b4390f RB	136	.name = "pata-rb532-cf",
	137	.dev.platform_data = &cf_slot0_data,
	138	.resource = cf_slot0_res,
	139	.num_resources = ARRAY_SIZE(cf_slot0_res),
	140	};
	141
	142	/* Resources and device for NAND */
	143	static int rb532_dev_ready(struct mtd_info *mtd)
	144	{
1b432840	145	return gpio_get_value(GPIO_RDY);
73b4390f RB	146	}
	147
	148	static void rb532_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
	149	{
	150	struct nand_chip *chip = mtd->priv;
	151	unsigned char orbits, nandbits;
	152
	153	if (ctrl & NAND_CTRL_CHANGE) {
	154	orbits = (ctrl & NAND_CLE) << 1;
	155	orbits \|= (ctrl & NAND_ALE) >> 1;
	156
	157	nandbits = (~ctrl & NAND_CLE) << 1;
	158	nandbits \|= (~ctrl & NAND_ALE) >> 1;
	159
	160	set_latch_u5(orbits, nandbits);
	161	}
	162	if (cmd != NAND_CMD_NONE)
	163	writeb(cmd, chip->IO_ADDR_W);
	164	}
	165
	166	static struct resource nand_slot0_res[] = {
	167	[0] = {
	168	.name = "nand_membase",
	169	.flags = IORESOURCE_MEM
	170	}
	171	};
	172
	173	static struct platform_nand_data rb532_nand_data = {
	174	.ctrl.dev_ready = rb532_dev_ready,
	175	.ctrl.cmd_ctrl = rb532_cmd_ctrl,
	176	};
	177
	178	static struct platform_device nand_slot0 = {
	179	.name = "gen_nand",
	180	.id = -1,
	181	.resource = nand_slot0_res,
	182	.num_resources = ARRAY_SIZE(nand_slot0_res),
	183	.dev.platform_data = &rb532_nand_data,
	184	};
	185
	186	static struct mtd_partition rb532_partition_info[] = {
	187	{
	188	.name = "Routerboard NAND boot",
	189	.offset = 0,
	190	.size = 4 * 1024 * 1024,
	191	}, {
	192	.name = "rootfs",
	193	.offset = MTDPART_OFS_NXTBLK,
	194	.size = MTDPART_SIZ_FULL,
	195	}
	196	};
	197
	198	static struct platform_device rb532_led = {
	199	.name = "rb532-led",
b6e2f58a	200	.id = -1,
73b4390f RB	201	};
73b4390f RB	202
73b4390f	203	static struct platform_device rb532_button = {
d9bdffd2	204	.name = "rb532-button",
73b4390f	205	.id = -1,
73b4390f RB	206	};
	207
	208	static struct resource rb532_wdt_res[] = {
	209	{
	210	.name = "rb532_wdt_res",
	211	.start = INTEG0_BASE_ADDR,
	212	.end = INTEG0_BASE_ADDR + sizeof(struct integ),
	213	.flags = IORESOURCE_MEM,
	214	}
	215	};
	216
	217	static struct platform_device rb532_wdt = {
70342287 RB	218	.name = "rc32434_wdt",
	219	.id = -1,
	220	.resource = rb532_wdt_res,
73b4390f RB	221	.num_resources = ARRAY_SIZE(rb532_wdt_res),
	222	};
	223
1452fc7d PS	224	static struct plat_serial8250_port rb532_uart_res[] = {
	225	{
	226	.membase = (char *)KSEG1ADDR(REGBASE + UART0BASE),
	227	.irq = UART0_IRQ,
	228	.regshift = 2,
	229	.iotype = UPIO_MEM,
	230	.flags = UPF_BOOT_AUTOCONF,
	231	},
	232	{
	233	.flags = 0,
	234	}
	235	};
	236
	237	static struct platform_device rb532_uart = {
70342287 RB	238	.name = "serial8250",
70342287 RB	239	.id = PLAT8250_DEV_PLATFORM,
1452fc7d PS	240	.dev.platform_data = &rb532_uart_res,
	241	};
	242
73b4390f RB	243	static struct platform_device *rb532_devs[] = {
	244	&korina_dev0,
	245	&nand_slot0,
	246	&cf_slot0,
	247	&rb532_led,
	248	&rb532_button,
1452fc7d	249	&rb532_uart,
73b4390f RB	250	&rb532_wdt
	251	};
	252
	253	static void __init parse_mac_addr(char *macstr)
	254	{
c8e58856	255	int i, h, l;
73b4390f RB	256
73b4390f RB	257	for (i = 0; i < 6; i++) {
73b4390f RB	258	if (i != 5 && *(macstr + 2) != ':')
	259	return;
	260
c8e58856 AS	261	h = hex_to_bin(*macstr++);
	262	if (h == -1)
	263	return;
	264
	265	l = hex_to_bin(*macstr++);
	266	if (l == -1)
	267	return;
73b4390f RB	268
73b4390f RB	269	macstr++;
c8e58856	270	korina_dev0_data.mac[i] = (h << 4) + l;
73b4390f RB	271	}
	272	}
	273
	274
73b4390f	275	/* NAND definitions */
70342287	276	#define NAND_CHIP_DELAY 25
73b4390f RB	277
	278	static void __init rb532_nand_setup(void)
	279	{
	280	switch (mips_machtype) {
	281	case MACH_MIKROTIK_RB532A:
	282	set_latch_u5(LO_FOFF \| LO_CEX,
	283	LO_ULED \| LO_ALE \| LO_CLE \| LO_WPX);
	284	break;
	285	default:
	286	set_latch_u5(LO_WPX \| LO_FOFF \| LO_CEX,
	287	LO_ULED \| LO_ALE \| LO_CLE);
	288	break;
	289	}
	290
	291	/* Setup NAND specific settings */
	292	rb532_nand_data.chip.nr_chips = 1;
	293	rb532_nand_data.chip.nr_partitions = ARRAY_SIZE(rb532_partition_info);
	294	rb532_nand_data.chip.partitions = rb532_partition_info;
	295	rb532_nand_data.chip.chip_delay = NAND_CHIP_DELAY;
73b4390f RB	296	}
	297
	298
	299	static int __init plat_setup_devices(void)
	300	{
	301	/* Look for the CF card reader */
1ddfe82d	302	if (!readl(IDT434_REG_BASE + DEV1MASK))
bc4c4e83	303	rb532_devs[2] = NULL; /* disable cf_slot0 at index 2 */
73b4390f RB	304	else {
73b4390f RB	305	cf_slot0_res[0].start =
1ddfe82d	306	readl(IDT434_REG_BASE + DEV1BASE);
73b4390f RB	307	cf_slot0_res[0].end = cf_slot0_res[0].start + 0x1000;
	308	}
	309
	310	/* Read the NAND resources from the device controller */
1ddfe82d	311	nand_slot0_res[0].start = readl(IDT434_REG_BASE + DEV2BASE);
73b4390f RB	312	nand_slot0_res[0].end = nand_slot0_res[0].start + 0x1000;
73b4390f RB	313
1c4db8e8 PS	314	/* Read and map device controller 3 */
1c4db8e8 PS	315	dev3.base = ioremap_nocache(readl(IDT434_REG_BASE + DEV3BASE), 1);
36f2db4b PS	316
	317	if (!dev3.base) {
	318	printk(KERN_ERR "rb532: cannot remap device controller 3\n");
	319	return -ENXIO;
	320	}
	321
73b4390f RB	322	/* Initialise the NAND device */
	323	rb532_nand_setup();
	324
1452fc7d PS	325	/* set the uart clock to the current cpu frequency */
	326	rb532_uart_res[0].uartclk = idt_cpu_freq;
	327
4e7c81af FF	328	dev_set_drvdata(&korina_dev0.dev, &korina_dev0_data);
4e7c81af FF	329
73b4390f RB	330	return platform_add_devices(rb532_devs, ARRAY_SIZE(rb532_devs));
	331	}
	332
	333	static int __init setup_kmac(char *s)
	334	{
	335	printk(KERN_INFO "korina mac = %s\n", s);
	336	parse_mac_addr(s);
	337	return 0;
	338	}
	339
	340	__setup("kmac=", setup_kmac);
	341
	342	arch_initcall(plat_setup_devices);