[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / mips / pci / pci.c

/*
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 * Copyright (C) 2003, 04 Ralf Baechle (ralf@linux-mips.org)
 */
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/bootmem.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/pci.h>

/*
 * Indicate whether we respect the PCI setup left by the firmware.
 *
 * Make this long-lived  so that we know when shutting down
 * whether we probed only or not.
 */
int pci_probe_only;

#define PCI_ASSIGN_ALL_BUSSES	1

unsigned int pci_probe = PCI_ASSIGN_ALL_BUSSES;

/*
 * The PCI controller list.
 */

static struct pci_controller *hose_head, **hose_tail = &hose_head;

unsigned long PCIBIOS_MIN_IO;
unsigned long PCIBIOS_MIN_MEM;

static int pci_initialized;

/*
 * We need to avoid collisions with `mirrored' VGA ports
 * and other strange ISA hardware, so we always want the
 * addresses to be allocated in the 0x000-0x0ff region
 * modulo 0x400.
 *
 * Why? Because some silly external IO cards only decode
 * the low 10 bits of the IO address. The 0x00-0xff region
 * is reserved for motherboard devices that decode all 16
 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
 * but we want to try to avoid allocating at 0x2900-0x2bff
 * which might have be mirrored at 0x0100-0x03ff..
 */
resource_size_t
pcibios_align_resource(void *data, struct resource *res,
		       resource_size_t size, resource_size_t align)
{
	struct pci_dev *dev = data;
	struct pci_controller *hose = dev->sysdata;
	resource_size_t start = res->start;

	if (res->flags & IORESOURCE_IO) {
		/* Make sure we start at our min on all hoses */
		if (start < PCIBIOS_MIN_IO + hose->io_resource->start)
			start = PCIBIOS_MIN_IO + hose->io_resource->start;

		/*
		 * Put everything into 0x00-0xff region modulo 0x400
		 */
		if (start & 0x300)
			start = (start + 0x3ff) & ~0x3ff;
	} else if (res->flags & IORESOURCE_MEM) {
		/* Make sure we start at our min on all hoses */
		if (start < PCIBIOS_MIN_MEM + hose->mem_resource->start)
			start = PCIBIOS_MIN_MEM + hose->mem_resource->start;
	}

	return start;
}

static void __devinit pcibios_scanbus(struct pci_controller *hose)
{
	static int next_busno;
	static int need_domain_info;
	struct pci_bus *bus;

	if (!hose->iommu)
		PCI_DMA_BUS_IS_PHYS = 1;

	if (hose->get_busno && pci_probe_only)
		next_busno = (*hose->get_busno)();

	bus = pci_scan_bus(next_busno, hose->pci_ops, hose);
	hose->bus = bus;

	need_domain_info = need_domain_info || hose->index;
	hose->need_domain_info = need_domain_info;
	if (bus) {
		next_busno = bus->subordinate + 1;
		/* Don't allow 8-bit bus number overflow inside the hose -
		   reserve some space for bridges. */
		if (next_busno > 224) {
			next_busno = 0;
			need_domain_info = 1;
		}

		if (!pci_probe_only) {
			pci_bus_size_bridges(bus);
			pci_bus_assign_resources(bus);
			pci_enable_bridges(bus);
		}
	}
}

static DEFINE_MUTEX(pci_scan_mutex);

void __devinit register_pci_controller(struct pci_controller *hose)
{
	if (request_resource(&iomem_resource, hose->mem_resource) < 0)
		goto out;
	if (request_resource(&ioport_resource, hose->io_resource) < 0) {
		release_resource(hose->mem_resource);
		goto out;
	}

	*hose_tail = hose;
	hose_tail = &hose->next;

	/*
	 * Do not panic here but later - this might hapen before console init.
	 */
	if (!hose->io_map_base) {
		printk(KERN_WARNING
		       "registering PCI controller with io_map_base unset\n");
	}

	/*
	 * Scan the bus if it is register after the PCI subsystem
	 * initialization.
	 */
	if (pci_initialized) {
		mutex_lock(&pci_scan_mutex);
		pcibios_scanbus(hose);
		mutex_unlock(&pci_scan_mutex);
	}

	return;

out:
	printk(KERN_WARNING
	       "Skipping PCI bus scan due to resource conflict\n");
}

static int __init pcibios_init(void)
{
	struct pci_controller *hose;

	/* Scan all of the recorded PCI controllers.  */
	for (hose = hose_head; hose; hose = hose->next)
		pcibios_scanbus(hose);

	pci_fixup_irqs(pci_common_swizzle, pcibios_map_irq);

	pci_initialized = 1;

	return 0;
}

subsys_initcall(pcibios_init);

static int pcibios_enable_resources(struct pci_dev *dev, int mask)
{
	u16 cmd, old_cmd;
	int idx;
	struct resource *r;

	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	old_cmd = cmd;
	for (idx=0; idx < PCI_NUM_RESOURCES; idx++) {
		/* Only set up the requested stuff */
		if (!(mask & (1<<idx)))
			continue;

		r = &dev->resource[idx];
		if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
			continue;
		if ((idx == PCI_ROM_RESOURCE) &&
				(!(r->flags & IORESOURCE_ROM_ENABLE)))
			continue;
		if (!r->start && r->end) {
			printk(KERN_ERR "PCI: Device %s not available "
			       "because of resource collisions\n",
			       pci_name(dev));
			return -EINVAL;
		}
		if (r->flags & IORESOURCE_IO)
			cmd |= PCI_COMMAND_IO;
		if (r->flags & IORESOURCE_MEM)
			cmd |= PCI_COMMAND_MEMORY;
	}
	if (cmd != old_cmd) {
		printk("PCI: Enabling device %s (%04x -> %04x)\n",
		       pci_name(dev), old_cmd, cmd);
		pci_write_config_word(dev, PCI_COMMAND, cmd);
	}
	return 0;
}

/*
 *  If we set up a device for bus mastering, we need to check the latency
 *  timer as certain crappy BIOSes forget to set it properly.
 */
static unsigned int pcibios_max_latency = 255;

void pcibios_set_master(struct pci_dev *dev)
{
	u8 lat;
	pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
	if (lat < 16)
		lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
	else if (lat > pcibios_max_latency)
		lat = pcibios_max_latency;
	else
		return;
	printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n",
	       pci_name(dev), lat);
	pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
}

unsigned int pcibios_assign_all_busses(void)
{
	return (pci_probe & PCI_ASSIGN_ALL_BUSSES) ? 1 : 0;
}

int pcibios_enable_device(struct pci_dev *dev, int mask)
{
	int err;

	if ((err = pcibios_enable_resources(dev, mask)) < 0)
		return err;

	return pcibios_plat_dev_init(dev);
}

static void pcibios_fixup_device_resources(struct pci_dev *dev,
	struct pci_bus *bus)
{
	/* Update device resources.  */
	struct pci_controller *hose = (struct pci_controller *)bus->sysdata;
	unsigned long offset = 0;
	int i;

	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
		if (!dev->resource[i].start)
			continue;
		if (dev->resource[i].flags & IORESOURCE_PCI_FIXED)
			continue;
		if (dev->resource[i].flags & IORESOURCE_IO)
			offset = hose->io_offset;
		else if (dev->resource[i].flags & IORESOURCE_MEM)
			offset = hose->mem_offset;

		dev->resource[i].start += offset;
		dev->resource[i].end += offset;
	}
}

void __devinit pcibios_fixup_bus(struct pci_bus *bus)
{
	/* Propagate hose info into the subordinate devices.  */

	struct pci_controller *hose = bus->sysdata;
	struct list_head *ln;
	struct pci_dev *dev = bus->self;

	if (!dev) {
		bus->resource[0] = hose->io_resource;
		bus->resource[1] = hose->mem_resource;
	} else if (pci_probe_only &&
		   (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
		pci_read_bridge_bases(bus);
		pcibios_fixup_device_resources(dev, bus);
	}

	for (ln = bus->devices.next; ln != &bus->devices; ln = ln->next) {
		dev = pci_dev_b(ln);

		if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
			pcibios_fixup_device_resources(dev, bus);
	}
}

void __init
pcibios_update_irq(struct pci_dev *dev, int irq)
{
	pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
}

void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
			 struct resource *res)
{
	struct pci_controller *hose = (struct pci_controller *)dev->sysdata;
	unsigned long offset = 0;

	if (res->flags & IORESOURCE_IO)
		offset = hose->io_offset;
	else if (res->flags & IORESOURCE_MEM)
		offset = hose->mem_offset;

	region->start = res->start - offset;
	region->end = res->end - offset;
}

void __devinit
pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
			struct pci_bus_region *region)
{
	struct pci_controller *hose = (struct pci_controller *)dev->sysdata;
	unsigned long offset = 0;

	if (res->flags & IORESOURCE_IO)
		offset = hose->io_offset;
	else if (res->flags & IORESOURCE_MEM)
		offset = hose->mem_offset;

	res->start = region->start + offset;
	res->end = region->end + offset;
}

#ifdef CONFIG_HOTPLUG
EXPORT_SYMBOL(pcibios_resource_to_bus);
EXPORT_SYMBOL(pcibios_bus_to_resource);
EXPORT_SYMBOL(PCIBIOS_MIN_IO);
EXPORT_SYMBOL(PCIBIOS_MIN_MEM);
#endif

int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
			enum pci_mmap_state mmap_state, int write_combine)
{
	unsigned long prot;

	/*
	 * I/O space can be accessed via normal processor loads and stores on
	 * this platform but for now we elect not to do this and portable
	 * drivers should not do this anyway.
	 */
	if (mmap_state == pci_mmap_io)
		return -EINVAL;

	/*
	 * Ignore write-combine; for now only return uncached mappings.
	 */
	prot = pgprot_val(vma->vm_page_prot);
	prot = (prot & ~_CACHE_MASK) | _CACHE_UNCACHED;
	vma->vm_page_prot = __pgprot(prot);

	return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
		vma->vm_end - vma->vm_start, vma->vm_page_prot);
}

char * (*pcibios_plat_setup)(char *str) __devinitdata;

char *__devinit pcibios_setup(char *str)
{
	if (pcibios_plat_setup)
		return pcibios_plat_setup(str);
	return str;
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This program is free software; you can redistribute it and/or modify it
	3	* under the terms of the GNU General Public License as published by the
	4	* Free Software Foundation; either version 2 of the License, or (at your
	5	* option) any later version.
	6	*
	7	* Copyright (C) 2003, 04 Ralf Baechle (ralf@linux-mips.org)
	8	*/
1da177e4 LT	9	#include <linux/kernel.h>
	10	#include <linux/mm.h>
	11	#include <linux/bootmem.h>
	12	#include <linux/init.h>
	13	#include <linux/types.h>
	14	#include <linux/pci.h>
	15
	16	/*
	17	* Indicate whether we respect the PCI setup left by the firmware.
	18	*
	19	* Make this long-lived so that we know when shutting down
	20	* whether we probed only or not.
	21	*/
	22	int pci_probe_only;
	23
	24	#define PCI_ASSIGN_ALL_BUSSES 1
	25
	26	unsigned int pci_probe = PCI_ASSIGN_ALL_BUSSES;
	27
	28	/*
	29	* The PCI controller list.
	30	*/
	31
d58eaab5	32	static struct pci_controller hose_head, *hose_tail = &hose_head;
1da177e4	33
982f6ffe RB	34	unsigned long PCIBIOS_MIN_IO;
982f6ffe RB	35	unsigned long PCIBIOS_MIN_MEM;
1da177e4	36
540799e3 AJ	37	static int pci_initialized;
540799e3 AJ	38
1da177e4 LT	39	/*
	40	* We need to avoid collisions with `mirrored' VGA ports
	41	* and other strange ISA hardware, so we always want the
	42	* addresses to be allocated in the 0x000-0x0ff region
	43	* modulo 0x400.
	44	*
	45	* Why? Because some silly external IO cards only decode
	46	* the low 10 bits of the IO address. The 0x00-0xff region
	47	* is reserved for motherboard devices that decode all 16
	48	* bits, so it's ok to allocate at, say, 0x2800-0x28ff,
	49	* but we want to try to avoid allocating at 0x2900-0x2bff
	50	* which might have be mirrored at 0x0100-0x03ff..
	51	*/
b26b2d49	52	resource_size_t
1da177e4	53	pcibios_align_resource(void data, struct resource res,
e31dd6e4	54	resource_size_t size, resource_size_t align)
1da177e4 LT	55	{
	56	struct pci_dev *dev = data;
	57	struct pci_controller *hose = dev->sysdata;
e31dd6e4	58	resource_size_t start = res->start;
1da177e4 LT	59
	60	if (res->flags & IORESOURCE_IO) {
	61	/* Make sure we start at our min on all hoses */
	62	if (start < PCIBIOS_MIN_IO + hose->io_resource->start)
	63	start = PCIBIOS_MIN_IO + hose->io_resource->start;
	64
	65	/*
	66	* Put everything into 0x00-0xff region modulo 0x400
	67	*/
	68	if (start & 0x300)
	69	start = (start + 0x3ff) & ~0x3ff;
	70	} else if (res->flags & IORESOURCE_MEM) {
	71	/* Make sure we start at our min on all hoses */
	72	if (start < PCIBIOS_MIN_MEM + hose->mem_resource->start)
	73	start = PCIBIOS_MIN_MEM + hose->mem_resource->start;
	74	}
	75
b26b2d49	76	return start;
1da177e4 LT	77	}
1da177e4 LT	78
540799e3 AJ	79	static void __devinit pcibios_scanbus(struct pci_controller *hose)
	80	{
	81	static int next_busno;
	82	static int need_domain_info;
	83	struct pci_bus *bus;
	84
	85	if (!hose->iommu)
	86	PCI_DMA_BUS_IS_PHYS = 1;
	87
	88	if (hose->get_busno && pci_probe_only)
	89	next_busno = (*hose->get_busno)();
	90
	91	bus = pci_scan_bus(next_busno, hose->pci_ops, hose);
	92	hose->bus = bus;
	93
	94	need_domain_info = need_domain_info \|\| hose->index;
	95	hose->need_domain_info = need_domain_info;
	96	if (bus) {
	97	next_busno = bus->subordinate + 1;
	98	/* Don't allow 8-bit bus number overflow inside the hose -
	99	reserve some space for bridges. */
	100	if (next_busno > 224) {
	101	next_busno = 0;
	102	need_domain_info = 1;
	103	}
	104
	105	if (!pci_probe_only) {
	106	pci_bus_size_bridges(bus);
	107	pci_bus_assign_resources(bus);
	108	pci_enable_bridges(bus);
	109	}
	110	}
	111	}
	112
	113	static DEFINE_MUTEX(pci_scan_mutex);
	114
606bf782	115	void __devinit register_pci_controller(struct pci_controller *hose)
1da177e4	116	{
639702bd TB	117	if (request_resource(&iomem_resource, hose->mem_resource) < 0)
	118	goto out;
	119	if (request_resource(&ioport_resource, hose->io_resource) < 0) {
	120	release_resource(hose->mem_resource);
	121	goto out;
	122	}
	123
1da177e4 LT	124	*hose_tail = hose;
1da177e4 LT	125	hose_tail = &hose->next;
140c1729 RB	126
	127	/*
	128	* Do not panic here but later - this might hapen before console init.
	129	*/
	130	if (!hose->io_map_base) {
	131	printk(KERN_WARNING
	132	"registering PCI controller with io_map_base unset\n");
	133	}
540799e3 AJ	134
	135	/*
	136	* Scan the bus if it is register after the PCI subsystem
	137	* initialization.
	138	*/
	139	if (pci_initialized) {
	140	mutex_lock(&pci_scan_mutex);
	141	pcibios_scanbus(hose);
	142	mutex_unlock(&pci_scan_mutex);
	143	}
	144
639702bd TB	145	return;
	146
	147	out:
	148	printk(KERN_WARNING
	149	"Skipping PCI bus scan due to resource conflict\n");
1da177e4 LT	150	}
1da177e4 LT	151
1da177e4 LT	152	static int __init pcibios_init(void)
	153	{
	154	struct pci_controller *hose;
1da177e4 LT	155
1da177e4 LT	156	/* Scan all of the recorded PCI controllers. */
540799e3 AJ	157	for (hose = hose_head; hose; hose = hose->next)
540799e3 AJ	158	pcibios_scanbus(hose);
1da177e4	159
67eed580	160	pci_fixup_irqs(pci_common_swizzle, pcibios_map_irq);
1da177e4	161
540799e3 AJ	162	pci_initialized = 1;
540799e3 AJ	163
1da177e4 LT	164	return 0;
	165	}
	166
	167	subsys_initcall(pcibios_init);
	168
	169	static int pcibios_enable_resources(struct pci_dev *dev, int mask)
	170	{
	171	u16 cmd, old_cmd;
	172	int idx;
	173	struct resource *r;
	174
	175	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	176	old_cmd = cmd;
e5de3b46	177	for (idx=0; idx < PCI_NUM_RESOURCES; idx++) {
1da177e4 LT	178	/* Only set up the requested stuff */
	179	if (!(mask & (1<<idx)))
	180	continue;
	181
	182	r = &dev->resource[idx];
986c9485 RB	183	if (!(r->flags & (IORESOURCE_IO \| IORESOURCE_MEM)))
	184	continue;
	185	if ((idx == PCI_ROM_RESOURCE) &&
	186	(!(r->flags & IORESOURCE_ROM_ENABLE)))
	187	continue;
1da177e4	188	if (!r->start && r->end) {
40d7c1aa RB	189	printk(KERN_ERR "PCI: Device %s not available "
	190	"because of resource collisions\n",
	191	pci_name(dev));
1da177e4 LT	192	return -EINVAL;
	193	}
	194	if (r->flags & IORESOURCE_IO)
	195	cmd \|= PCI_COMMAND_IO;
	196	if (r->flags & IORESOURCE_MEM)
	197	cmd \|= PCI_COMMAND_MEMORY;
	198	}
1da177e4	199	if (cmd != old_cmd) {
40d7c1aa RB	200	printk("PCI: Enabling device %s (%04x -> %04x)\n",
40d7c1aa RB	201	pci_name(dev), old_cmd, cmd);
1da177e4 LT	202	pci_write_config_word(dev, PCI_COMMAND, cmd);
	203	}
	204	return 0;
	205	}
	206
	207	/*
	208	* If we set up a device for bus mastering, we need to check the latency
	209	* timer as certain crappy BIOSes forget to set it properly.
	210	*/
3450004a	211	static unsigned int pcibios_max_latency = 255;
1da177e4 LT	212
	213	void pcibios_set_master(struct pci_dev *dev)
	214	{
	215	u8 lat;
	216	pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
	217	if (lat < 16)
	218	lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
	219	else if (lat > pcibios_max_latency)
	220	lat = pcibios_max_latency;
	221	else
	222	return;
	223	printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n",
	224	pci_name(dev), lat);
	225	pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
	226	}
	227
	228	unsigned int pcibios_assign_all_busses(void)
	229	{
	230	return (pci_probe & PCI_ASSIGN_ALL_BUSSES) ? 1 : 0;
	231	}
	232
	233	int pcibios_enable_device(struct pci_dev *dev, int mask)
	234	{
	235	int err;
	236
	237	if ((err = pcibios_enable_resources(dev, mask)) < 0)
	238	return err;
	239
	240	return pcibios_plat_dev_init(dev);
	241	}
	242
c4aa2563	243	static void pcibios_fixup_device_resources(struct pci_dev *dev,
1da177e4 LT	244	struct pci_bus *bus)
	245	{
	246	/* Update device resources. */
	247	struct pci_controller hose = (struct pci_controller )bus->sysdata;
	248	unsigned long offset = 0;
	249	int i;
	250
	251	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
	252	if (!dev->resource[i].start)
	253	continue;
d20e47e1 RB	254	if (dev->resource[i].flags & IORESOURCE_PCI_FIXED)
d20e47e1 RB	255	continue;
1da177e4 LT	256	if (dev->resource[i].flags & IORESOURCE_IO)
	257	offset = hose->io_offset;
	258	else if (dev->resource[i].flags & IORESOURCE_MEM)
	259	offset = hose->mem_offset;
	260
	261	dev->resource[i].start += offset;
	262	dev->resource[i].end += offset;
	263	}
	264	}
	265
234fcd14	266	void __devinit pcibios_fixup_bus(struct pci_bus *bus)
1da177e4 LT	267	{
	268	/* Propagate hose info into the subordinate devices. */
	269
	270	struct pci_controller *hose = bus->sysdata;
	271	struct list_head *ln;
	272	struct pci_dev *dev = bus->self;
	273
	274	if (!dev) {
	275	bus->resource[0] = hose->io_resource;
	276	bus->resource[1] = hose->mem_resource;
	277	} else if (pci_probe_only &&
	278	(dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
	279	pci_read_bridge_bases(bus);
	280	pcibios_fixup_device_resources(dev, bus);
42a3b4f2	281	}
1da177e4 LT	282
1da177e4 LT	283	for (ln = bus->devices.next; ln != &bus->devices; ln = ln->next) {
8ed07a1c	284	dev = pci_dev_b(ln);
1da177e4 LT	285
	286	if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
	287	pcibios_fixup_device_resources(dev, bus);
	288	}
	289	}
	290
	291	void __init
	292	pcibios_update_irq(struct pci_dev *dev, int irq)
	293	{
	294	pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
	295	}
	296
c4aa2563	297	void pcibios_resource_to_bus(struct pci_dev dev, struct pci_bus_region region,
1da177e4 LT	298	struct resource *res)
	299	{
	300	struct pci_controller hose = (struct pci_controller )dev->sysdata;
	301	unsigned long offset = 0;
	302
	303	if (res->flags & IORESOURCE_IO)
	304	offset = hose->io_offset;
	305	else if (res->flags & IORESOURCE_MEM)
	306	offset = hose->mem_offset;
	307
	308	region->start = res->start - offset;
	309	region->end = res->end - offset;
	310	}
	311
e63ea56f YY	312	void __devinit
	313	pcibios_bus_to_resource(struct pci_dev dev, struct resource res,
	314	struct pci_bus_region *region)
	315	{
	316	struct pci_controller hose = (struct pci_controller )dev->sysdata;
	317	unsigned long offset = 0;
	318
	319	if (res->flags & IORESOURCE_IO)
	320	offset = hose->io_offset;
	321	else if (res->flags & IORESOURCE_MEM)
	322	offset = hose->mem_offset;
	323
	324	res->start = region->start + offset;
	325	res->end = region->end + offset;
	326	}
	327
1da177e4 LT	328	#ifdef CONFIG_HOTPLUG
1da177e4 LT	329	EXPORT_SYMBOL(pcibios_resource_to_bus);
e63ea56f	330	EXPORT_SYMBOL(pcibios_bus_to_resource);
1da177e4 LT	331	EXPORT_SYMBOL(PCIBIOS_MIN_IO);
	332	EXPORT_SYMBOL(PCIBIOS_MIN_MEM);
	333	#endif
	334
98873f53 RB	335	int pci_mmap_page_range(struct pci_dev dev, struct vm_area_struct vma,
	336	enum pci_mmap_state mmap_state, int write_combine)
	337	{
	338	unsigned long prot;
	339
	340	/*
	341	* I/O space can be accessed via normal processor loads and stores on
	342	* this platform but for now we elect not to do this and portable
	343	* drivers should not do this anyway.
	344	*/
	345	if (mmap_state == pci_mmap_io)
	346	return -EINVAL;
	347
	348	/*
	349	* Ignore write-combine; for now only return uncached mappings.
	350	*/
	351	prot = pgprot_val(vma->vm_page_prot);
	352	prot = (prot & ~_CACHE_MASK) \| _CACHE_UNCACHED;
	353	vma->vm_page_prot = __pgprot(prot);
	354
	355	return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
	356	vma->vm_end - vma->vm_start, vma->vm_page_prot);
	357	}
	358
47a5c976 AN	359	char * (pcibios_plat_setup)(char str) __devinitdata;
	360
	361	char __devinit pcibios_setup(char str)
1da177e4	362	{
47a5c976 AN	363	if (pcibios_plat_setup)
47a5c976 AN	364	return pcibios_plat_setup(str);
1da177e4 LT	365	return str;
1da177e4 LT	366	}