Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Cobalt Qube/Raq PCI support | |
3 | * | |
4 | * This file is subject to the terms and conditions of the GNU General Public | |
5 | * License. See the file "COPYING" in the main directory of this archive | |
6 | * for more details. | |
7 | * | |
8 | * Copyright (C) 1995, 1996, 1997, 2002, 2003 by Ralf Baechle | |
9 | * Copyright (C) 2001, 2002, 2003 by Liam Davies (ldavies@agile.tv) | |
10 | */ | |
11 | #include <linux/types.h> | |
12 | #include <linux/pci.h> | |
13 | #include <linux/kernel.h> | |
14 | #include <linux/init.h> | |
15 | ||
16 | #include <asm/pci.h> | |
17 | #include <asm/io.h> | |
18 | #include <asm/gt64120.h> | |
19 | ||
44320f2b | 20 | #include <cobalt.h> |
1da177e4 | 21 | |
c4ed38a0 RB |
22 | static void qube_raq_galileo_early_fixup(struct pci_dev *dev) |
23 | { | |
24 | if (dev->devfn == PCI_DEVFN(0, 0) && | |
25 | (dev->class >> 8) == PCI_CLASS_MEMORY_OTHER) { | |
26 | ||
27 | dev->class = (PCI_CLASS_BRIDGE_HOST << 8) | (dev->class & 0xff); | |
28 | ||
29 | printk(KERN_INFO "Galileo: fixed bridge class\n"); | |
30 | } | |
31 | } | |
32 | ||
33 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111, | |
34 | qube_raq_galileo_early_fixup); | |
35 | ||
1da177e4 LT |
36 | static void qube_raq_via_bmIDE_fixup(struct pci_dev *dev) |
37 | { | |
38 | unsigned short cfgword; | |
39 | unsigned char lt; | |
40 | ||
41 | /* Enable Bus Mastering and fast back to back. */ | |
42 | pci_read_config_word(dev, PCI_COMMAND, &cfgword); | |
43 | cfgword |= (PCI_COMMAND_FAST_BACK | PCI_COMMAND_MASTER); | |
44 | pci_write_config_word(dev, PCI_COMMAND, cfgword); | |
45 | ||
46 | /* Enable both ide interfaces. ROM only enables primary one. */ | |
47 | pci_write_config_byte(dev, 0x40, 0xb); | |
48 | ||
49 | /* Set latency timer to reasonable value. */ | |
50 | pci_read_config_byte(dev, PCI_LATENCY_TIMER, <); | |
51 | if (lt < 64) | |
52 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64); | |
52378445 | 53 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8); |
1da177e4 LT |
54 | } |
55 | ||
56 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, | |
57 | qube_raq_via_bmIDE_fixup); | |
58 | ||
59 | static void qube_raq_galileo_fixup(struct pci_dev *dev) | |
60 | { | |
c4ed38a0 RB |
61 | if (dev->devfn != PCI_DEVFN(0, 0)) |
62 | return; | |
63 | ||
1da177e4 LT |
64 | /* Fix PCI latency-timer and cache-line-size values in Galileo |
65 | * host bridge. | |
66 | */ | |
67 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64); | |
52378445 | 68 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8); |
1da177e4 LT |
69 | |
70 | /* | |
c4ed38a0 RB |
71 | * The code described by the comment below has been removed |
72 | * as it causes bus mastering by the Ethernet controllers | |
73 | * to break under any kind of network load. We always set | |
74 | * the retry timeouts to their maximum. | |
75 | * | |
76 | * --x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x-- | |
77 | * | |
1da177e4 LT |
78 | * On all machines prior to Q2, we had the STOP line disconnected |
79 | * from Galileo to VIA on PCI. The new Galileo does not function | |
80 | * correctly unless we have it connected. | |
81 | * | |
82 | * Therefore we must set the disconnect/retry cycle values to | |
83 | * something sensible when using the new Galileo. | |
84 | */ | |
c4ed38a0 | 85 | |
44c10138 | 86 | printk(KERN_INFO "Galileo: revision %u\n", dev->revision); |
c4ed38a0 RB |
87 | |
88 | #if 0 | |
44c10138 | 89 | if (dev->revision >= 0x10) { |
1da177e4 | 90 | /* New Galileo, assumes PCI stop line to VIA is connected. */ |
56ae5833 | 91 | GT_WRITE(GT_PCI0_TOR_OFS, 0x4020); |
44c10138 | 92 | } else if (dev->revision == 0x1 || dev->revision == 0x2) |
c4ed38a0 RB |
93 | #endif |
94 | { | |
1da177e4 LT |
95 | signed int timeo; |
96 | /* XXX WE MUST DO THIS ELSE GALILEO LOCKS UP! -DaveM */ | |
56ae5833 | 97 | timeo = GT_READ(GT_PCI0_TOR_OFS); |
1da177e4 | 98 | /* Old Galileo, assumes PCI STOP line to VIA is disconnected. */ |
56ae5833 | 99 | GT_WRITE(GT_PCI0_TOR_OFS, |
c4ed38a0 RB |
100 | (0xff << 16) | /* retry count */ |
101 | (0xff << 8) | /* timeout 1 */ | |
56ae5833 | 102 | 0xff); /* timeout 0 */ |
c4ed38a0 RB |
103 | |
104 | /* enable PCI retry exceeded interrupt */ | |
56ae5833 | 105 | GT_WRITE(GT_INTRMASK_OFS, GT_INTR_RETRYCTR0_MSK | GT_READ(GT_INTRMASK_OFS)); |
1da177e4 LT |
106 | } |
107 | } | |
108 | ||
c4ed38a0 | 109 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111, |
1da177e4 LT |
110 | qube_raq_galileo_fixup); |
111 | ||
3f2d560e YY |
112 | int cobalt_board_id; |
113 | ||
114 | static void qube_raq_via_board_id_fixup(struct pci_dev *dev) | |
115 | { | |
116 | u8 id; | |
117 | int retval; | |
118 | ||
119 | retval = pci_read_config_byte(dev, VIA_COBALT_BRD_ID_REG, &id); | |
120 | if (retval) { | |
121 | panic("Cannot read board ID"); | |
122 | return; | |
123 | } | |
124 | ||
125 | cobalt_board_id = VIA_COBALT_BRD_REG_to_ID(id); | |
126 | ||
127 | printk(KERN_INFO "Cobalt board ID: %d\n", cobalt_board_id); | |
128 | } | |
129 | ||
130 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, | |
131 | qube_raq_via_board_id_fixup); | |
132 | ||
c4ed38a0 RB |
133 | static char irq_tab_qube1[] __initdata = { |
134 | [COBALT_PCICONF_CPU] = 0, | |
135 | [COBALT_PCICONF_ETH0] = COBALT_QUBE1_ETH0_IRQ, | |
136 | [COBALT_PCICONF_RAQSCSI] = COBALT_SCSI_IRQ, | |
137 | [COBALT_PCICONF_VIA] = 0, | |
138 | [COBALT_PCICONF_PCISLOT] = COBALT_QUBE_SLOT_IRQ, | |
139 | [COBALT_PCICONF_ETH1] = 0 | |
140 | }; | |
141 | ||
1da177e4 LT |
142 | static char irq_tab_cobalt[] __initdata = { |
143 | [COBALT_PCICONF_CPU] = 0, | |
144 | [COBALT_PCICONF_ETH0] = COBALT_ETH0_IRQ, | |
145 | [COBALT_PCICONF_RAQSCSI] = COBALT_SCSI_IRQ, | |
146 | [COBALT_PCICONF_VIA] = 0, | |
147 | [COBALT_PCICONF_PCISLOT] = COBALT_QUBE_SLOT_IRQ, | |
148 | [COBALT_PCICONF_ETH1] = COBALT_ETH1_IRQ | |
149 | }; | |
150 | ||
151 | static char irq_tab_raq2[] __initdata = { | |
152 | [COBALT_PCICONF_CPU] = 0, | |
153 | [COBALT_PCICONF_ETH0] = COBALT_ETH0_IRQ, | |
154 | [COBALT_PCICONF_RAQSCSI] = COBALT_RAQ_SCSI_IRQ, | |
155 | [COBALT_PCICONF_VIA] = 0, | |
156 | [COBALT_PCICONF_PCISLOT] = COBALT_QUBE_SLOT_IRQ, | |
157 | [COBALT_PCICONF_ETH1] = COBALT_ETH1_IRQ | |
158 | }; | |
159 | ||
19df0d11 | 160 | int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) |
1da177e4 | 161 | { |
c4ed38a0 RB |
162 | if (cobalt_board_id < COBALT_BRD_ID_QUBE2) |
163 | return irq_tab_qube1[slot]; | |
164 | ||
1da177e4 LT |
165 | if (cobalt_board_id == COBALT_BRD_ID_RAQ2) |
166 | return irq_tab_raq2[slot]; | |
167 | ||
168 | return irq_tab_cobalt[slot]; | |
169 | } | |
170 | ||
171 | /* Do platform specific device initialization at pci_enable_device() time */ | |
172 | int pcibios_plat_dev_init(struct pci_dev *dev) | |
173 | { | |
174 | return 0; | |
175 | } |