Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) | |
7 | * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org) | |
8 | * Copyright (C) 1999, 2000 Silicon Graphics, Inc. | |
9 | */ | |
a754f708 | 10 | #include <linux/hardirq.h> |
1da177e4 | 11 | #include <linux/init.h> |
db813fe5 | 12 | #include <linux/highmem.h> |
1da177e4 | 13 | #include <linux/kernel.h> |
641e97f3 | 14 | #include <linux/linkage.h> |
1da177e4 LT |
15 | #include <linux/sched.h> |
16 | #include <linux/mm.h> | |
17 | #include <linux/bitops.h> | |
18 | ||
19 | #include <asm/bcache.h> | |
20 | #include <asm/bootinfo.h> | |
ec74e361 | 21 | #include <asm/cache.h> |
1da177e4 LT |
22 | #include <asm/cacheops.h> |
23 | #include <asm/cpu.h> | |
24 | #include <asm/cpu-features.h> | |
25 | #include <asm/io.h> | |
26 | #include <asm/page.h> | |
27 | #include <asm/pgtable.h> | |
28 | #include <asm/r4kcache.h> | |
e001e528 | 29 | #include <asm/sections.h> |
1da177e4 LT |
30 | #include <asm/system.h> |
31 | #include <asm/mmu_context.h> | |
32 | #include <asm/war.h> | |
ba5187db | 33 | #include <asm/cacheflush.h> /* for run_uncached() */ |
1da177e4 | 34 | |
7f3f1d01 RB |
35 | |
36 | /* | |
37 | * Special Variant of smp_call_function for use by cache functions: | |
38 | * | |
39 | * o No return value | |
40 | * o collapses to normal function call on UP kernels | |
41 | * o collapses to normal function call on systems with a single shared | |
42 | * primary cache. | |
43 | */ | |
44 | static inline void r4k_on_each_cpu(void (*func) (void *info), void *info, | |
45 | int retry, int wait) | |
46 | { | |
47 | preempt_disable(); | |
48 | ||
49 | #if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC) | |
50 | smp_call_function(func, info, retry, wait); | |
51 | #endif | |
52 | func(info); | |
53 | preempt_enable(); | |
54 | } | |
55 | ||
ec74e361 RB |
56 | /* |
57 | * Must die. | |
58 | */ | |
59 | static unsigned long icache_size __read_mostly; | |
60 | static unsigned long dcache_size __read_mostly; | |
61 | static unsigned long scache_size __read_mostly; | |
1da177e4 LT |
62 | |
63 | /* | |
64 | * Dummy cache handling routines for machines without boardcaches | |
65 | */ | |
73f40352 | 66 | static void cache_noop(void) {} |
1da177e4 LT |
67 | |
68 | static struct bcache_ops no_sc_ops = { | |
73f40352 CD |
69 | .bc_enable = (void *)cache_noop, |
70 | .bc_disable = (void *)cache_noop, | |
71 | .bc_wback_inv = (void *)cache_noop, | |
72 | .bc_inv = (void *)cache_noop | |
1da177e4 LT |
73 | }; |
74 | ||
75 | struct bcache_ops *bcops = &no_sc_ops; | |
76 | ||
330cfe01 TS |
77 | #define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x00002010) |
78 | #define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x00002020) | |
1da177e4 LT |
79 | |
80 | #define R4600_HIT_CACHEOP_WAR_IMPL \ | |
81 | do { \ | |
82 | if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) \ | |
83 | *(volatile unsigned long *)CKSEG1; \ | |
84 | if (R4600_V1_HIT_CACHEOP_WAR) \ | |
85 | __asm__ __volatile__("nop;nop;nop;nop"); \ | |
86 | } while (0) | |
87 | ||
88 | static void (*r4k_blast_dcache_page)(unsigned long addr); | |
89 | ||
90 | static inline void r4k_blast_dcache_page_dc32(unsigned long addr) | |
91 | { | |
92 | R4600_HIT_CACHEOP_WAR_IMPL; | |
93 | blast_dcache32_page(addr); | |
94 | } | |
95 | ||
234fcd14 | 96 | static void __cpuinit r4k_blast_dcache_page_setup(void) |
1da177e4 LT |
97 | { |
98 | unsigned long dc_lsize = cpu_dcache_line_size(); | |
99 | ||
73f40352 CD |
100 | if (dc_lsize == 0) |
101 | r4k_blast_dcache_page = (void *)cache_noop; | |
102 | else if (dc_lsize == 16) | |
1da177e4 LT |
103 | r4k_blast_dcache_page = blast_dcache16_page; |
104 | else if (dc_lsize == 32) | |
105 | r4k_blast_dcache_page = r4k_blast_dcache_page_dc32; | |
106 | } | |
107 | ||
108 | static void (* r4k_blast_dcache_page_indexed)(unsigned long addr); | |
109 | ||
234fcd14 | 110 | static void __cpuinit r4k_blast_dcache_page_indexed_setup(void) |
1da177e4 LT |
111 | { |
112 | unsigned long dc_lsize = cpu_dcache_line_size(); | |
113 | ||
73f40352 CD |
114 | if (dc_lsize == 0) |
115 | r4k_blast_dcache_page_indexed = (void *)cache_noop; | |
116 | else if (dc_lsize == 16) | |
1da177e4 LT |
117 | r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed; |
118 | else if (dc_lsize == 32) | |
119 | r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed; | |
120 | } | |
121 | ||
122 | static void (* r4k_blast_dcache)(void); | |
123 | ||
234fcd14 | 124 | static void __cpuinit r4k_blast_dcache_setup(void) |
1da177e4 LT |
125 | { |
126 | unsigned long dc_lsize = cpu_dcache_line_size(); | |
127 | ||
73f40352 CD |
128 | if (dc_lsize == 0) |
129 | r4k_blast_dcache = (void *)cache_noop; | |
130 | else if (dc_lsize == 16) | |
1da177e4 LT |
131 | r4k_blast_dcache = blast_dcache16; |
132 | else if (dc_lsize == 32) | |
133 | r4k_blast_dcache = blast_dcache32; | |
134 | } | |
135 | ||
136 | /* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */ | |
137 | #define JUMP_TO_ALIGN(order) \ | |
138 | __asm__ __volatile__( \ | |
139 | "b\t1f\n\t" \ | |
140 | ".align\t" #order "\n\t" \ | |
141 | "1:\n\t" \ | |
142 | ) | |
143 | #define CACHE32_UNROLL32_ALIGN JUMP_TO_ALIGN(10) /* 32 * 32 = 1024 */ | |
144 | #define CACHE32_UNROLL32_ALIGN2 JUMP_TO_ALIGN(11) | |
145 | ||
146 | static inline void blast_r4600_v1_icache32(void) | |
147 | { | |
148 | unsigned long flags; | |
149 | ||
150 | local_irq_save(flags); | |
151 | blast_icache32(); | |
152 | local_irq_restore(flags); | |
153 | } | |
154 | ||
155 | static inline void tx49_blast_icache32(void) | |
156 | { | |
157 | unsigned long start = INDEX_BASE; | |
158 | unsigned long end = start + current_cpu_data.icache.waysize; | |
159 | unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; | |
160 | unsigned long ws_end = current_cpu_data.icache.ways << | |
161 | current_cpu_data.icache.waybit; | |
162 | unsigned long ws, addr; | |
163 | ||
164 | CACHE32_UNROLL32_ALIGN2; | |
165 | /* I'm in even chunk. blast odd chunks */ | |
42a3b4f2 RB |
166 | for (ws = 0; ws < ws_end; ws += ws_inc) |
167 | for (addr = start + 0x400; addr < end; addr += 0x400 * 2) | |
21a151d8 | 168 | cache32_unroll32(addr|ws, Index_Invalidate_I); |
1da177e4 LT |
169 | CACHE32_UNROLL32_ALIGN; |
170 | /* I'm in odd chunk. blast even chunks */ | |
42a3b4f2 RB |
171 | for (ws = 0; ws < ws_end; ws += ws_inc) |
172 | for (addr = start; addr < end; addr += 0x400 * 2) | |
21a151d8 | 173 | cache32_unroll32(addr|ws, Index_Invalidate_I); |
1da177e4 LT |
174 | } |
175 | ||
176 | static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page) | |
177 | { | |
178 | unsigned long flags; | |
179 | ||
180 | local_irq_save(flags); | |
181 | blast_icache32_page_indexed(page); | |
182 | local_irq_restore(flags); | |
183 | } | |
184 | ||
185 | static inline void tx49_blast_icache32_page_indexed(unsigned long page) | |
186 | { | |
67a3f6de AN |
187 | unsigned long indexmask = current_cpu_data.icache.waysize - 1; |
188 | unsigned long start = INDEX_BASE + (page & indexmask); | |
1da177e4 LT |
189 | unsigned long end = start + PAGE_SIZE; |
190 | unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; | |
191 | unsigned long ws_end = current_cpu_data.icache.ways << | |
192 | current_cpu_data.icache.waybit; | |
193 | unsigned long ws, addr; | |
194 | ||
195 | CACHE32_UNROLL32_ALIGN2; | |
196 | /* I'm in even chunk. blast odd chunks */ | |
42a3b4f2 RB |
197 | for (ws = 0; ws < ws_end; ws += ws_inc) |
198 | for (addr = start + 0x400; addr < end; addr += 0x400 * 2) | |
21a151d8 | 199 | cache32_unroll32(addr|ws, Index_Invalidate_I); |
1da177e4 LT |
200 | CACHE32_UNROLL32_ALIGN; |
201 | /* I'm in odd chunk. blast even chunks */ | |
42a3b4f2 RB |
202 | for (ws = 0; ws < ws_end; ws += ws_inc) |
203 | for (addr = start; addr < end; addr += 0x400 * 2) | |
21a151d8 | 204 | cache32_unroll32(addr|ws, Index_Invalidate_I); |
1da177e4 LT |
205 | } |
206 | ||
207 | static void (* r4k_blast_icache_page)(unsigned long addr); | |
208 | ||
234fcd14 | 209 | static void __cpuinit r4k_blast_icache_page_setup(void) |
1da177e4 LT |
210 | { |
211 | unsigned long ic_lsize = cpu_icache_line_size(); | |
212 | ||
73f40352 CD |
213 | if (ic_lsize == 0) |
214 | r4k_blast_icache_page = (void *)cache_noop; | |
215 | else if (ic_lsize == 16) | |
1da177e4 LT |
216 | r4k_blast_icache_page = blast_icache16_page; |
217 | else if (ic_lsize == 32) | |
218 | r4k_blast_icache_page = blast_icache32_page; | |
219 | else if (ic_lsize == 64) | |
220 | r4k_blast_icache_page = blast_icache64_page; | |
221 | } | |
222 | ||
223 | ||
224 | static void (* r4k_blast_icache_page_indexed)(unsigned long addr); | |
225 | ||
234fcd14 | 226 | static void __cpuinit r4k_blast_icache_page_indexed_setup(void) |
1da177e4 LT |
227 | { |
228 | unsigned long ic_lsize = cpu_icache_line_size(); | |
229 | ||
73f40352 CD |
230 | if (ic_lsize == 0) |
231 | r4k_blast_icache_page_indexed = (void *)cache_noop; | |
232 | else if (ic_lsize == 16) | |
1da177e4 LT |
233 | r4k_blast_icache_page_indexed = blast_icache16_page_indexed; |
234 | else if (ic_lsize == 32) { | |
02fe2c9c | 235 | if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x()) |
1da177e4 LT |
236 | r4k_blast_icache_page_indexed = |
237 | blast_icache32_r4600_v1_page_indexed; | |
02fe2c9c TS |
238 | else if (TX49XX_ICACHE_INDEX_INV_WAR) |
239 | r4k_blast_icache_page_indexed = | |
240 | tx49_blast_icache32_page_indexed; | |
1da177e4 LT |
241 | else |
242 | r4k_blast_icache_page_indexed = | |
243 | blast_icache32_page_indexed; | |
244 | } else if (ic_lsize == 64) | |
245 | r4k_blast_icache_page_indexed = blast_icache64_page_indexed; | |
246 | } | |
247 | ||
248 | static void (* r4k_blast_icache)(void); | |
249 | ||
234fcd14 | 250 | static void __cpuinit r4k_blast_icache_setup(void) |
1da177e4 LT |
251 | { |
252 | unsigned long ic_lsize = cpu_icache_line_size(); | |
253 | ||
73f40352 CD |
254 | if (ic_lsize == 0) |
255 | r4k_blast_icache = (void *)cache_noop; | |
256 | else if (ic_lsize == 16) | |
1da177e4 LT |
257 | r4k_blast_icache = blast_icache16; |
258 | else if (ic_lsize == 32) { | |
259 | if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x()) | |
260 | r4k_blast_icache = blast_r4600_v1_icache32; | |
261 | else if (TX49XX_ICACHE_INDEX_INV_WAR) | |
262 | r4k_blast_icache = tx49_blast_icache32; | |
263 | else | |
264 | r4k_blast_icache = blast_icache32; | |
265 | } else if (ic_lsize == 64) | |
266 | r4k_blast_icache = blast_icache64; | |
267 | } | |
268 | ||
269 | static void (* r4k_blast_scache_page)(unsigned long addr); | |
270 | ||
234fcd14 | 271 | static void __cpuinit r4k_blast_scache_page_setup(void) |
1da177e4 LT |
272 | { |
273 | unsigned long sc_lsize = cpu_scache_line_size(); | |
274 | ||
4debe4f9 | 275 | if (scache_size == 0) |
73f40352 | 276 | r4k_blast_scache_page = (void *)cache_noop; |
4debe4f9 | 277 | else if (sc_lsize == 16) |
1da177e4 LT |
278 | r4k_blast_scache_page = blast_scache16_page; |
279 | else if (sc_lsize == 32) | |
280 | r4k_blast_scache_page = blast_scache32_page; | |
281 | else if (sc_lsize == 64) | |
282 | r4k_blast_scache_page = blast_scache64_page; | |
283 | else if (sc_lsize == 128) | |
284 | r4k_blast_scache_page = blast_scache128_page; | |
285 | } | |
286 | ||
287 | static void (* r4k_blast_scache_page_indexed)(unsigned long addr); | |
288 | ||
234fcd14 | 289 | static void __cpuinit r4k_blast_scache_page_indexed_setup(void) |
1da177e4 LT |
290 | { |
291 | unsigned long sc_lsize = cpu_scache_line_size(); | |
292 | ||
4debe4f9 | 293 | if (scache_size == 0) |
73f40352 | 294 | r4k_blast_scache_page_indexed = (void *)cache_noop; |
4debe4f9 | 295 | else if (sc_lsize == 16) |
1da177e4 LT |
296 | r4k_blast_scache_page_indexed = blast_scache16_page_indexed; |
297 | else if (sc_lsize == 32) | |
298 | r4k_blast_scache_page_indexed = blast_scache32_page_indexed; | |
299 | else if (sc_lsize == 64) | |
300 | r4k_blast_scache_page_indexed = blast_scache64_page_indexed; | |
301 | else if (sc_lsize == 128) | |
302 | r4k_blast_scache_page_indexed = blast_scache128_page_indexed; | |
303 | } | |
304 | ||
305 | static void (* r4k_blast_scache)(void); | |
306 | ||
234fcd14 | 307 | static void __cpuinit r4k_blast_scache_setup(void) |
1da177e4 LT |
308 | { |
309 | unsigned long sc_lsize = cpu_scache_line_size(); | |
310 | ||
4debe4f9 | 311 | if (scache_size == 0) |
73f40352 | 312 | r4k_blast_scache = (void *)cache_noop; |
4debe4f9 | 313 | else if (sc_lsize == 16) |
1da177e4 LT |
314 | r4k_blast_scache = blast_scache16; |
315 | else if (sc_lsize == 32) | |
316 | r4k_blast_scache = blast_scache32; | |
317 | else if (sc_lsize == 64) | |
318 | r4k_blast_scache = blast_scache64; | |
319 | else if (sc_lsize == 128) | |
320 | r4k_blast_scache = blast_scache128; | |
321 | } | |
322 | ||
1da177e4 LT |
323 | static inline void local_r4k___flush_cache_all(void * args) |
324 | { | |
2a21c730 FZ |
325 | #if defined(CONFIG_CPU_LOONGSON2) |
326 | r4k_blast_scache(); | |
327 | return; | |
328 | #endif | |
1da177e4 LT |
329 | r4k_blast_dcache(); |
330 | r4k_blast_icache(); | |
331 | ||
10cc3529 | 332 | switch (current_cpu_type()) { |
1da177e4 LT |
333 | case CPU_R4000SC: |
334 | case CPU_R4000MC: | |
335 | case CPU_R4400SC: | |
336 | case CPU_R4400MC: | |
337 | case CPU_R10000: | |
338 | case CPU_R12000: | |
44d921b2 | 339 | case CPU_R14000: |
1da177e4 LT |
340 | r4k_blast_scache(); |
341 | } | |
342 | } | |
343 | ||
344 | static void r4k___flush_cache_all(void) | |
345 | { | |
7f3f1d01 | 346 | r4k_on_each_cpu(local_r4k___flush_cache_all, NULL, 1, 1); |
1da177e4 LT |
347 | } |
348 | ||
a76ab5c1 RB |
349 | static inline int has_valid_asid(const struct mm_struct *mm) |
350 | { | |
351 | #if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC) | |
352 | int i; | |
353 | ||
354 | for_each_online_cpu(i) | |
355 | if (cpu_context(i, mm)) | |
356 | return 1; | |
357 | ||
358 | return 0; | |
359 | #else | |
360 | return cpu_context(smp_processor_id(), mm); | |
361 | #endif | |
362 | } | |
363 | ||
9c5a3d72 RB |
364 | static void r4k__flush_cache_vmap(void) |
365 | { | |
366 | r4k_blast_dcache(); | |
367 | } | |
368 | ||
369 | static void r4k__flush_cache_vunmap(void) | |
370 | { | |
371 | r4k_blast_dcache(); | |
372 | } | |
373 | ||
1da177e4 LT |
374 | static inline void local_r4k_flush_cache_range(void * args) |
375 | { | |
376 | struct vm_area_struct *vma = args; | |
2eaa7ec2 | 377 | int exec = vma->vm_flags & VM_EXEC; |
1da177e4 | 378 | |
a76ab5c1 | 379 | if (!(has_valid_asid(vma->vm_mm))) |
1da177e4 LT |
380 | return; |
381 | ||
0550d9d1 | 382 | r4k_blast_dcache(); |
2eaa7ec2 RB |
383 | if (exec) |
384 | r4k_blast_icache(); | |
1da177e4 LT |
385 | } |
386 | ||
387 | static void r4k_flush_cache_range(struct vm_area_struct *vma, | |
388 | unsigned long start, unsigned long end) | |
389 | { | |
2eaa7ec2 | 390 | int exec = vma->vm_flags & VM_EXEC; |
0550d9d1 | 391 | |
2eaa7ec2 RB |
392 | if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) |
393 | r4k_on_each_cpu(local_r4k_flush_cache_range, vma, 1, 1); | |
1da177e4 LT |
394 | } |
395 | ||
396 | static inline void local_r4k_flush_cache_mm(void * args) | |
397 | { | |
398 | struct mm_struct *mm = args; | |
399 | ||
a76ab5c1 | 400 | if (!has_valid_asid(mm)) |
1da177e4 LT |
401 | return; |
402 | ||
1da177e4 LT |
403 | /* |
404 | * Kludge alert. For obscure reasons R4000SC and R4400SC go nuts if we | |
405 | * only flush the primary caches but R10000 and R12000 behave sane ... | |
617667ba RB |
406 | * R4000SC and R4400SC indexed S-cache ops also invalidate primary |
407 | * caches, so we can bail out early. | |
1da177e4 | 408 | */ |
10cc3529 RB |
409 | if (current_cpu_type() == CPU_R4000SC || |
410 | current_cpu_type() == CPU_R4000MC || | |
411 | current_cpu_type() == CPU_R4400SC || | |
412 | current_cpu_type() == CPU_R4400MC) { | |
1da177e4 | 413 | r4k_blast_scache(); |
617667ba RB |
414 | return; |
415 | } | |
416 | ||
417 | r4k_blast_dcache(); | |
1da177e4 LT |
418 | } |
419 | ||
420 | static void r4k_flush_cache_mm(struct mm_struct *mm) | |
421 | { | |
422 | if (!cpu_has_dc_aliases) | |
423 | return; | |
424 | ||
7f3f1d01 | 425 | r4k_on_each_cpu(local_r4k_flush_cache_mm, mm, 1, 1); |
1da177e4 LT |
426 | } |
427 | ||
428 | struct flush_cache_page_args { | |
429 | struct vm_area_struct *vma; | |
6ec25809 | 430 | unsigned long addr; |
de62893b | 431 | unsigned long pfn; |
1da177e4 LT |
432 | }; |
433 | ||
434 | static inline void local_r4k_flush_cache_page(void *args) | |
435 | { | |
436 | struct flush_cache_page_args *fcp_args = args; | |
437 | struct vm_area_struct *vma = fcp_args->vma; | |
6ec25809 | 438 | unsigned long addr = fcp_args->addr; |
db813fe5 | 439 | struct page *page = pfn_to_page(fcp_args->pfn); |
1da177e4 LT |
440 | int exec = vma->vm_flags & VM_EXEC; |
441 | struct mm_struct *mm = vma->vm_mm; | |
442 | pgd_t *pgdp; | |
c6e8b587 | 443 | pud_t *pudp; |
1da177e4 LT |
444 | pmd_t *pmdp; |
445 | pte_t *ptep; | |
db813fe5 | 446 | void *vaddr; |
1da177e4 | 447 | |
79acf83e RB |
448 | /* |
449 | * If ownes no valid ASID yet, cannot possibly have gotten | |
450 | * this page into the cache. | |
451 | */ | |
a76ab5c1 | 452 | if (!has_valid_asid(mm)) |
79acf83e RB |
453 | return; |
454 | ||
6ec25809 RB |
455 | addr &= PAGE_MASK; |
456 | pgdp = pgd_offset(mm, addr); | |
457 | pudp = pud_offset(pgdp, addr); | |
458 | pmdp = pmd_offset(pudp, addr); | |
459 | ptep = pte_offset(pmdp, addr); | |
1da177e4 LT |
460 | |
461 | /* | |
462 | * If the page isn't marked valid, the page cannot possibly be | |
463 | * in the cache. | |
464 | */ | |
526af35e | 465 | if (!(pte_present(*ptep))) |
1da177e4 LT |
466 | return; |
467 | ||
db813fe5 RB |
468 | if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) |
469 | vaddr = NULL; | |
470 | else { | |
471 | /* | |
472 | * Use kmap_coherent or kmap_atomic to do flushes for | |
473 | * another ASID than the current one. | |
474 | */ | |
475 | if (cpu_has_dc_aliases) | |
476 | vaddr = kmap_coherent(page, addr); | |
477 | else | |
478 | vaddr = kmap_atomic(page, KM_USER0); | |
479 | addr = (unsigned long)vaddr; | |
1da177e4 LT |
480 | } |
481 | ||
1da177e4 | 482 | if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) { |
db813fe5 | 483 | r4k_blast_dcache_page(addr); |
1da177e4 LT |
484 | } |
485 | if (exec) { | |
db813fe5 | 486 | if (vaddr && cpu_has_vtag_icache && mm == current->active_mm) { |
1da177e4 LT |
487 | int cpu = smp_processor_id(); |
488 | ||
26a51b27 TS |
489 | if (cpu_context(cpu, mm) != 0) |
490 | drop_mmu_context(mm, cpu); | |
1da177e4 | 491 | } else |
db813fe5 RB |
492 | r4k_blast_icache_page(addr); |
493 | } | |
494 | ||
495 | if (vaddr) { | |
496 | if (cpu_has_dc_aliases) | |
497 | kunmap_coherent(); | |
498 | else | |
499 | kunmap_atomic(vaddr, KM_USER0); | |
1da177e4 LT |
500 | } |
501 | } | |
502 | ||
6ec25809 RB |
503 | static void r4k_flush_cache_page(struct vm_area_struct *vma, |
504 | unsigned long addr, unsigned long pfn) | |
1da177e4 LT |
505 | { |
506 | struct flush_cache_page_args args; | |
507 | ||
1da177e4 | 508 | args.vma = vma; |
6ec25809 | 509 | args.addr = addr; |
de62893b | 510 | args.pfn = pfn; |
1da177e4 | 511 | |
7f3f1d01 | 512 | r4k_on_each_cpu(local_r4k_flush_cache_page, &args, 1, 1); |
1da177e4 LT |
513 | } |
514 | ||
515 | static inline void local_r4k_flush_data_cache_page(void * addr) | |
516 | { | |
517 | r4k_blast_dcache_page((unsigned long) addr); | |
518 | } | |
519 | ||
520 | static void r4k_flush_data_cache_page(unsigned long addr) | |
521 | { | |
a754f708 RB |
522 | if (in_atomic()) |
523 | local_r4k_flush_data_cache_page((void *)addr); | |
524 | else | |
525 | r4k_on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr, | |
526 | 1, 1); | |
1da177e4 LT |
527 | } |
528 | ||
529 | struct flush_icache_range_args { | |
d4264f18 AN |
530 | unsigned long start; |
531 | unsigned long end; | |
1da177e4 LT |
532 | }; |
533 | ||
534 | static inline void local_r4k_flush_icache_range(void *args) | |
535 | { | |
536 | struct flush_icache_range_args *fir_args = args; | |
1da177e4 LT |
537 | unsigned long start = fir_args->start; |
538 | unsigned long end = fir_args->end; | |
1da177e4 LT |
539 | |
540 | if (!cpu_has_ic_fills_f_dc) { | |
73f40352 | 541 | if (end - start >= dcache_size) { |
1da177e4 LT |
542 | r4k_blast_dcache(); |
543 | } else { | |
10a3dabd | 544 | R4600_HIT_CACHEOP_WAR_IMPL; |
41700e73 | 545 | protected_blast_dcache_range(start, end); |
1da177e4 | 546 | } |
1da177e4 LT |
547 | } |
548 | ||
549 | if (end - start > icache_size) | |
550 | r4k_blast_icache(); | |
41700e73 AN |
551 | else |
552 | protected_blast_icache_range(start, end); | |
1da177e4 LT |
553 | } |
554 | ||
d4264f18 | 555 | static void r4k_flush_icache_range(unsigned long start, unsigned long end) |
1da177e4 LT |
556 | { |
557 | struct flush_icache_range_args args; | |
558 | ||
559 | args.start = start; | |
560 | args.end = end; | |
561 | ||
7f3f1d01 | 562 | r4k_on_each_cpu(local_r4k_flush_icache_range, &args, 1, 1); |
cc61c1fe | 563 | instruction_hazard(); |
1da177e4 LT |
564 | } |
565 | ||
1da177e4 LT |
566 | #ifdef CONFIG_DMA_NONCOHERENT |
567 | ||
568 | static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size) | |
569 | { | |
1da177e4 LT |
570 | /* Catch bad driver code */ |
571 | BUG_ON(size == 0); | |
572 | ||
fc5d2d27 | 573 | if (cpu_has_inclusive_pcaches) { |
41700e73 | 574 | if (size >= scache_size) |
1da177e4 | 575 | r4k_blast_scache(); |
41700e73 AN |
576 | else |
577 | blast_scache_range(addr, addr + size); | |
1da177e4 LT |
578 | return; |
579 | } | |
580 | ||
581 | /* | |
582 | * Either no secondary cache or the available caches don't have the | |
583 | * subset property so we have to flush the primary caches | |
584 | * explicitly | |
585 | */ | |
586 | if (size >= dcache_size) { | |
587 | r4k_blast_dcache(); | |
588 | } else { | |
1da177e4 | 589 | R4600_HIT_CACHEOP_WAR_IMPL; |
41700e73 | 590 | blast_dcache_range(addr, addr + size); |
1da177e4 LT |
591 | } |
592 | ||
593 | bc_wback_inv(addr, size); | |
594 | } | |
595 | ||
596 | static void r4k_dma_cache_inv(unsigned long addr, unsigned long size) | |
597 | { | |
1da177e4 LT |
598 | /* Catch bad driver code */ |
599 | BUG_ON(size == 0); | |
600 | ||
fc5d2d27 | 601 | if (cpu_has_inclusive_pcaches) { |
41700e73 | 602 | if (size >= scache_size) |
1da177e4 | 603 | r4k_blast_scache(); |
41700e73 | 604 | else |
e9c33572 | 605 | blast_inv_scache_range(addr, addr + size); |
1da177e4 LT |
606 | return; |
607 | } | |
608 | ||
609 | if (size >= dcache_size) { | |
610 | r4k_blast_dcache(); | |
611 | } else { | |
1da177e4 | 612 | R4600_HIT_CACHEOP_WAR_IMPL; |
e9c33572 | 613 | blast_inv_dcache_range(addr, addr + size); |
1da177e4 LT |
614 | } |
615 | ||
616 | bc_inv(addr, size); | |
617 | } | |
618 | #endif /* CONFIG_DMA_NONCOHERENT */ | |
619 | ||
620 | /* | |
621 | * While we're protected against bad userland addresses we don't care | |
622 | * very much about what happens in that case. Usually a segmentation | |
623 | * fault will dump the process later on anyway ... | |
624 | */ | |
625 | static void local_r4k_flush_cache_sigtramp(void * arg) | |
626 | { | |
02fe2c9c TS |
627 | unsigned long ic_lsize = cpu_icache_line_size(); |
628 | unsigned long dc_lsize = cpu_dcache_line_size(); | |
629 | unsigned long sc_lsize = cpu_scache_line_size(); | |
1da177e4 LT |
630 | unsigned long addr = (unsigned long) arg; |
631 | ||
632 | R4600_HIT_CACHEOP_WAR_IMPL; | |
73f40352 CD |
633 | if (dc_lsize) |
634 | protected_writeback_dcache_line(addr & ~(dc_lsize - 1)); | |
4debe4f9 | 635 | if (!cpu_icache_snoops_remote_store && scache_size) |
1da177e4 | 636 | protected_writeback_scache_line(addr & ~(sc_lsize - 1)); |
73f40352 CD |
637 | if (ic_lsize) |
638 | protected_flush_icache_line(addr & ~(ic_lsize - 1)); | |
1da177e4 LT |
639 | if (MIPS4K_ICACHE_REFILL_WAR) { |
640 | __asm__ __volatile__ ( | |
641 | ".set push\n\t" | |
642 | ".set noat\n\t" | |
643 | ".set mips3\n\t" | |
875d43e7 | 644 | #ifdef CONFIG_32BIT |
1da177e4 LT |
645 | "la $at,1f\n\t" |
646 | #endif | |
875d43e7 | 647 | #ifdef CONFIG_64BIT |
1da177e4 LT |
648 | "dla $at,1f\n\t" |
649 | #endif | |
650 | "cache %0,($at)\n\t" | |
651 | "nop; nop; nop\n" | |
652 | "1:\n\t" | |
653 | ".set pop" | |
654 | : | |
655 | : "i" (Hit_Invalidate_I)); | |
656 | } | |
657 | if (MIPS_CACHE_SYNC_WAR) | |
658 | __asm__ __volatile__ ("sync"); | |
659 | } | |
660 | ||
661 | static void r4k_flush_cache_sigtramp(unsigned long addr) | |
662 | { | |
7f3f1d01 | 663 | r4k_on_each_cpu(local_r4k_flush_cache_sigtramp, (void *) addr, 1, 1); |
1da177e4 LT |
664 | } |
665 | ||
666 | static void r4k_flush_icache_all(void) | |
667 | { | |
668 | if (cpu_has_vtag_icache) | |
669 | r4k_blast_icache(); | |
670 | } | |
671 | ||
672 | static inline void rm7k_erratum31(void) | |
673 | { | |
674 | const unsigned long ic_lsize = 32; | |
675 | unsigned long addr; | |
676 | ||
677 | /* RM7000 erratum #31. The icache is screwed at startup. */ | |
678 | write_c0_taglo(0); | |
679 | write_c0_taghi(0); | |
680 | ||
681 | for (addr = INDEX_BASE; addr <= INDEX_BASE + 4096; addr += ic_lsize) { | |
682 | __asm__ __volatile__ ( | |
d8748a3a | 683 | ".set push\n\t" |
1da177e4 LT |
684 | ".set noreorder\n\t" |
685 | ".set mips3\n\t" | |
686 | "cache\t%1, 0(%0)\n\t" | |
687 | "cache\t%1, 0x1000(%0)\n\t" | |
688 | "cache\t%1, 0x2000(%0)\n\t" | |
689 | "cache\t%1, 0x3000(%0)\n\t" | |
690 | "cache\t%2, 0(%0)\n\t" | |
691 | "cache\t%2, 0x1000(%0)\n\t" | |
692 | "cache\t%2, 0x2000(%0)\n\t" | |
693 | "cache\t%2, 0x3000(%0)\n\t" | |
694 | "cache\t%1, 0(%0)\n\t" | |
695 | "cache\t%1, 0x1000(%0)\n\t" | |
696 | "cache\t%1, 0x2000(%0)\n\t" | |
697 | "cache\t%1, 0x3000(%0)\n\t" | |
d8748a3a | 698 | ".set pop\n" |
1da177e4 LT |
699 | : |
700 | : "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill)); | |
701 | } | |
702 | } | |
703 | ||
234fcd14 | 704 | static char *way_string[] __cpuinitdata = { NULL, "direct mapped", "2-way", |
1da177e4 LT |
705 | "3-way", "4-way", "5-way", "6-way", "7-way", "8-way" |
706 | }; | |
707 | ||
234fcd14 | 708 | static void __cpuinit probe_pcache(void) |
1da177e4 LT |
709 | { |
710 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
711 | unsigned int config = read_c0_config(); | |
712 | unsigned int prid = read_c0_prid(); | |
713 | unsigned long config1; | |
714 | unsigned int lsize; | |
715 | ||
716 | switch (c->cputype) { | |
717 | case CPU_R4600: /* QED style two way caches? */ | |
718 | case CPU_R4700: | |
719 | case CPU_R5000: | |
720 | case CPU_NEVADA: | |
721 | icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); | |
722 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | |
723 | c->icache.ways = 2; | |
3c68da79 | 724 | c->icache.waybit = __ffs(icache_size/2); |
1da177e4 LT |
725 | |
726 | dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); | |
727 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | |
728 | c->dcache.ways = 2; | |
3c68da79 | 729 | c->dcache.waybit= __ffs(dcache_size/2); |
1da177e4 LT |
730 | |
731 | c->options |= MIPS_CPU_CACHE_CDEX_P; | |
732 | break; | |
733 | ||
734 | case CPU_R5432: | |
735 | case CPU_R5500: | |
736 | icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); | |
737 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | |
738 | c->icache.ways = 2; | |
739 | c->icache.waybit= 0; | |
740 | ||
741 | dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); | |
742 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | |
743 | c->dcache.ways = 2; | |
744 | c->dcache.waybit = 0; | |
745 | ||
746 | c->options |= MIPS_CPU_CACHE_CDEX_P; | |
747 | break; | |
748 | ||
749 | case CPU_TX49XX: | |
750 | icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); | |
751 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | |
752 | c->icache.ways = 4; | |
753 | c->icache.waybit= 0; | |
754 | ||
755 | dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); | |
756 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | |
757 | c->dcache.ways = 4; | |
758 | c->dcache.waybit = 0; | |
759 | ||
760 | c->options |= MIPS_CPU_CACHE_CDEX_P; | |
de862b48 | 761 | c->options |= MIPS_CPU_PREFETCH; |
1da177e4 LT |
762 | break; |
763 | ||
764 | case CPU_R4000PC: | |
765 | case CPU_R4000SC: | |
766 | case CPU_R4000MC: | |
767 | case CPU_R4400PC: | |
768 | case CPU_R4400SC: | |
769 | case CPU_R4400MC: | |
770 | case CPU_R4300: | |
771 | icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); | |
772 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | |
773 | c->icache.ways = 1; | |
774 | c->icache.waybit = 0; /* doesn't matter */ | |
775 | ||
776 | dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); | |
777 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | |
778 | c->dcache.ways = 1; | |
779 | c->dcache.waybit = 0; /* does not matter */ | |
780 | ||
781 | c->options |= MIPS_CPU_CACHE_CDEX_P; | |
782 | break; | |
783 | ||
784 | case CPU_R10000: | |
785 | case CPU_R12000: | |
44d921b2 | 786 | case CPU_R14000: |
1da177e4 LT |
787 | icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29)); |
788 | c->icache.linesz = 64; | |
789 | c->icache.ways = 2; | |
790 | c->icache.waybit = 0; | |
791 | ||
792 | dcache_size = 1 << (12 + ((config & R10K_CONF_DC) >> 26)); | |
793 | c->dcache.linesz = 32; | |
794 | c->dcache.ways = 2; | |
795 | c->dcache.waybit = 0; | |
796 | ||
797 | c->options |= MIPS_CPU_PREFETCH; | |
798 | break; | |
799 | ||
800 | case CPU_VR4133: | |
2874fe55 | 801 | write_c0_config(config & ~VR41_CONF_P4K); |
1da177e4 LT |
802 | case CPU_VR4131: |
803 | /* Workaround for cache instruction bug of VR4131 */ | |
804 | if (c->processor_id == 0x0c80U || c->processor_id == 0x0c81U || | |
805 | c->processor_id == 0x0c82U) { | |
4e8ab361 YY |
806 | config |= 0x00400000U; |
807 | if (c->processor_id == 0x0c80U) | |
808 | config |= VR41_CONF_BP; | |
1da177e4 | 809 | write_c0_config(config); |
1058ecda YY |
810 | } else |
811 | c->options |= MIPS_CPU_CACHE_CDEX_P; | |
812 | ||
1da177e4 LT |
813 | icache_size = 1 << (10 + ((config & CONF_IC) >> 9)); |
814 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | |
815 | c->icache.ways = 2; | |
3c68da79 | 816 | c->icache.waybit = __ffs(icache_size/2); |
1da177e4 LT |
817 | |
818 | dcache_size = 1 << (10 + ((config & CONF_DC) >> 6)); | |
819 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | |
820 | c->dcache.ways = 2; | |
3c68da79 | 821 | c->dcache.waybit = __ffs(dcache_size/2); |
1da177e4 LT |
822 | break; |
823 | ||
824 | case CPU_VR41XX: | |
825 | case CPU_VR4111: | |
826 | case CPU_VR4121: | |
827 | case CPU_VR4122: | |
828 | case CPU_VR4181: | |
829 | case CPU_VR4181A: | |
830 | icache_size = 1 << (10 + ((config & CONF_IC) >> 9)); | |
831 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | |
832 | c->icache.ways = 1; | |
833 | c->icache.waybit = 0; /* doesn't matter */ | |
834 | ||
835 | dcache_size = 1 << (10 + ((config & CONF_DC) >> 6)); | |
836 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | |
837 | c->dcache.ways = 1; | |
838 | c->dcache.waybit = 0; /* does not matter */ | |
839 | ||
840 | c->options |= MIPS_CPU_CACHE_CDEX_P; | |
841 | break; | |
842 | ||
843 | case CPU_RM7000: | |
844 | rm7k_erratum31(); | |
845 | ||
846 | case CPU_RM9000: | |
847 | icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); | |
848 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | |
849 | c->icache.ways = 4; | |
3c68da79 | 850 | c->icache.waybit = __ffs(icache_size / c->icache.ways); |
1da177e4 LT |
851 | |
852 | dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); | |
853 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | |
854 | c->dcache.ways = 4; | |
3c68da79 | 855 | c->dcache.waybit = __ffs(dcache_size / c->dcache.ways); |
1da177e4 LT |
856 | |
857 | #if !defined(CONFIG_SMP) || !defined(RM9000_CDEX_SMP_WAR) | |
858 | c->options |= MIPS_CPU_CACHE_CDEX_P; | |
859 | #endif | |
860 | c->options |= MIPS_CPU_PREFETCH; | |
861 | break; | |
862 | ||
2a21c730 FZ |
863 | case CPU_LOONGSON2: |
864 | icache_size = 1 << (12 + ((config & CONF_IC) >> 9)); | |
865 | c->icache.linesz = 16 << ((config & CONF_IB) >> 5); | |
866 | if (prid & 0x3) | |
867 | c->icache.ways = 4; | |
868 | else | |
869 | c->icache.ways = 2; | |
870 | c->icache.waybit = 0; | |
871 | ||
872 | dcache_size = 1 << (12 + ((config & CONF_DC) >> 6)); | |
873 | c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); | |
874 | if (prid & 0x3) | |
875 | c->dcache.ways = 4; | |
876 | else | |
877 | c->dcache.ways = 2; | |
878 | c->dcache.waybit = 0; | |
879 | break; | |
880 | ||
1da177e4 LT |
881 | default: |
882 | if (!(config & MIPS_CONF_M)) | |
883 | panic("Don't know how to probe P-caches on this cpu."); | |
884 | ||
885 | /* | |
886 | * So we seem to be a MIPS32 or MIPS64 CPU | |
887 | * So let's probe the I-cache ... | |
888 | */ | |
889 | config1 = read_c0_config1(); | |
890 | ||
891 | if ((lsize = ((config1 >> 19) & 7))) | |
892 | c->icache.linesz = 2 << lsize; | |
893 | else | |
894 | c->icache.linesz = lsize; | |
895 | c->icache.sets = 64 << ((config1 >> 22) & 7); | |
896 | c->icache.ways = 1 + ((config1 >> 16) & 7); | |
897 | ||
898 | icache_size = c->icache.sets * | |
899 | c->icache.ways * | |
900 | c->icache.linesz; | |
3c68da79 | 901 | c->icache.waybit = __ffs(icache_size/c->icache.ways); |
1da177e4 LT |
902 | |
903 | if (config & 0x8) /* VI bit */ | |
904 | c->icache.flags |= MIPS_CACHE_VTAG; | |
905 | ||
906 | /* | |
907 | * Now probe the MIPS32 / MIPS64 data cache. | |
908 | */ | |
909 | c->dcache.flags = 0; | |
910 | ||
911 | if ((lsize = ((config1 >> 10) & 7))) | |
912 | c->dcache.linesz = 2 << lsize; | |
913 | else | |
914 | c->dcache.linesz= lsize; | |
915 | c->dcache.sets = 64 << ((config1 >> 13) & 7); | |
916 | c->dcache.ways = 1 + ((config1 >> 7) & 7); | |
917 | ||
918 | dcache_size = c->dcache.sets * | |
919 | c->dcache.ways * | |
920 | c->dcache.linesz; | |
3c68da79 | 921 | c->dcache.waybit = __ffs(dcache_size/c->dcache.ways); |
1da177e4 LT |
922 | |
923 | c->options |= MIPS_CPU_PREFETCH; | |
924 | break; | |
925 | } | |
926 | ||
927 | /* | |
928 | * Processor configuration sanity check for the R4000SC erratum | |
929 | * #5. With page sizes larger than 32kB there is no possibility | |
930 | * to get a VCE exception anymore so we don't care about this | |
931 | * misconfiguration. The case is rather theoretical anyway; | |
932 | * presumably no vendor is shipping his hardware in the "bad" | |
933 | * configuration. | |
934 | */ | |
935 | if ((prid & 0xff00) == PRID_IMP_R4000 && (prid & 0xff) < 0x40 && | |
936 | !(config & CONF_SC) && c->icache.linesz != 16 && | |
937 | PAGE_SIZE <= 0x8000) | |
938 | panic("Improper R4000SC processor configuration detected"); | |
939 | ||
940 | /* compute a couple of other cache variables */ | |
941 | c->icache.waysize = icache_size / c->icache.ways; | |
942 | c->dcache.waysize = dcache_size / c->dcache.ways; | |
943 | ||
73f40352 CD |
944 | c->icache.sets = c->icache.linesz ? |
945 | icache_size / (c->icache.linesz * c->icache.ways) : 0; | |
946 | c->dcache.sets = c->dcache.linesz ? | |
947 | dcache_size / (c->dcache.linesz * c->dcache.ways) : 0; | |
1da177e4 LT |
948 | |
949 | /* | |
950 | * R10000 and R12000 P-caches are odd in a positive way. They're 32kB | |
951 | * 2-way virtually indexed so normally would suffer from aliases. So | |
952 | * normally they'd suffer from aliases but magic in the hardware deals | |
953 | * with that for us so we don't need to take care ourselves. | |
954 | */ | |
d1e344e5 | 955 | switch (c->cputype) { |
a95970f3 | 956 | case CPU_20KC: |
505403b6 | 957 | case CPU_25KF: |
641e97f3 RB |
958 | case CPU_SB1: |
959 | case CPU_SB1A: | |
de62893b | 960 | c->dcache.flags |= MIPS_CACHE_PINDEX; |
641e97f3 RB |
961 | break; |
962 | ||
d1e344e5 RB |
963 | case CPU_R10000: |
964 | case CPU_R12000: | |
44d921b2 | 965 | case CPU_R14000: |
d1e344e5 | 966 | break; |
641e97f3 | 967 | |
d1e344e5 | 968 | case CPU_24K: |
98a41de9 | 969 | case CPU_34K: |
2e78ae3f | 970 | case CPU_74K: |
beab375a RB |
971 | if ((read_c0_config7() & (1 << 16))) { |
972 | /* effectively physically indexed dcache, | |
973 | thus no virtual aliases. */ | |
974 | c->dcache.flags |= MIPS_CACHE_PINDEX; | |
975 | break; | |
976 | } | |
d1e344e5 | 977 | default: |
beab375a RB |
978 | if (c->dcache.waysize > PAGE_SIZE) |
979 | c->dcache.flags |= MIPS_CACHE_ALIASES; | |
d1e344e5 | 980 | } |
1da177e4 LT |
981 | |
982 | switch (c->cputype) { | |
983 | case CPU_20KC: | |
984 | /* | |
985 | * Some older 20Kc chips doesn't have the 'VI' bit in | |
986 | * the config register. | |
987 | */ | |
988 | c->icache.flags |= MIPS_CACHE_VTAG; | |
989 | break; | |
990 | ||
e3ad1c23 | 991 | case CPU_AU1000: |
1da177e4 | 992 | case CPU_AU1500: |
e3ad1c23 PP |
993 | case CPU_AU1100: |
994 | case CPU_AU1550: | |
995 | case CPU_AU1200: | |
237cfee1 ML |
996 | case CPU_AU1210: |
997 | case CPU_AU1250: | |
1da177e4 LT |
998 | c->icache.flags |= MIPS_CACHE_IC_F_DC; |
999 | break; | |
1000 | } | |
1001 | ||
2a21c730 FZ |
1002 | #ifdef CONFIG_CPU_LOONGSON2 |
1003 | /* | |
1004 | * LOONGSON2 has 4 way icache, but when using indexed cache op, | |
1005 | * one op will act on all 4 ways | |
1006 | */ | |
1007 | c->icache.ways = 1; | |
1008 | #endif | |
1009 | ||
1da177e4 LT |
1010 | printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n", |
1011 | icache_size >> 10, | |
64bfca5c | 1012 | cpu_has_vtag_icache ? "VIVT" : "VIPT", |
1da177e4 LT |
1013 | way_string[c->icache.ways], c->icache.linesz); |
1014 | ||
64bfca5c RB |
1015 | printk("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n", |
1016 | dcache_size >> 10, way_string[c->dcache.ways], | |
1017 | (c->dcache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT", | |
1018 | (c->dcache.flags & MIPS_CACHE_ALIASES) ? | |
1019 | "cache aliases" : "no aliases", | |
1020 | c->dcache.linesz); | |
1da177e4 LT |
1021 | } |
1022 | ||
1023 | /* | |
1024 | * If you even _breathe_ on this function, look at the gcc output and make sure | |
1025 | * it does not pop things on and off the stack for the cache sizing loop that | |
1026 | * executes in KSEG1 space or else you will crash and burn badly. You have | |
1027 | * been warned. | |
1028 | */ | |
234fcd14 | 1029 | static int __cpuinit probe_scache(void) |
1da177e4 | 1030 | { |
1da177e4 LT |
1031 | unsigned long flags, addr, begin, end, pow2; |
1032 | unsigned int config = read_c0_config(); | |
1033 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
1034 | int tmp; | |
1035 | ||
1036 | if (config & CONF_SC) | |
1037 | return 0; | |
1038 | ||
e001e528 | 1039 | begin = (unsigned long) &_stext; |
1da177e4 LT |
1040 | begin &= ~((4 * 1024 * 1024) - 1); |
1041 | end = begin + (4 * 1024 * 1024); | |
1042 | ||
1043 | /* | |
1044 | * This is such a bitch, you'd think they would make it easy to do | |
1045 | * this. Away you daemons of stupidity! | |
1046 | */ | |
1047 | local_irq_save(flags); | |
1048 | ||
1049 | /* Fill each size-multiple cache line with a valid tag. */ | |
1050 | pow2 = (64 * 1024); | |
1051 | for (addr = begin; addr < end; addr = (begin + pow2)) { | |
1052 | unsigned long *p = (unsigned long *) addr; | |
1053 | __asm__ __volatile__("nop" : : "r" (*p)); /* whee... */ | |
1054 | pow2 <<= 1; | |
1055 | } | |
1056 | ||
1057 | /* Load first line with zero (therefore invalid) tag. */ | |
1058 | write_c0_taglo(0); | |
1059 | write_c0_taghi(0); | |
1060 | __asm__ __volatile__("nop; nop; nop; nop;"); /* avoid the hazard */ | |
1061 | cache_op(Index_Store_Tag_I, begin); | |
1062 | cache_op(Index_Store_Tag_D, begin); | |
1063 | cache_op(Index_Store_Tag_SD, begin); | |
1064 | ||
1065 | /* Now search for the wrap around point. */ | |
1066 | pow2 = (128 * 1024); | |
1067 | tmp = 0; | |
1068 | for (addr = begin + (128 * 1024); addr < end; addr = begin + pow2) { | |
1069 | cache_op(Index_Load_Tag_SD, addr); | |
1070 | __asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */ | |
1071 | if (!read_c0_taglo()) | |
1072 | break; | |
1073 | pow2 <<= 1; | |
1074 | } | |
1075 | local_irq_restore(flags); | |
1076 | addr -= begin; | |
1077 | ||
1078 | scache_size = addr; | |
1079 | c->scache.linesz = 16 << ((config & R4K_CONF_SB) >> 22); | |
1080 | c->scache.ways = 1; | |
1081 | c->dcache.waybit = 0; /* does not matter */ | |
1082 | ||
1083 | return 1; | |
1084 | } | |
1085 | ||
2a21c730 FZ |
1086 | #if defined(CONFIG_CPU_LOONGSON2) |
1087 | static void __init loongson2_sc_init(void) | |
1088 | { | |
1089 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
1090 | ||
1091 | scache_size = 512*1024; | |
1092 | c->scache.linesz = 32; | |
1093 | c->scache.ways = 4; | |
1094 | c->scache.waybit = 0; | |
1095 | c->scache.waysize = scache_size / (c->scache.ways); | |
1096 | c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways); | |
1097 | pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n", | |
1098 | scache_size >> 10, way_string[c->scache.ways], c->scache.linesz); | |
1099 | ||
1100 | c->options |= MIPS_CPU_INCLUSIVE_CACHES; | |
1101 | } | |
1102 | #endif | |
1103 | ||
1da177e4 LT |
1104 | extern int r5k_sc_init(void); |
1105 | extern int rm7k_sc_init(void); | |
9318c51a | 1106 | extern int mips_sc_init(void); |
1da177e4 | 1107 | |
234fcd14 | 1108 | static void __cpuinit setup_scache(void) |
1da177e4 LT |
1109 | { |
1110 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
1111 | unsigned int config = read_c0_config(); | |
1da177e4 LT |
1112 | int sc_present = 0; |
1113 | ||
1114 | /* | |
1115 | * Do the probing thing on R4000SC and R4400SC processors. Other | |
1116 | * processors don't have a S-cache that would be relevant to the | |
603e82ed | 1117 | * Linux memory management. |
1da177e4 LT |
1118 | */ |
1119 | switch (c->cputype) { | |
1120 | case CPU_R4000SC: | |
1121 | case CPU_R4000MC: | |
1122 | case CPU_R4400SC: | |
1123 | case CPU_R4400MC: | |
ba5187db | 1124 | sc_present = run_uncached(probe_scache); |
1da177e4 LT |
1125 | if (sc_present) |
1126 | c->options |= MIPS_CPU_CACHE_CDEX_S; | |
1127 | break; | |
1128 | ||
1129 | case CPU_R10000: | |
1130 | case CPU_R12000: | |
44d921b2 | 1131 | case CPU_R14000: |
1da177e4 LT |
1132 | scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16); |
1133 | c->scache.linesz = 64 << ((config >> 13) & 1); | |
1134 | c->scache.ways = 2; | |
1135 | c->scache.waybit= 0; | |
1136 | sc_present = 1; | |
1137 | break; | |
1138 | ||
1139 | case CPU_R5000: | |
1140 | case CPU_NEVADA: | |
1141 | #ifdef CONFIG_R5000_CPU_SCACHE | |
1142 | r5k_sc_init(); | |
1143 | #endif | |
1144 | return; | |
1145 | ||
1146 | case CPU_RM7000: | |
1147 | case CPU_RM9000: | |
1148 | #ifdef CONFIG_RM7000_CPU_SCACHE | |
1149 | rm7k_sc_init(); | |
1150 | #endif | |
1151 | return; | |
1152 | ||
2a21c730 FZ |
1153 | #if defined(CONFIG_CPU_LOONGSON2) |
1154 | case CPU_LOONGSON2: | |
1155 | loongson2_sc_init(); | |
1156 | return; | |
1157 | #endif | |
1158 | ||
1da177e4 | 1159 | default: |
9318c51a CD |
1160 | if (c->isa_level == MIPS_CPU_ISA_M32R1 || |
1161 | c->isa_level == MIPS_CPU_ISA_M32R2 || | |
1162 | c->isa_level == MIPS_CPU_ISA_M64R1 || | |
1163 | c->isa_level == MIPS_CPU_ISA_M64R2) { | |
1164 | #ifdef CONFIG_MIPS_CPU_SCACHE | |
1165 | if (mips_sc_init ()) { | |
1166 | scache_size = c->scache.ways * c->scache.sets * c->scache.linesz; | |
1167 | printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n", | |
1168 | scache_size >> 10, | |
1169 | way_string[c->scache.ways], c->scache.linesz); | |
1170 | } | |
1171 | #else | |
1172 | if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT)) | |
1173 | panic("Dunno how to handle MIPS32 / MIPS64 second level cache"); | |
1174 | #endif | |
1175 | return; | |
1176 | } | |
1da177e4 LT |
1177 | sc_present = 0; |
1178 | } | |
1179 | ||
1180 | if (!sc_present) | |
1181 | return; | |
1182 | ||
1da177e4 LT |
1183 | /* compute a couple of other cache variables */ |
1184 | c->scache.waysize = scache_size / c->scache.ways; | |
1185 | ||
1186 | c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways); | |
1187 | ||
1188 | printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n", | |
1189 | scache_size >> 10, way_string[c->scache.ways], c->scache.linesz); | |
1190 | ||
fc5d2d27 | 1191 | c->options |= MIPS_CPU_INCLUSIVE_CACHES; |
1da177e4 LT |
1192 | } |
1193 | ||
9370b351 SS |
1194 | void au1x00_fixup_config_od(void) |
1195 | { | |
1196 | /* | |
1197 | * c0_config.od (bit 19) was write only (and read as 0) | |
1198 | * on the early revisions of Alchemy SOCs. It disables the bus | |
1199 | * transaction overlapping and needs to be set to fix various errata. | |
1200 | */ | |
1201 | switch (read_c0_prid()) { | |
1202 | case 0x00030100: /* Au1000 DA */ | |
1203 | case 0x00030201: /* Au1000 HA */ | |
1204 | case 0x00030202: /* Au1000 HB */ | |
1205 | case 0x01030200: /* Au1500 AB */ | |
1206 | /* | |
1207 | * Au1100 errata actually keeps silence about this bit, so we set it | |
1208 | * just in case for those revisions that require it to be set according | |
1209 | * to arch/mips/au1000/common/cputable.c | |
1210 | */ | |
1211 | case 0x02030200: /* Au1100 AB */ | |
1212 | case 0x02030201: /* Au1100 BA */ | |
1213 | case 0x02030202: /* Au1100 BC */ | |
1214 | set_c0_config(1 << 19); | |
1215 | break; | |
1216 | } | |
1217 | } | |
1218 | ||
234fcd14 | 1219 | static void __cpuinit coherency_setup(void) |
1da177e4 LT |
1220 | { |
1221 | change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT); | |
1222 | ||
1223 | /* | |
1224 | * c0_status.cu=0 specifies that updates by the sc instruction use | |
1225 | * the coherency mode specified by the TLB; 1 means cachable | |
1226 | * coherent update on write will be used. Not all processors have | |
1227 | * this bit and; some wire it to zero, others like Toshiba had the | |
1228 | * silly idea of putting something else there ... | |
1229 | */ | |
10cc3529 | 1230 | switch (current_cpu_type()) { |
1da177e4 LT |
1231 | case CPU_R4000PC: |
1232 | case CPU_R4000SC: | |
1233 | case CPU_R4000MC: | |
1234 | case CPU_R4400PC: | |
1235 | case CPU_R4400SC: | |
1236 | case CPU_R4400MC: | |
1237 | clear_c0_config(CONF_CU); | |
1238 | break; | |
9370b351 | 1239 | /* |
df586d59 | 1240 | * We need to catch the early Alchemy SOCs with |
9370b351 SS |
1241 | * the write-only co_config.od bit and set it back to one... |
1242 | */ | |
1243 | case CPU_AU1000: /* rev. DA, HA, HB */ | |
1244 | case CPU_AU1100: /* rev. AB, BA, BC ?? */ | |
1245 | case CPU_AU1500: /* rev. AB */ | |
1246 | au1x00_fixup_config_od(); | |
1247 | break; | |
1da177e4 LT |
1248 | } |
1249 | } | |
1250 | ||
234fcd14 | 1251 | void __cpuinit r4k_cache_init(void) |
1da177e4 LT |
1252 | { |
1253 | extern void build_clear_page(void); | |
1254 | extern void build_copy_page(void); | |
641e97f3 RB |
1255 | extern char __weak except_vec2_generic; |
1256 | extern char __weak except_vec2_sb1; | |
1da177e4 LT |
1257 | struct cpuinfo_mips *c = ¤t_cpu_data; |
1258 | ||
641e97f3 RB |
1259 | switch (c->cputype) { |
1260 | case CPU_SB1: | |
1261 | case CPU_SB1A: | |
1262 | set_uncached_handler(0x100, &except_vec2_sb1, 0x80); | |
1263 | break; | |
1264 | ||
1265 | default: | |
1266 | set_uncached_handler(0x100, &except_vec2_generic, 0x80); | |
1267 | break; | |
1268 | } | |
1da177e4 LT |
1269 | |
1270 | probe_pcache(); | |
1271 | setup_scache(); | |
1272 | ||
1da177e4 LT |
1273 | r4k_blast_dcache_page_setup(); |
1274 | r4k_blast_dcache_page_indexed_setup(); | |
1275 | r4k_blast_dcache_setup(); | |
1276 | r4k_blast_icache_page_setup(); | |
1277 | r4k_blast_icache_page_indexed_setup(); | |
1278 | r4k_blast_icache_setup(); | |
1279 | r4k_blast_scache_page_setup(); | |
1280 | r4k_blast_scache_page_indexed_setup(); | |
1281 | r4k_blast_scache_setup(); | |
1282 | ||
1283 | /* | |
1284 | * Some MIPS32 and MIPS64 processors have physically indexed caches. | |
1285 | * This code supports virtually indexed processors and will be | |
1286 | * unnecessarily inefficient on physically indexed processors. | |
1287 | */ | |
73f40352 CD |
1288 | if (c->dcache.linesz) |
1289 | shm_align_mask = max_t( unsigned long, | |
1290 | c->dcache.sets * c->dcache.linesz - 1, | |
1291 | PAGE_SIZE - 1); | |
1292 | else | |
1293 | shm_align_mask = PAGE_SIZE-1; | |
9c5a3d72 RB |
1294 | |
1295 | __flush_cache_vmap = r4k__flush_cache_vmap; | |
1296 | __flush_cache_vunmap = r4k__flush_cache_vunmap; | |
1297 | ||
db813fe5 | 1298 | flush_cache_all = cache_noop; |
1da177e4 LT |
1299 | __flush_cache_all = r4k___flush_cache_all; |
1300 | flush_cache_mm = r4k_flush_cache_mm; | |
1301 | flush_cache_page = r4k_flush_cache_page; | |
1da177e4 LT |
1302 | flush_cache_range = r4k_flush_cache_range; |
1303 | ||
1304 | flush_cache_sigtramp = r4k_flush_cache_sigtramp; | |
1305 | flush_icache_all = r4k_flush_icache_all; | |
7e3bfc7c | 1306 | local_flush_data_cache_page = local_r4k_flush_data_cache_page; |
1da177e4 LT |
1307 | flush_data_cache_page = r4k_flush_data_cache_page; |
1308 | flush_icache_range = r4k_flush_icache_range; | |
1309 | ||
1310 | #ifdef CONFIG_DMA_NONCOHERENT | |
1311 | _dma_cache_wback_inv = r4k_dma_cache_wback_inv; | |
1312 | _dma_cache_wback = r4k_dma_cache_wback_inv; | |
1313 | _dma_cache_inv = r4k_dma_cache_inv; | |
1314 | #endif | |
1315 | ||
1da177e4 LT |
1316 | build_clear_page(); |
1317 | build_copy_page(); | |
1d40cfcd RB |
1318 | local_r4k___flush_cache_all(NULL); |
1319 | coherency_setup(); | |
1da177e4 | 1320 | } |