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Define EOWNERDEAD and ENOTRECOVERABLE.
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / mips / mm / c-r4k.c
CommitLineData
1da177e4
LT		 1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
7 * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org)
8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
9 */
10#include <linux/config.h>
11#include <linux/init.h>
12#include <linux/kernel.h>
13#include <linux/sched.h>
14#include <linux/mm.h>
15#include <linux/bitops.h>
16
17#include <asm/bcache.h>
18#include <asm/bootinfo.h>
ec74e361 19#include <asm/cache.h>
1da177e4
LT		 20#include <asm/cacheops.h>
21#include <asm/cpu.h>
22#include <asm/cpu-features.h>
23#include <asm/io.h>
24#include <asm/page.h>
25#include <asm/pgtable.h>
26#include <asm/r4kcache.h>
27#include <asm/system.h>
28#include <asm/mmu_context.h>
29#include <asm/war.h>
ba5187db 30#include <asm/cacheflush.h> /* for run_uncached() */
1da177e4 31
ec74e361
RB		 32/*
33 * Must die.
34 */
35static unsigned long icache_size __read_mostly;
36static unsigned long dcache_size __read_mostly;
37static unsigned long scache_size __read_mostly;
1da177e4
LT		 38
39/*
40 * Dummy cache handling routines for machines without boardcaches
41 */
42static void no_sc_noop(void) {}
43
44static struct bcache_ops no_sc_ops = {
45 .bc_enable = (void *)no_sc_noop,
46 .bc_disable = (void *)no_sc_noop,
47 .bc_wback_inv = (void *)no_sc_noop,
48 .bc_inv = (void *)no_sc_noop
49};
50
51struct bcache_ops *bcops = &no_sc_ops;
52
330cfe01
TS		 53#define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x00002010)
54#define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x00002020)
1da177e4
LT		 55
56#define R4600_HIT_CACHEOP_WAR_IMPL \
57do { \
58 if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) \
59 *(volatile unsigned long *)CKSEG1; \
60 if (R4600_V1_HIT_CACHEOP_WAR) \
61 __asm__ __volatile__("nop;nop;nop;nop"); \
62} while (0)
63
64static void (*r4k_blast_dcache_page)(unsigned long addr);
65
66static inline void r4k_blast_dcache_page_dc32(unsigned long addr)
67{
68 R4600_HIT_CACHEOP_WAR_IMPL;
69 blast_dcache32_page(addr);
70}
71
72static inline void r4k_blast_dcache_page_setup(void)
73{
74 unsigned long dc_lsize = cpu_dcache_line_size();
75
76 if (dc_lsize == 16)
77 r4k_blast_dcache_page = blast_dcache16_page;
78 else if (dc_lsize == 32)
79 r4k_blast_dcache_page = r4k_blast_dcache_page_dc32;
80}
81
82static void (* r4k_blast_dcache_page_indexed)(unsigned long addr);
83
84static inline void r4k_blast_dcache_page_indexed_setup(void)
85{
86 unsigned long dc_lsize = cpu_dcache_line_size();
87
88 if (dc_lsize == 16)
89 r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed;
90 else if (dc_lsize == 32)
91 r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed;
92}
93
94static void (* r4k_blast_dcache)(void);
95
96static inline void r4k_blast_dcache_setup(void)
97{
98 unsigned long dc_lsize = cpu_dcache_line_size();
99
100 if (dc_lsize == 16)
101 r4k_blast_dcache = blast_dcache16;
102 else if (dc_lsize == 32)
103 r4k_blast_dcache = blast_dcache32;
104}
105
106/* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */
107#define JUMP_TO_ALIGN(order) \
108 __asm__ __volatile__( \
109 "b\t1f\n\t" \
110 ".align\t" #order "\n\t" \
111 "1:\n\t" \
112 )
113#define CACHE32_UNROLL32_ALIGN JUMP_TO_ALIGN(10) /* 32 * 32 = 1024 */
114#define CACHE32_UNROLL32_ALIGN2 JUMP_TO_ALIGN(11)
115
116static inline void blast_r4600_v1_icache32(void)
117{
118 unsigned long flags;
119
120 local_irq_save(flags);
121 blast_icache32();
122 local_irq_restore(flags);
123}
124
125static inline void tx49_blast_icache32(void)
126{
127 unsigned long start = INDEX_BASE;
128 unsigned long end = start + current_cpu_data.icache.waysize;
129 unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
130 unsigned long ws_end = current_cpu_data.icache.ways <<
131 current_cpu_data.icache.waybit;
132 unsigned long ws, addr;
133
134 CACHE32_UNROLL32_ALIGN2;
135 /* I'm in even chunk. blast odd chunks */
42a3b4f2
RB		 136 for (ws = 0; ws < ws_end; ws += ws_inc)
137 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
1da177e4
LT		 138 cache32_unroll32(addr|ws,Index_Invalidate_I);
139 CACHE32_UNROLL32_ALIGN;
140 /* I'm in odd chunk. blast even chunks */
42a3b4f2
RB		 141 for (ws = 0; ws < ws_end; ws += ws_inc)
142 for (addr = start; addr < end; addr += 0x400 * 2)
1da177e4
LT		 143 cache32_unroll32(addr|ws,Index_Invalidate_I);
144}
145
146static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page)
147{
148 unsigned long flags;
149
150 local_irq_save(flags);
151 blast_icache32_page_indexed(page);
152 local_irq_restore(flags);
153}
154
155static inline void tx49_blast_icache32_page_indexed(unsigned long page)
156{
157 unsigned long start = page;
158 unsigned long end = start + PAGE_SIZE;
159 unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
160 unsigned long ws_end = current_cpu_data.icache.ways <<
161 current_cpu_data.icache.waybit;
162 unsigned long ws, addr;
163
164 CACHE32_UNROLL32_ALIGN2;
165 /* I'm in even chunk. blast odd chunks */
42a3b4f2
RB		 166 for (ws = 0; ws < ws_end; ws += ws_inc)
167 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
1da177e4
LT		 168 cache32_unroll32(addr|ws,Index_Invalidate_I);
169 CACHE32_UNROLL32_ALIGN;
170 /* I'm in odd chunk. blast even chunks */
42a3b4f2
RB		 171 for (ws = 0; ws < ws_end; ws += ws_inc)
172 for (addr = start; addr < end; addr += 0x400 * 2)
1da177e4
LT		 173 cache32_unroll32(addr|ws,Index_Invalidate_I);
174}
175
176static void (* r4k_blast_icache_page)(unsigned long addr);
177
178static inline void r4k_blast_icache_page_setup(void)
179{
180 unsigned long ic_lsize = cpu_icache_line_size();
181
182 if (ic_lsize == 16)
183 r4k_blast_icache_page = blast_icache16_page;
184 else if (ic_lsize == 32)
185 r4k_blast_icache_page = blast_icache32_page;
186 else if (ic_lsize == 64)
187 r4k_blast_icache_page = blast_icache64_page;
188}
189
190
191static void (* r4k_blast_icache_page_indexed)(unsigned long addr);
192
193static inline void r4k_blast_icache_page_indexed_setup(void)
194{
195 unsigned long ic_lsize = cpu_icache_line_size();
196
197 if (ic_lsize == 16)
198 r4k_blast_icache_page_indexed = blast_icache16_page_indexed;
199 else if (ic_lsize == 32) {
02fe2c9c 200 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
1da177e4
LT		 201 r4k_blast_icache_page_indexed =
202 blast_icache32_r4600_v1_page_indexed;
02fe2c9c
TS		 203 else if (TX49XX_ICACHE_INDEX_INV_WAR)
204 r4k_blast_icache_page_indexed =
205 tx49_blast_icache32_page_indexed;
1da177e4
LT		 206 else
207 r4k_blast_icache_page_indexed =
208 blast_icache32_page_indexed;
209 } else if (ic_lsize == 64)
210 r4k_blast_icache_page_indexed = blast_icache64_page_indexed;
211}
212
213static void (* r4k_blast_icache)(void);
214
215static inline void r4k_blast_icache_setup(void)
216{
217 unsigned long ic_lsize = cpu_icache_line_size();
218
219 if (ic_lsize == 16)
220 r4k_blast_icache = blast_icache16;
221 else if (ic_lsize == 32) {
222 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
223 r4k_blast_icache = blast_r4600_v1_icache32;
224 else if (TX49XX_ICACHE_INDEX_INV_WAR)
225 r4k_blast_icache = tx49_blast_icache32;
226 else
227 r4k_blast_icache = blast_icache32;
228 } else if (ic_lsize == 64)
229 r4k_blast_icache = blast_icache64;
230}
231
232static void (* r4k_blast_scache_page)(unsigned long addr);
233
234static inline void r4k_blast_scache_page_setup(void)
235{
236 unsigned long sc_lsize = cpu_scache_line_size();
237
238 if (sc_lsize == 16)
239 r4k_blast_scache_page = blast_scache16_page;
240 else if (sc_lsize == 32)
241 r4k_blast_scache_page = blast_scache32_page;
242 else if (sc_lsize == 64)
243 r4k_blast_scache_page = blast_scache64_page;
244 else if (sc_lsize == 128)
245 r4k_blast_scache_page = blast_scache128_page;
246}
247
248static void (* r4k_blast_scache_page_indexed)(unsigned long addr);
249
250static inline void r4k_blast_scache_page_indexed_setup(void)
251{
252 unsigned long sc_lsize = cpu_scache_line_size();
253
254 if (sc_lsize == 16)
255 r4k_blast_scache_page_indexed = blast_scache16_page_indexed;
256 else if (sc_lsize == 32)
257 r4k_blast_scache_page_indexed = blast_scache32_page_indexed;
258 else if (sc_lsize == 64)
259 r4k_blast_scache_page_indexed = blast_scache64_page_indexed;
260 else if (sc_lsize == 128)
261 r4k_blast_scache_page_indexed = blast_scache128_page_indexed;
262}
263
264static void (* r4k_blast_scache)(void);
265
266static inline void r4k_blast_scache_setup(void)
267{
268 unsigned long sc_lsize = cpu_scache_line_size();
269
270 if (sc_lsize == 16)
271 r4k_blast_scache = blast_scache16;
272 else if (sc_lsize == 32)
273 r4k_blast_scache = blast_scache32;
274 else if (sc_lsize == 64)
275 r4k_blast_scache = blast_scache64;
276 else if (sc_lsize == 128)
277 r4k_blast_scache = blast_scache128;
278}
279
280/*
281 * This is former mm's flush_cache_all() which really should be
282 * flush_cache_vunmap these days ...
283 */
284static inline void local_r4k_flush_cache_all(void * args)
285{
286 r4k_blast_dcache();
287 r4k_blast_icache();
288}
289
290static void r4k_flush_cache_all(void)
291{
292 if (!cpu_has_dc_aliases)
293 return;
294
295 on_each_cpu(local_r4k_flush_cache_all, NULL, 1, 1);
296}
297
298static inline void local_r4k___flush_cache_all(void * args)
299{
300 r4k_blast_dcache();
301 r4k_blast_icache();
302
303 switch (current_cpu_data.cputype) {
304 case CPU_R4000SC:
305 case CPU_R4000MC:
306 case CPU_R4400SC:
307 case CPU_R4400MC:
308 case CPU_R10000:
309 case CPU_R12000:
310 r4k_blast_scache();
311 }
312}
313
314static void r4k___flush_cache_all(void)
315{
316 on_each_cpu(local_r4k___flush_cache_all, NULL, 1, 1);
317}
318
319static inline void local_r4k_flush_cache_range(void * args)
320{
321 struct vm_area_struct *vma = args;
322 int exec;
323
324 if (!(cpu_context(smp_processor_id(), vma->vm_mm)))
325 return;
326
327 exec = vma->vm_flags & VM_EXEC;
328 if (cpu_has_dc_aliases || exec)
329 r4k_blast_dcache();
330 if (exec)
331 r4k_blast_icache();
332}
333
334static void r4k_flush_cache_range(struct vm_area_struct *vma,
335 unsigned long start, unsigned long end)
336{
337 on_each_cpu(local_r4k_flush_cache_range, vma, 1, 1);
338}
339
340static inline void local_r4k_flush_cache_mm(void * args)
341{
342 struct mm_struct *mm = args;
343
344 if (!cpu_context(smp_processor_id(), mm))
345 return;
346
347 r4k_blast_dcache();
348 r4k_blast_icache();
349
350 /*
351 * Kludge alert. For obscure reasons R4000SC and R4400SC go nuts if we
352 * only flush the primary caches but R10000 and R12000 behave sane ...
353 */
354 if (current_cpu_data.cputype == CPU_R4000SC ||
355 current_cpu_data.cputype == CPU_R4000MC ||
356 current_cpu_data.cputype == CPU_R4400SC ||
357 current_cpu_data.cputype == CPU_R4400MC)
358 r4k_blast_scache();
359}
360
361static void r4k_flush_cache_mm(struct mm_struct *mm)
362{
363 if (!cpu_has_dc_aliases)
364 return;
365
366 on_each_cpu(local_r4k_flush_cache_mm, mm, 1, 1);
367}
368
369struct flush_cache_page_args {
370 struct vm_area_struct *vma;
371 unsigned long page;
372};
373
374static inline void local_r4k_flush_cache_page(void *args)
375{
376 struct flush_cache_page_args *fcp_args = args;
377 struct vm_area_struct *vma = fcp_args->vma;
378 unsigned long page = fcp_args->page;
379 int exec = vma->vm_flags & VM_EXEC;
380 struct mm_struct *mm = vma->vm_mm;
381 pgd_t *pgdp;
c6e8b587 382 pud_t *pudp;
1da177e4
LT		 383 pmd_t *pmdp;
384 pte_t *ptep;
385
79acf83e
RB		 386 /*
387 * If ownes no valid ASID yet, cannot possibly have gotten
388 * this page into the cache.
389 */
26a51b27 390 if (cpu_context(smp_processor_id(), mm) == 0)
79acf83e
RB		 391 return;
392
1da177e4
LT		 393 page &= PAGE_MASK;
394 pgdp = pgd_offset(mm, page);
c6e8b587
RB		 395 pudp = pud_offset(pgdp, page);
396 pmdp = pmd_offset(pudp, page);
1da177e4
LT		 397 ptep = pte_offset(pmdp, page);
398
399 /*
400 * If the page isn't marked valid, the page cannot possibly be
401 * in the cache.
402 */
403 if (!(pte_val(*ptep) & _PAGE_PRESENT))
404 return;
405
406 /*
407 * Doing flushes for another ASID than the current one is
408 * too difficult since stupid R4k caches do a TLB translation
409 * for every cache flush operation. So we do indexed flushes
410 * in that case, which doesn't overly flush the cache too much.
411 */
412 if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) {
413 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
414 r4k_blast_dcache_page(page);
415 if (exec && !cpu_icache_snoops_remote_store)
416 r4k_blast_scache_page(page);
417 }
418 if (exec)
419 r4k_blast_icache_page(page);
420
421 return;
422 }
423
424 /*
425 * Do indexed flush, too much work to get the (possible) TLB refills
426 * to work correctly.
427 */
428 page = INDEX_BASE + (page & (dcache_size - 1));
429 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
430 r4k_blast_dcache_page_indexed(page);
431 if (exec && !cpu_icache_snoops_remote_store)
432 r4k_blast_scache_page_indexed(page);
433 }
434 if (exec) {
435 if (cpu_has_vtag_icache) {
436 int cpu = smp_processor_id();
437
26a51b27
TS		 438 if (cpu_context(cpu, mm) != 0)
439 drop_mmu_context(mm, cpu);
1da177e4
LT		 440 } else
441 r4k_blast_icache_page_indexed(page);
442 }
443}
444
445static void r4k_flush_cache_page(struct vm_area_struct *vma, unsigned long page, unsigned long pfn)
446{
447 struct flush_cache_page_args args;
448
1da177e4
LT		 449 args.vma = vma;
450 args.page = page;
451
452 on_each_cpu(local_r4k_flush_cache_page, &args, 1, 1);
453}
454
455static inline void local_r4k_flush_data_cache_page(void * addr)
456{
457 r4k_blast_dcache_page((unsigned long) addr);
458}
459
460static void r4k_flush_data_cache_page(unsigned long addr)
461{
462 on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr, 1, 1);
463}
464
465struct flush_icache_range_args {
fe00f943
RB		 466 unsigned long __user start;
467 unsigned long __user end;
1da177e4
LT		 468};
469
470static inline void local_r4k_flush_icache_range(void *args)
471{
472 struct flush_icache_range_args *fir_args = args;
02fe2c9c
TS		 473 unsigned long dc_lsize = cpu_dcache_line_size();
474 unsigned long ic_lsize = cpu_icache_line_size();
475 unsigned long sc_lsize = cpu_scache_line_size();
1da177e4
LT		 476 unsigned long start = fir_args->start;
477 unsigned long end = fir_args->end;
478 unsigned long addr, aend;
479
480 if (!cpu_has_ic_fills_f_dc) {
481 if (end - start > dcache_size) {
482 r4k_blast_dcache();
483 } else {
10a3dabd 484 R4600_HIT_CACHEOP_WAR_IMPL;
1da177e4
LT		 485 addr = start & ~(dc_lsize - 1);
486 aend = (end - 1) & ~(dc_lsize - 1);
487
488 while (1) {
489 /* Hit_Writeback_Inv_D */
490 protected_writeback_dcache_line(addr);
491 if (addr == aend)
492 break;
493 addr += dc_lsize;
494 }
495 }
496
497 if (!cpu_icache_snoops_remote_store) {
498 if (end - start > scache_size) {
499 r4k_blast_scache();
500 } else {
501 addr = start & ~(sc_lsize - 1);
502 aend = (end - 1) & ~(sc_lsize - 1);
503
504 while (1) {
02fe2c9c 505 /* Hit_Writeback_Inv_SD */
1da177e4
LT		 506 protected_writeback_scache_line(addr);
507 if (addr == aend)
508 break;
509 addr += sc_lsize;
510 }
511 }
512 }
513 }
514
515 if (end - start > icache_size)
516 r4k_blast_icache();
517 else {
518 addr = start & ~(ic_lsize - 1);
519 aend = (end - 1) & ~(ic_lsize - 1);
520 while (1) {
521 /* Hit_Invalidate_I */
522 protected_flush_icache_line(addr);
523 if (addr == aend)
524 break;
525 addr += ic_lsize;
526 }
527 }
528}
529
fe00f943
RB		 530static void r4k_flush_icache_range(unsigned long __user start,
531 unsigned long __user end)
1da177e4
LT		 532{
533 struct flush_icache_range_args args;
534
535 args.start = start;
536 args.end = end;
537
538 on_each_cpu(local_r4k_flush_icache_range, &args, 1, 1);
cc61c1fe 539 instruction_hazard();
1da177e4
LT		 540}
541
542/*
543 * Ok, this seriously sucks. We use them to flush a user page but don't
544 * know the virtual address, so we have to blast away the whole icache
545 * which is significantly more expensive than the real thing. Otoh we at
546 * least know the kernel address of the page so we can flush it
547 * selectivly.
548 */
549
550struct flush_icache_page_args {
551 struct vm_area_struct *vma;
552 struct page *page;
553};
554
555static inline void local_r4k_flush_icache_page(void *args)
556{
557 struct flush_icache_page_args *fip_args = args;
558 struct vm_area_struct *vma = fip_args->vma;
559 struct page *page = fip_args->page;
560
561 /*
562 * Tricky ... Because we don't know the virtual address we've got the
563 * choice of either invalidating the entire primary and secondary
564 * caches or invalidating the secondary caches also. With the subset
565 * enforcment on R4000SC, R4400SC, R10000 and R12000 invalidating the
566 * secondary cache will result in any entries in the primary caches
567 * also getting invalidated which hopefully is a bit more economical.
568 */
569 if (cpu_has_subset_pcaches) {
570 unsigned long addr = (unsigned long) page_address(page);
571
572 r4k_blast_scache_page(addr);
573 ClearPageDcacheDirty(page);
574
575 return;
576 }
577
578 if (!cpu_has_ic_fills_f_dc) {
579 unsigned long addr = (unsigned long) page_address(page);
580 r4k_blast_dcache_page(addr);
581 if (!cpu_icache_snoops_remote_store)
582 r4k_blast_scache_page(addr);
583 ClearPageDcacheDirty(page);
584 }
585
586 /*
587 * We're not sure of the virtual address(es) involved here, so
588 * we have to flush the entire I-cache.
589 */
590 if (cpu_has_vtag_icache) {
591 int cpu = smp_processor_id();
592
593 if (cpu_context(cpu, vma->vm_mm) != 0)
594 drop_mmu_context(vma->vm_mm, cpu);
595 } else
596 r4k_blast_icache();
597}
598
599static void r4k_flush_icache_page(struct vm_area_struct *vma,
600 struct page *page)
601{
602 struct flush_icache_page_args args;
603
604 /*
605 * If there's no context yet, or the page isn't executable, no I-cache
606 * flush is needed.
607 */
608 if (!(vma->vm_flags & VM_EXEC))
609 return;
610
611 args.vma = vma;
612 args.page = page;
613
614 on_each_cpu(local_r4k_flush_icache_page, &args, 1, 1);
615}
616
617
618#ifdef CONFIG_DMA_NONCOHERENT
619
620static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
621{
622 unsigned long end, a;
623
624 /* Catch bad driver code */
625 BUG_ON(size == 0);
626
627 if (cpu_has_subset_pcaches) {
02fe2c9c 628 unsigned long sc_lsize = cpu_scache_line_size();
1da177e4
LT		 629
630 if (size >= scache_size) {
631 r4k_blast_scache();
632 return;
633 }
634
635 a = addr & ~(sc_lsize - 1);
636 end = (addr + size - 1) & ~(sc_lsize - 1);
637 while (1) {
638 flush_scache_line(a); /* Hit_Writeback_Inv_SD */
639 if (a == end)
640 break;
641 a += sc_lsize;
642 }
643 return;
644 }
645
646 /*
647 * Either no secondary cache or the available caches don't have the
648 * subset property so we have to flush the primary caches
649 * explicitly
650 */
651 if (size >= dcache_size) {
652 r4k_blast_dcache();
653 } else {
02fe2c9c 654 unsigned long dc_lsize = cpu_dcache_line_size();
1da177e4
LT		 655
656 R4600_HIT_CACHEOP_WAR_IMPL;
657 a = addr & ~(dc_lsize - 1);
658 end = (addr + size - 1) & ~(dc_lsize - 1);
659 while (1) {
660 flush_dcache_line(a); /* Hit_Writeback_Inv_D */
661 if (a == end)
662 break;
663 a += dc_lsize;
664 }
665 }
666
667 bc_wback_inv(addr, size);
668}
669
670static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
671{
672 unsigned long end, a;
673
674 /* Catch bad driver code */
675 BUG_ON(size == 0);
676
677 if (cpu_has_subset_pcaches) {
02fe2c9c 678 unsigned long sc_lsize = cpu_scache_line_size();
1da177e4
LT		 679
680 if (size >= scache_size) {
681 r4k_blast_scache();
682 return;
683 }
684
685 a = addr & ~(sc_lsize - 1);
686 end = (addr + size - 1) & ~(sc_lsize - 1);
687 while (1) {
688 flush_scache_line(a); /* Hit_Writeback_Inv_SD */
689 if (a == end)
690 break;
691 a += sc_lsize;
692 }
693 return;
694 }
695
696 if (size >= dcache_size) {
697 r4k_blast_dcache();
698 } else {
02fe2c9c 699 unsigned long dc_lsize = cpu_dcache_line_size();
1da177e4
LT		 700
701 R4600_HIT_CACHEOP_WAR_IMPL;
702 a = addr & ~(dc_lsize - 1);
703 end = (addr + size - 1) & ~(dc_lsize - 1);
704 while (1) {
705 flush_dcache_line(a); /* Hit_Writeback_Inv_D */
706 if (a == end)
707 break;
708 a += dc_lsize;
709 }
710 }
711
712 bc_inv(addr, size);
713}
714#endif /* CONFIG_DMA_NONCOHERENT */
715
716/*
717 * While we're protected against bad userland addresses we don't care
718 * very much about what happens in that case. Usually a segmentation
719 * fault will dump the process later on anyway ...
720 */
721static void local_r4k_flush_cache_sigtramp(void * arg)
722{
02fe2c9c
TS		 723 unsigned long ic_lsize = cpu_icache_line_size();
724 unsigned long dc_lsize = cpu_dcache_line_size();
725 unsigned long sc_lsize = cpu_scache_line_size();
1da177e4
LT		 726 unsigned long addr = (unsigned long) arg;
727
728 R4600_HIT_CACHEOP_WAR_IMPL;
729 protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
730 if (!cpu_icache_snoops_remote_store)
731 protected_writeback_scache_line(addr & ~(sc_lsize - 1));
732 protected_flush_icache_line(addr & ~(ic_lsize - 1));
733 if (MIPS4K_ICACHE_REFILL_WAR) {
734 __asm__ __volatile__ (
735 ".set push\n\t"
736 ".set noat\n\t"
737 ".set mips3\n\t"
875d43e7 738#ifdef CONFIG_32BIT
1da177e4
LT		 739 "la $at,1f\n\t"
740#endif
875d43e7 741#ifdef CONFIG_64BIT
1da177e4
LT		 742 "dla $at,1f\n\t"
743#endif
744 "cache %0,($at)\n\t"
745 "nop; nop; nop\n"
746 "1:\n\t"
747 ".set pop"
748 :
749 : "i" (Hit_Invalidate_I));
750 }
751 if (MIPS_CACHE_SYNC_WAR)
752 __asm__ __volatile__ ("sync");
753}
754
755static void r4k_flush_cache_sigtramp(unsigned long addr)
756{
757 on_each_cpu(local_r4k_flush_cache_sigtramp, (void *) addr, 1, 1);
758}
759
760static void r4k_flush_icache_all(void)
761{
762 if (cpu_has_vtag_icache)
763 r4k_blast_icache();
764}
765
766static inline void rm7k_erratum31(void)
767{
768 const unsigned long ic_lsize = 32;
769 unsigned long addr;
770
771 /* RM7000 erratum #31. The icache is screwed at startup. */
772 write_c0_taglo(0);
773 write_c0_taghi(0);
774
775 for (addr = INDEX_BASE; addr <= INDEX_BASE + 4096; addr += ic_lsize) {
776 __asm__ __volatile__ (
d8748a3a 777 ".set push\n\t"
1da177e4
LT		 778 ".set noreorder\n\t"
779 ".set mips3\n\t"
780 "cache\t%1, 0(%0)\n\t"
781 "cache\t%1, 0x1000(%0)\n\t"
782 "cache\t%1, 0x2000(%0)\n\t"
783 "cache\t%1, 0x3000(%0)\n\t"
784 "cache\t%2, 0(%0)\n\t"
785 "cache\t%2, 0x1000(%0)\n\t"
786 "cache\t%2, 0x2000(%0)\n\t"
787 "cache\t%2, 0x3000(%0)\n\t"
788 "cache\t%1, 0(%0)\n\t"
789 "cache\t%1, 0x1000(%0)\n\t"
790 "cache\t%1, 0x2000(%0)\n\t"
791 "cache\t%1, 0x3000(%0)\n\t"
d8748a3a 792 ".set pop\n"
1da177e4
LT		 793 :
794 : "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill));
795 }
796}
797
798static char *way_string[] __initdata = { NULL, "direct mapped", "2-way",
799 "3-way", "4-way", "5-way", "6-way", "7-way", "8-way"
800};
801
802static void __init probe_pcache(void)
803{
804 struct cpuinfo_mips *c = &current_cpu_data;
805 unsigned int config = read_c0_config();
806 unsigned int prid = read_c0_prid();
807 unsigned long config1;
808 unsigned int lsize;
809
810 switch (c->cputype) {
811 case CPU_R4600: /* QED style two way caches? */
812 case CPU_R4700:
813 case CPU_R5000:
814 case CPU_NEVADA:
815 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
816 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
817 c->icache.ways = 2;
818 c->icache.waybit = ffs(icache_size/2) - 1;
819
820 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
821 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
822 c->dcache.ways = 2;
823 c->dcache.waybit= ffs(dcache_size/2) - 1;
824
825 c->options |= MIPS_CPU_CACHE_CDEX_P;
826 break;
827
828 case CPU_R5432:
829 case CPU_R5500:
830 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
831 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
832 c->icache.ways = 2;
833 c->icache.waybit= 0;
834
835 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
836 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
837 c->dcache.ways = 2;
838 c->dcache.waybit = 0;
839
840 c->options |= MIPS_CPU_CACHE_CDEX_P;
841 break;
842
843 case CPU_TX49XX:
844 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
845 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
846 c->icache.ways = 4;
847 c->icache.waybit= 0;
848
849 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
850 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
851 c->dcache.ways = 4;
852 c->dcache.waybit = 0;
853
854 c->options |= MIPS_CPU_CACHE_CDEX_P;
855 break;
856
857 case CPU_R4000PC:
858 case CPU_R4000SC:
859 case CPU_R4000MC:
860 case CPU_R4400PC:
861 case CPU_R4400SC:
862 case CPU_R4400MC:
863 case CPU_R4300:
864 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
865 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
866 c->icache.ways = 1;
867 c->icache.waybit = 0; /* doesn't matter */
868
869 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
870 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
871 c->dcache.ways = 1;
872 c->dcache.waybit = 0; /* does not matter */
873
874 c->options |= MIPS_CPU_CACHE_CDEX_P;
875 break;
876
877 case CPU_R10000:
878 case CPU_R12000:
879 icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29));
880 c->icache.linesz = 64;
881 c->icache.ways = 2;
882 c->icache.waybit = 0;
883
884 dcache_size = 1 << (12 + ((config & R10K_CONF_DC) >> 26));
885 c->dcache.linesz = 32;
886 c->dcache.ways = 2;
887 c->dcache.waybit = 0;
888
889 c->options |= MIPS_CPU_PREFETCH;
890 break;
891
892 case CPU_VR4133:
893 write_c0_config(config & ~CONF_EB);
894 case CPU_VR4131:
895 /* Workaround for cache instruction bug of VR4131 */
896 if (c->processor_id == 0x0c80U || c->processor_id == 0x0c81U ||
897 c->processor_id == 0x0c82U) {
898 config &= ~0x00000030U;
899 config |= 0x00410000U;
900 write_c0_config(config);
901 }
902 icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
903 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
904 c->icache.ways = 2;
905 c->icache.waybit = ffs(icache_size/2) - 1;
906
907 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
908 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
909 c->dcache.ways = 2;
910 c->dcache.waybit = ffs(dcache_size/2) - 1;
911
912 c->options |= MIPS_CPU_CACHE_CDEX_P;
913 break;
914
915 case CPU_VR41XX:
916 case CPU_VR4111:
917 case CPU_VR4121:
918 case CPU_VR4122:
919 case CPU_VR4181:
920 case CPU_VR4181A:
921 icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
922 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
923 c->icache.ways = 1;
924 c->icache.waybit = 0; /* doesn't matter */
925
926 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
927 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
928 c->dcache.ways = 1;
929 c->dcache.waybit = 0; /* does not matter */
930
931 c->options |= MIPS_CPU_CACHE_CDEX_P;
932 break;
933
934 case CPU_RM7000:
935 rm7k_erratum31();
936
937 case CPU_RM9000:
938 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
939 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
940 c->icache.ways = 4;
941 c->icache.waybit = ffs(icache_size / c->icache.ways) - 1;
942
943 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
944 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
945 c->dcache.ways = 4;
946 c->dcache.waybit = ffs(dcache_size / c->dcache.ways) - 1;
947
948#if !defined(CONFIG_SMP) || !defined(RM9000_CDEX_SMP_WAR)
949 c->options |= MIPS_CPU_CACHE_CDEX_P;
950#endif
951 c->options |= MIPS_CPU_PREFETCH;
952 break;
953
954 default:
955 if (!(config & MIPS_CONF_M))
956 panic("Don't know how to probe P-caches on this cpu.");
957
958 /*
959 * So we seem to be a MIPS32 or MIPS64 CPU
960 * So let's probe the I-cache ...
961 */
962 config1 = read_c0_config1();
963
964 if ((lsize = ((config1 >> 19) & 7)))
965 c->icache.linesz = 2 << lsize;
966 else
967 c->icache.linesz = lsize;
968 c->icache.sets = 64 << ((config1 >> 22) & 7);
969 c->icache.ways = 1 + ((config1 >> 16) & 7);
970
971 icache_size = c->icache.sets *
972 c->icache.ways *
973 c->icache.linesz;
974 c->icache.waybit = ffs(icache_size/c->icache.ways) - 1;
975
976 if (config & 0x8) /* VI bit */
977 c->icache.flags |= MIPS_CACHE_VTAG;
978
979 /*
980 * Now probe the MIPS32 / MIPS64 data cache.
981 */
982 c->dcache.flags = 0;
983
984 if ((lsize = ((config1 >> 10) & 7)))
985 c->dcache.linesz = 2 << lsize;
986 else
987 c->dcache.linesz= lsize;
988 c->dcache.sets = 64 << ((config1 >> 13) & 7);
989 c->dcache.ways = 1 + ((config1 >> 7) & 7);
990
991 dcache_size = c->dcache.sets *
992 c->dcache.ways *
993 c->dcache.linesz;
994 c->dcache.waybit = ffs(dcache_size/c->dcache.ways) - 1;
995
996 c->options |= MIPS_CPU_PREFETCH;
997 break;
998 }
999
1000 /*
1001 * Processor configuration sanity check for the R4000SC erratum
1002 * #5. With page sizes larger than 32kB there is no possibility
1003 * to get a VCE exception anymore so we don't care about this
1004 * misconfiguration. The case is rather theoretical anyway;
1005 * presumably no vendor is shipping his hardware in the "bad"
1006 * configuration.
1007 */
1008 if ((prid & 0xff00) == PRID_IMP_R4000 && (prid & 0xff) < 0x40 &&
1009 !(config & CONF_SC) && c->icache.linesz != 16 &&
1010 PAGE_SIZE <= 0x8000)
1011 panic("Improper R4000SC processor configuration detected");
1012
1013 /* compute a couple of other cache variables */
1014 c->icache.waysize = icache_size / c->icache.ways;
1015 c->dcache.waysize = dcache_size / c->dcache.ways;
1016
1017 c->icache.sets = icache_size / (c->icache.linesz * c->icache.ways);
1018 c->dcache.sets = dcache_size / (c->dcache.linesz * c->dcache.ways);
1019
1020 /*
1021 * R10000 and R12000 P-caches are odd in a positive way. They're 32kB
1022 * 2-way virtually indexed so normally would suffer from aliases. So
1023 * normally they'd suffer from aliases but magic in the hardware deals
1024 * with that for us so we don't need to take care ourselves.
1025 */
d1e344e5 1026 switch (c->cputype) {
a95970f3 1027 case CPU_20KC:
505403b6 1028 case CPU_25KF:
d1e344e5
RB		 1029 case CPU_R10000:
1030 case CPU_R12000:
a95970f3 1031 case CPU_SB1:
d1e344e5
RB		 1032 break;
1033 case CPU_24K:
1034 if (!(read_c0_config7() & (1 << 16)))
1035 default:
ae6aafe3
RB		 1036 if (c->dcache.waysize > PAGE_SIZE)
1037 c->dcache.flags |= MIPS_CACHE_ALIASES;
d1e344e5 1038 }
1da177e4
LT		 1039
1040 switch (c->cputype) {
1041 case CPU_20KC:
1042 /*
1043 * Some older 20Kc chips doesn't have the 'VI' bit in
1044 * the config register.
1045 */
1046 c->icache.flags |= MIPS_CACHE_VTAG;
1047 break;
1048
e3ad1c23 1049 case CPU_AU1000:
1da177e4 1050 case CPU_AU1500:
e3ad1c23
PP		 1051 case CPU_AU1100:
1052 case CPU_AU1550:
1053 case CPU_AU1200:
1da177e4
LT		 1054 c->icache.flags |= MIPS_CACHE_IC_F_DC;
1055 break;
1056 }
1057
1058 printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n",
1059 icache_size >> 10,
1060 cpu_has_vtag_icache ? "virtually tagged" : "physically tagged",
1061 way_string[c->icache.ways], c->icache.linesz);
1062
1063 printk("Primary data cache %ldkB, %s, linesize %d bytes.\n",
1064 dcache_size >> 10, way_string[c->dcache.ways], c->dcache.linesz);
1065}
1066
1067/*
1068 * If you even _breathe_ on this function, look at the gcc output and make sure
1069 * it does not pop things on and off the stack for the cache sizing loop that
1070 * executes in KSEG1 space or else you will crash and burn badly. You have
1071 * been warned.
1072 */
1073static int __init probe_scache(void)
1074{
1075 extern unsigned long stext;
1076 unsigned long flags, addr, begin, end, pow2;
1077 unsigned int config = read_c0_config();
1078 struct cpuinfo_mips *c = &current_cpu_data;
1079 int tmp;
1080
1081 if (config & CONF_SC)
1082 return 0;
1083
1084 begin = (unsigned long) &stext;
1085 begin &= ~((4 * 1024 * 1024) - 1);
1086 end = begin + (4 * 1024 * 1024);
1087
1088 /*
1089 * This is such a bitch, you'd think they would make it easy to do
1090 * this. Away you daemons of stupidity!
1091 */
1092 local_irq_save(flags);
1093
1094 /* Fill each size-multiple cache line with a valid tag. */
1095 pow2 = (64 * 1024);
1096 for (addr = begin; addr < end; addr = (begin + pow2)) {
1097 unsigned long *p = (unsigned long *) addr;
1098 __asm__ __volatile__("nop" : : "r" (*p)); /* whee... */
1099 pow2 <<= 1;
1100 }
1101
1102 /* Load first line with zero (therefore invalid) tag. */
1103 write_c0_taglo(0);
1104 write_c0_taghi(0);
1105 __asm__ __volatile__("nop; nop; nop; nop;"); /* avoid the hazard */
1106 cache_op(Index_Store_Tag_I, begin);
1107 cache_op(Index_Store_Tag_D, begin);
1108 cache_op(Index_Store_Tag_SD, begin);
1109
1110 /* Now search for the wrap around point. */
1111 pow2 = (128 * 1024);
1112 tmp = 0;
1113 for (addr = begin + (128 * 1024); addr < end; addr = begin + pow2) {
1114 cache_op(Index_Load_Tag_SD, addr);
1115 __asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */
1116 if (!read_c0_taglo())
1117 break;
1118 pow2 <<= 1;
1119 }
1120 local_irq_restore(flags);
1121 addr -= begin;
1122
1123 scache_size = addr;
1124 c->scache.linesz = 16 << ((config & R4K_CONF_SB) >> 22);
1125 c->scache.ways = 1;
1126 c->dcache.waybit = 0; /* does not matter */
1127
1128 return 1;
1129}
1130
1da177e4
LT		 1131extern int r5k_sc_init(void);
1132extern int rm7k_sc_init(void);
1133
1134static void __init setup_scache(void)
1135{
1136 struct cpuinfo_mips *c = &current_cpu_data;
1137 unsigned int config = read_c0_config();
1da177e4
LT		 1138 int sc_present = 0;
1139
1140 /*
1141 * Do the probing thing on R4000SC and R4400SC processors. Other
1142 * processors don't have a S-cache that would be relevant to the
1143 * Linux memory managment.
1144 */
1145 switch (c->cputype) {
1146 case CPU_R4000SC:
1147 case CPU_R4000MC:
1148 case CPU_R4400SC:
1149 case CPU_R4400MC:
ba5187db 1150 sc_present = run_uncached(probe_scache);
1da177e4
LT		 1151 if (sc_present)
1152 c->options |= MIPS_CPU_CACHE_CDEX_S;
1153 break;
1154
1155 case CPU_R10000:
1156 case CPU_R12000:
1157 scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16);
1158 c->scache.linesz = 64 << ((config >> 13) & 1);
1159 c->scache.ways = 2;
1160 c->scache.waybit= 0;
1161 sc_present = 1;
1162 break;
1163
1164 case CPU_R5000:
1165 case CPU_NEVADA:
1166#ifdef CONFIG_R5000_CPU_SCACHE
1167 r5k_sc_init();
1168#endif
1169 return;
1170
1171 case CPU_RM7000:
1172 case CPU_RM9000:
1173#ifdef CONFIG_RM7000_CPU_SCACHE
1174 rm7k_sc_init();
1175#endif
1176 return;
1177
1178 default:
1179 sc_present = 0;
1180 }
1181
1182 if (!sc_present)
1183 return;
1184
1185 if ((c->isa_level == MIPS_CPU_ISA_M32 ||
1186 c->isa_level == MIPS_CPU_ISA_M64) &&
1187 !(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
1188 panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
1189
1190 /* compute a couple of other cache variables */
1191 c->scache.waysize = scache_size / c->scache.ways;
1192
1193 c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
1194
1195 printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1196 scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1197
1198 c->options |= MIPS_CPU_SUBSET_CACHES;
1199}
1200
1201static inline void coherency_setup(void)
1202{
1203 change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT);
1204
1205 /*
1206 * c0_status.cu=0 specifies that updates by the sc instruction use
1207 * the coherency mode specified by the TLB; 1 means cachable
1208 * coherent update on write will be used. Not all processors have
1209 * this bit and; some wire it to zero, others like Toshiba had the
1210 * silly idea of putting something else there ...
1211 */
1212 switch (current_cpu_data.cputype) {
1213 case CPU_R4000PC:
1214 case CPU_R4000SC:
1215 case CPU_R4000MC:
1216 case CPU_R4400PC:
1217 case CPU_R4400SC:
1218 case CPU_R4400MC:
1219 clear_c0_config(CONF_CU);
1220 break;
1221 }
1222}
1223
02cf2119 1224void __init r4k_cache_init(void)
1da177e4
LT		 1225{
1226 extern void build_clear_page(void);
1227 extern void build_copy_page(void);
1228 extern char except_vec2_generic;
1229 struct cpuinfo_mips *c = &current_cpu_data;
1230
1231 /* Default cache error handler for R4000 and R5000 family */
e01402b1 1232 set_uncached_handler (0x100, &except_vec2_generic, 0x80);
1da177e4
LT		 1233
1234 probe_pcache();
1235 setup_scache();
1236
1da177e4
LT		 1237 r4k_blast_dcache_page_setup();
1238 r4k_blast_dcache_page_indexed_setup();
1239 r4k_blast_dcache_setup();
1240 r4k_blast_icache_page_setup();
1241 r4k_blast_icache_page_indexed_setup();
1242 r4k_blast_icache_setup();
1243 r4k_blast_scache_page_setup();
1244 r4k_blast_scache_page_indexed_setup();
1245 r4k_blast_scache_setup();
1246
1247 /*
1248 * Some MIPS32 and MIPS64 processors have physically indexed caches.
1249 * This code supports virtually indexed processors and will be
1250 * unnecessarily inefficient on physically indexed processors.
1251 */
1252 shm_align_mask = max_t( unsigned long,
1253 c->dcache.sets * c->dcache.linesz - 1,
1254 PAGE_SIZE - 1);
1255
1256 flush_cache_all = r4k_flush_cache_all;
1257 __flush_cache_all = r4k___flush_cache_all;
1258 flush_cache_mm = r4k_flush_cache_mm;
1259 flush_cache_page = r4k_flush_cache_page;
1260 flush_icache_page = r4k_flush_icache_page;
1261 flush_cache_range = r4k_flush_cache_range;
1262
1263 flush_cache_sigtramp = r4k_flush_cache_sigtramp;
1264 flush_icache_all = r4k_flush_icache_all;
1265 flush_data_cache_page = r4k_flush_data_cache_page;
1266 flush_icache_range = r4k_flush_icache_range;
1267
1268#ifdef CONFIG_DMA_NONCOHERENT
1269 _dma_cache_wback_inv = r4k_dma_cache_wback_inv;
1270 _dma_cache_wback = r4k_dma_cache_wback_inv;
1271 _dma_cache_inv = r4k_dma_cache_inv;
1272#endif
1273
1da177e4
LT		 1274 build_clear_page();
1275 build_copy_page();
1d40cfcd
RB		 1276 local_r4k___flush_cache_all(NULL);
1277 coherency_setup();
1da177e4 1278}
kernel source for telekom puls (alcatel/mediatek)