[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / mips / mips-boards / malta / malta_setup.c

/*
 * Carsten Langgaard, carstenl@mips.com
 * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
 *
 *  This program is free software; you can distribute it and/or modify it
 *  under the terms of the GNU General Public License (Version 2) as
 *  published by the Free Software Foundation.
 *
 *  This program is distributed in the hope it will be useful, but WITHOUT
 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 *  for more details.
 *
 *  You should have received a copy of the GNU General Public License along
 *  with this program; if not, write to the Free Software Foundation, Inc.,
 *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
 */
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/ioport.h>
#include <linux/pci.h>
#include <linux/screen_info.h>

#include <asm/cpu.h>
#include <asm/bootinfo.h>
#include <asm/irq.h>
#include <asm/mips-boards/generic.h>
#include <asm/mips-boards/prom.h>
#include <asm/mips-boards/malta.h>
#include <asm/mips-boards/maltaint.h>
#include <asm/dma.h>
#include <asm/time.h>
#include <asm/traps.h>
#ifdef CONFIG_VT
#include <linux/console.h>
#endif

extern void mips_reboot_setup(void);
extern void mips_time_init(void);
extern unsigned long mips_rtc_get_time(void);

#ifdef CONFIG_KGDB
extern void kgdb_config(void);
#endif

struct resource standard_io_resources[] = {
	{ .name = "dma1", .start = 0x00, .end = 0x1f, .flags = IORESOURCE_BUSY },
	{ .name = "timer", .start = 0x40, .end = 0x5f, .flags = IORESOURCE_BUSY },
	{ .name = "keyboard", .start = 0x60, .end = 0x6f, .flags = IORESOURCE_BUSY },
	{ .name = "dma page reg", .start = 0x80, .end = 0x8f, .flags = IORESOURCE_BUSY },
	{ .name = "dma2", .start = 0xc0, .end = 0xdf, .flags = IORESOURCE_BUSY },
};

const char *get_system_type(void)
{
	return "MIPS Malta";
}

#ifdef CONFIG_BLK_DEV_FD
void __init fd_activate(void)
{
	/*
	 * Activate Floppy Controller in the SMSC FDC37M817 Super I/O
	 * Controller.
	 * Done by YAMON 2.00 onwards
	 */
	/* Entering config state. */
	SMSC_WRITE(SMSC_CONFIG_ENTER, SMSC_CONFIG_REG);

	/* Activate floppy controller. */
	SMSC_WRITE(SMSC_CONFIG_DEVNUM, SMSC_CONFIG_REG);
	SMSC_WRITE(SMSC_CONFIG_DEVNUM_FLOPPY, SMSC_DATA_REG);
	SMSC_WRITE(SMSC_CONFIG_ACTIVATE, SMSC_CONFIG_REG);
	SMSC_WRITE(SMSC_CONFIG_ACTIVATE_ENABLE, SMSC_DATA_REG);

	/* Exit config state. */
	SMSC_WRITE(SMSC_CONFIG_EXIT, SMSC_CONFIG_REG);
}
#endif

void __init plat_mem_setup(void)
{
	unsigned int i;

	mips_pcibios_init();

	/* Request I/O space for devices used on the Malta board. */
	for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)
		request_resource(&ioport_resource, standard_io_resources+i);

	/*
	 * Enable DMA channel 4 (cascade channel) in the PIIX4 south bridge.
	 */
	enable_dma(4);

#ifdef CONFIG_KGDB
	kgdb_config ();
#endif

	if ((mips_revision_corid == MIPS_REVISION_CORID_BONITO64) ||
	    (mips_revision_corid == MIPS_REVISION_CORID_CORE_20K) ||
	    (mips_revision_corid == MIPS_REVISION_CORID_CORE_EMUL_BON)) {
		char *argptr;

		argptr = prom_getcmdline();
		if (strstr(argptr, "debug")) {
			BONITO_BONGENCFG |= BONITO_BONGENCFG_DEBUGMODE;
			printk ("Enabled Bonito debug mode\n");
		}
		else
			BONITO_BONGENCFG &= ~BONITO_BONGENCFG_DEBUGMODE;

#ifdef CONFIG_DMA_COHERENT
		if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) {
			BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN;
			printk("Enabled Bonito CPU coherency\n");

			argptr = prom_getcmdline();
			if (strstr(argptr, "iobcuncached")) {
				BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN;
				BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG &
					~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
					  BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
				printk("Disabled Bonito IOBC coherency\n");
			}
			else {
				BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN;
				BONITO_PCIMEMBASECFG |=
					(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
					 BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
				printk("Enabled Bonito IOBC coherency\n");
			}
		}
		else
			panic("Hardware DMA cache coherency not supported");

#endif
	}
#ifdef CONFIG_DMA_COHERENT
	else {
		panic("Hardware DMA cache coherency not supported");
	}
#endif

#ifdef CONFIG_BLK_DEV_IDE
	/* Check PCI clock */
	{
		unsigned int __iomem *jmpr_p = (unsigned int *) ioremap(MALTA_JMPRS_REG, sizeof(unsigned int));
		int jmpr = (readw(jmpr_p) >> 2) & 0x07;
		static const int pciclocks[] __initdata = {
			33, 20, 25, 30, 12, 16, 37, 10
		};
		int pciclock = pciclocks[jmpr];
		char *argptr = prom_getcmdline();

		if (pciclock != 33 && !strstr (argptr, "idebus=")) {
			printk("WARNING: PCI clock is %dMHz, setting idebus\n", pciclock);
			argptr += strlen(argptr);
			sprintf (argptr, " idebus=%d", pciclock);
			if (pciclock < 20 || pciclock > 66)
				printk ("WARNING: IDE timing calculations will be incorrect\n");
		}
	}
#endif
#ifdef CONFIG_BLK_DEV_FD
	fd_activate ();
#endif
#ifdef CONFIG_VT
#if defined(CONFIG_VGA_CONSOLE)
	screen_info = (struct screen_info) {
		0, 25,			/* orig-x, orig-y */
		0,			/* unused */
		0,			/* orig-video-page */
		0,			/* orig-video-mode */
		80,			/* orig-video-cols */
		0,0,0,			/* ega_ax, ega_bx, ega_cx */
		25,			/* orig-video-lines */
		VIDEO_TYPE_VGAC,	/* orig-video-isVGA */
		16			/* orig-video-points */
	};
#endif
#endif
	mips_reboot_setup();

	board_time_init = mips_time_init;
	rtc_mips_get_time = mips_rtc_get_time;
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Carsten Langgaard, carstenl@mips.com
	3	* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
	4	*
	5	* This program is free software; you can distribute it and/or modify it
	6	* under the terms of the GNU General Public License (Version 2) as
	7	* published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	12	* for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License along
	15	* with this program; if not, write to the Free Software Foundation, Inc.,
	16	* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
	17	*/
1da177e4 LT	18	#include <linux/init.h>
	19	#include <linux/sched.h>
	20	#include <linux/ioport.h>
	21	#include <linux/pci.h>
894673ee	22	#include <linux/screen_info.h>
1da177e4	23
1da177e4 LT	24	#include <asm/cpu.h>
	25	#include <asm/bootinfo.h>
	26	#include <asm/irq.h>
	27	#include <asm/mips-boards/generic.h>
	28	#include <asm/mips-boards/prom.h>
	29	#include <asm/mips-boards/malta.h>
	30	#include <asm/mips-boards/maltaint.h>
	31	#include <asm/dma.h>
	32	#include <asm/time.h>
	33	#include <asm/traps.h>
	34	#ifdef CONFIG_VT
	35	#include <linux/console.h>
	36	#endif
	37
	38	extern void mips_reboot_setup(void);
	39	extern void mips_time_init(void);
1da177e4 LT	40	extern unsigned long mips_rtc_get_time(void);
	41
	42	#ifdef CONFIG_KGDB
	43	extern void kgdb_config(void);
	44	#endif
	45
	46	struct resource standard_io_resources[] = {
5e46c3ae RB	47	{ .name = "dma1", .start = 0x00, .end = 0x1f, .flags = IORESOURCE_BUSY },
	48	{ .name = "timer", .start = 0x40, .end = 0x5f, .flags = IORESOURCE_BUSY },
	49	{ .name = "keyboard", .start = 0x60, .end = 0x6f, .flags = IORESOURCE_BUSY },
	50	{ .name = "dma page reg", .start = 0x80, .end = 0x8f, .flags = IORESOURCE_BUSY },
	51	{ .name = "dma2", .start = 0xc0, .end = 0xdf, .flags = IORESOURCE_BUSY },
1da177e4 LT	52	};
1da177e4 LT	53
1da177e4 LT	54	const char *get_system_type(void)
	55	{
	56	return "MIPS Malta";
	57	}
	58
	59	#ifdef CONFIG_BLK_DEV_FD
	60	void __init fd_activate(void)
	61	{
	62	/*
	63	* Activate Floppy Controller in the SMSC FDC37M817 Super I/O
	64	* Controller.
	65	* Done by YAMON 2.00 onwards
	66	*/
	67	/* Entering config state. */
	68	SMSC_WRITE(SMSC_CONFIG_ENTER, SMSC_CONFIG_REG);
	69
	70	/* Activate floppy controller. */
	71	SMSC_WRITE(SMSC_CONFIG_DEVNUM, SMSC_CONFIG_REG);
	72	SMSC_WRITE(SMSC_CONFIG_DEVNUM_FLOPPY, SMSC_DATA_REG);
	73	SMSC_WRITE(SMSC_CONFIG_ACTIVATE, SMSC_CONFIG_REG);
	74	SMSC_WRITE(SMSC_CONFIG_ACTIVATE_ENABLE, SMSC_DATA_REG);
	75
	76	/* Exit config state. */
	77	SMSC_WRITE(SMSC_CONFIG_EXIT, SMSC_CONFIG_REG);
	78	}
	79	#endif
	80
2925aba4	81	void __init plat_mem_setup(void)
1da177e4 LT	82	{
	83	unsigned int i;
	84
c83cfc9c RB	85	mips_pcibios_init();
c83cfc9c RB	86
1da177e4 LT	87	/* Request I/O space for devices used on the Malta board. */
	88	for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)
	89	request_resource(&ioport_resource, standard_io_resources+i);
	90
	91	/*
	92	* Enable DMA channel 4 (cascade channel) in the PIIX4 south bridge.
	93	*/
	94	enable_dma(4);
	95
	96	#ifdef CONFIG_KGDB
	97	kgdb_config ();
	98	#endif
	99
	100	if ((mips_revision_corid == MIPS_REVISION_CORID_BONITO64) \|\|
	101	(mips_revision_corid == MIPS_REVISION_CORID_CORE_20K) \|\|
	102	(mips_revision_corid == MIPS_REVISION_CORID_CORE_EMUL_BON)) {
	103	char *argptr;
	104
	105	argptr = prom_getcmdline();
	106	if (strstr(argptr, "debug")) {
	107	BONITO_BONGENCFG \|= BONITO_BONGENCFG_DEBUGMODE;
	108	printk ("Enabled Bonito debug mode\n");
	109	}
	110	else
	111	BONITO_BONGENCFG &= ~BONITO_BONGENCFG_DEBUGMODE;
	112
	113	#ifdef CONFIG_DMA_COHERENT
	114	if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) {
	115	BONITO_PCICACHECTRL \|= BONITO_PCICACHECTRL_CPUCOH_EN;
	116	printk("Enabled Bonito CPU coherency\n");
	117
	118	argptr = prom_getcmdline();
	119	if (strstr(argptr, "iobcuncached")) {
	120	BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN;
42a3b4f2	121	BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG &
1da177e4 LT	122	~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED \|
	123	BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
	124	printk("Disabled Bonito IOBC coherency\n");
	125	}
	126	else {
	127	BONITO_PCICACHECTRL \|= BONITO_PCICACHECTRL_IOBCCOH_EN;
42a3b4f2 RB	128	BONITO_PCIMEMBASECFG \|=
42a3b4f2 RB	129	(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED \|
1da177e4	130	BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
177b2927	131	printk("Enabled Bonito IOBC coherency\n");
1da177e4 LT	132	}
	133	}
	134	else
	135	panic("Hardware DMA cache coherency not supported");
	136
	137	#endif
	138	}
	139	#ifdef CONFIG_DMA_COHERENT
	140	else {
	141	panic("Hardware DMA cache coherency not supported");
	142	}
	143	#endif
	144
	145	#ifdef CONFIG_BLK_DEV_IDE
	146	/* Check PCI clock */
	147	{
f1974653 RB	148	unsigned int __iomem jmpr_p = (unsigned int ) ioremap(MALTA_JMPRS_REG, sizeof(unsigned int));
f1974653 RB	149	int jmpr = (readw(jmpr_p) >> 2) & 0x07;
1da177e4 LT	150	static const int pciclocks[] __initdata = {
	151	33, 20, 25, 30, 12, 16, 37, 10
	152	};
	153	int pciclock = pciclocks[jmpr];
	154	char *argptr = prom_getcmdline();
	155
	156	if (pciclock != 33 && !strstr (argptr, "idebus=")) {
	157	printk("WARNING: PCI clock is %dMHz, setting idebus\n", pciclock);
	158	argptr += strlen(argptr);
	159	sprintf (argptr, " idebus=%d", pciclock);
	160	if (pciclock < 20 \|\| pciclock > 66)
	161	printk ("WARNING: IDE timing calculations will be incorrect\n");
	162	}
	163	}
	164	#endif
	165	#ifdef CONFIG_BLK_DEV_FD
	166	fd_activate ();
	167	#endif
	168	#ifdef CONFIG_VT
	169	#if defined(CONFIG_VGA_CONSOLE)
	170	screen_info = (struct screen_info) {
	171	0, 25, /* orig-x, orig-y */
	172	0, /* unused */
	173	0, /* orig-video-page */
	174	0, /* orig-video-mode */
	175	80, /* orig-video-cols */
	176	0,0,0, /* ega_ax, ega_bx, ega_cx */
	177	25, /* orig-video-lines */
	178	VIDEO_TYPE_VGAC, /* orig-video-isVGA */
	179	16 /* orig-video-points */
	180	};
	181	#endif
	182	#endif
1da177e4 LT	183	mips_reboot_setup();
	184
	185	board_time_init = mips_time_init;
d23ee8fe	186	rtc_mips_get_time = mips_rtc_get_time;
1da177e4	187	}