[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / mips / mips-boards / atlas / atlas_int.c

/*
 * Copyright (C) 1999, 2000, 2006  MIPS Technologies, Inc.
 *	All rights reserved.
 *	Authors: Carsten Langgaard <carstenl@mips.com>
 *		 Maciej W. Rozycki <macro@mips.com>
 *
 * ########################################################################
 *
 *  This program is free software; you can distribute it and/or modify it
 *  under the terms of the GNU General Public License (Version 2) as
 *  published by the Free Software Foundation.
 *
 *  This program is distributed in the hope it will be useful, but WITHOUT
 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 *  for more details.
 *
 *  You should have received a copy of the GNU General Public License along
 *  with this program; if not, write to the Free Software Foundation, Inc.,
 *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
 *
 * ########################################################################
 *
 * Routines for generic manipulation of the interrupts found on the MIPS
 * Atlas board.
 *
 */
#include <linux/compiler.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/kernel_stat.h>
#include <linux/kernel.h>

#include <asm/gdb-stub.h>
#include <asm/io.h>
#include <asm/irq_cpu.h>
#include <asm/msc01_ic.h>

#include <asm/mips-boards/atlas.h>
#include <asm/mips-boards/atlasint.h>
#include <asm/mips-boards/generic.h>

static struct atlas_ictrl_regs *atlas_hw0_icregs;

#if 0
#define DEBUG_INT(x...) printk(x)
#else
#define DEBUG_INT(x...)
#endif

void disable_atlas_irq(unsigned int irq_nr)
{
	atlas_hw0_icregs->intrsten = 1 << (irq_nr - ATLAS_INT_BASE);
	iob();
}

void enable_atlas_irq(unsigned int irq_nr)
{
	atlas_hw0_icregs->intseten = 1 << (irq_nr - ATLAS_INT_BASE);
	iob();
}

static void end_atlas_irq(unsigned int irq)
{
	if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
		enable_atlas_irq(irq);
}

static struct irq_chip atlas_irq_type = {
	.name = "Atlas",
	.ack = disable_atlas_irq,
	.mask = disable_atlas_irq,
	.mask_ack = disable_atlas_irq,
	.unmask = enable_atlas_irq,
	.eoi = enable_atlas_irq,
	.end = end_atlas_irq,
};

static inline int ls1bit32(unsigned int x)
{
	int b = 31, s;

	s = 16; if (x << 16 == 0) s = 0; b -= s; x <<= s;
	s =  8; if (x <<  8 == 0) s = 0; b -= s; x <<= s;
	s =  4; if (x <<  4 == 0) s = 0; b -= s; x <<= s;
	s =  2; if (x <<  2 == 0) s = 0; b -= s; x <<= s;
	s =  1; if (x <<  1 == 0) s = 0; b -= s;

	return b;
}

static inline void atlas_hw0_irqdispatch(void)
{
	unsigned long int_status;
	int irq;

	int_status = atlas_hw0_icregs->intstatus;

	/* if int_status == 0, then the interrupt has already been cleared */
	if (unlikely(int_status == 0))
		return;

	irq = ATLAS_INT_BASE + ls1bit32(int_status);

	DEBUG_INT("atlas_hw0_irqdispatch: irq=%d\n", irq);

	do_IRQ(irq);
}

static inline int clz(unsigned long x)
{
	__asm__ (
	"	.set	push					\n"
	"	.set	mips32					\n"
	"	clz	%0, %1					\n"
	"	.set	pop					\n"
	: "=r" (x)
	: "r" (x));

	return x;
}

/*
 * Version of ffs that only looks at bits 12..15.
 */
static inline unsigned int irq_ffs(unsigned int pending)
{
#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
	return -clz(pending) + 31 - CAUSEB_IP;
#else
	unsigned int a0 = 7;
	unsigned int t0;

	t0 = s0 & 0xf000;
	t0 = t0 < 1;
	t0 = t0 << 2;
	a0 = a0 - t0;
	s0 = s0 << t0;

	t0 = s0 & 0xc000;
	t0 = t0 < 1;
	t0 = t0 << 1;
	a0 = a0 - t0;
	s0 = s0 << t0;

	t0 = s0 & 0x8000;
	t0 = t0 < 1;
	//t0 = t0 << 2;
	a0 = a0 - t0;
	//s0 = s0 << t0;

	return a0;
#endif
}

/*
 * IRQs on the Atlas board look basically like (all external interrupt
 * sources are combined together on hardware interrupt 0 (MIPS IRQ 2)):
 *
 *      MIPS IRQ        Source
 *      --------        ------
 *             0        Software 0 (reschedule IPI on MT)
 *             1        Software 1 (remote call IPI on MT)
 *             2        Combined Atlas hardware interrupt (hw0)
 *             3        Hardware (ignored)
 *             4        Hardware (ignored)
 *             5        Hardware (ignored)
 *             6        Hardware (ignored)
 *             7        R4k timer (what we use)
 *
 * We handle the IRQ according to _our_ priority which is:
 *
 * Highest ----     R4k Timer
 * Lowest  ----     Software 0
 *
 * then we just return, if multiple IRQs are pending then we will just take
 * another exception, big deal.
 */
asmlinkage void plat_irq_dispatch(void)
{
	unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
	int irq;

	irq = irq_ffs(pending);

	if (irq == MIPSCPU_INT_ATLAS)
		atlas_hw0_irqdispatch();
	else if (irq >= 0)
		do_IRQ(MIPSCPU_INT_BASE + irq);
	else
		spurious_interrupt();
}

static inline void init_atlas_irqs (int base)
{
	int i;

	atlas_hw0_icregs = (struct atlas_ictrl_regs *)
			   ioremap(ATLAS_ICTRL_REGS_BASE,
				   sizeof(struct atlas_ictrl_regs *));

	/*
	 * Mask out all interrupt by writing "1" to all bit position in
	 * the interrupt reset reg.
	 */
	atlas_hw0_icregs->intrsten = 0xffffffff;

	for (i = ATLAS_INT_BASE; i <= ATLAS_INT_END; i++)
		set_irq_chip_and_handler(i, &atlas_irq_type, handle_level_irq);
}

static struct irqaction atlasirq = {
	.handler = no_action,
	.name = "Atlas cascade"
};

msc_irqmap_t __initdata msc_irqmap[] = {
	{MSC01C_INT_TMR,		MSC01_IRQ_EDGE, 0},
	{MSC01C_INT_PCI,		MSC01_IRQ_LEVEL, 0},
};
int __initdata msc_nr_irqs = ARRAY_SIZE(msc_irqmap);

msc_irqmap_t __initdata msc_eicirqmap[] = {
	{MSC01E_INT_SW0,		MSC01_IRQ_LEVEL, 0},
	{MSC01E_INT_SW1,		MSC01_IRQ_LEVEL, 0},
	{MSC01E_INT_ATLAS,		MSC01_IRQ_LEVEL, 0},
	{MSC01E_INT_TMR,		MSC01_IRQ_EDGE, 0},
	{MSC01E_INT_PCI,		MSC01_IRQ_LEVEL, 0},
	{MSC01E_INT_PERFCTR,		MSC01_IRQ_LEVEL, 0},
	{MSC01E_INT_CPUCTR,		MSC01_IRQ_LEVEL, 0}
};
int __initdata msc_nr_eicirqs = ARRAY_SIZE(msc_eicirqmap);

void __init arch_init_irq(void)
{
	init_atlas_irqs(ATLAS_INT_BASE);

	if (!cpu_has_veic)
		mips_cpu_irq_init();

	switch(mips_revision_corid) {
	case MIPS_REVISION_CORID_CORE_MSC:
	case MIPS_REVISION_CORID_CORE_FPGA2:
	case MIPS_REVISION_CORID_CORE_FPGA3:
	case MIPS_REVISION_CORID_CORE_24K:
	case MIPS_REVISION_CORID_CORE_EMUL_MSC:
		if (cpu_has_veic)
			init_msc_irqs (MSC01E_INT_BASE,
				       msc_eicirqmap, msc_nr_eicirqs);
		else
			init_msc_irqs (MSC01C_INT_BASE,
				       msc_irqmap, msc_nr_irqs);
	}


	if (cpu_has_veic) {
		set_vi_handler (MSC01E_INT_ATLAS, atlas_hw0_irqdispatch);
		setup_irq (MSC01E_INT_BASE + MSC01E_INT_ATLAS, &atlasirq);
	} else if (cpu_has_vint) {
		set_vi_handler (MIPSCPU_INT_ATLAS, atlas_hw0_irqdispatch);
#ifdef CONFIG_MIPS_MT_SMTC
		setup_irq_smtc (MIPSCPU_INT_BASE + MIPSCPU_INT_ATLAS,
				&atlasirq, (0x100 << MIPSCPU_INT_ATLAS));
#else /* Not SMTC */
		setup_irq(MIPSCPU_INT_BASE + MIPSCPU_INT_ATLAS, &atlasirq);
#endif /* CONFIG_MIPS_MT_SMTC */
	} else
		setup_irq(MIPSCPU_INT_BASE + MIPSCPU_INT_ATLAS, &atlasirq);
}
Commit	Line	Data
1da177e4	1	/*
fc095a90 MR	2	* Copyright (C) 1999, 2000, 2006 MIPS Technologies, Inc.
	3	* All rights reserved.
	4	* Authors: Carsten Langgaard <carstenl@mips.com>
	5	* Maciej W. Rozycki <macro@mips.com>
1da177e4 LT	6	*
	7	* ########################################################################
	8	*
	9	* This program is free software; you can distribute it and/or modify it
	10	* under the terms of the GNU General Public License (Version 2) as
	11	* published by the Free Software Foundation.
	12	*
	13	* This program is distributed in the hope it will be useful, but WITHOUT
	14	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	15	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	16	* for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License along
	19	* with this program; if not, write to the Free Software Foundation, Inc.,
	20	* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
	21	*
	22	* ########################################################################
	23	*
	24	* Routines for generic manipulation of the interrupts found on the MIPS
	25	* Atlas board.
	26	*
	27	*/
	28	#include <linux/compiler.h>
	29	#include <linux/init.h>
fc095a90	30	#include <linux/irq.h>
1da177e4 LT	31	#include <linux/sched.h>
	32	#include <linux/slab.h>
	33	#include <linux/interrupt.h>
	34	#include <linux/kernel_stat.h>
25b8ac3b	35	#include <linux/kernel.h>
1da177e4	36
fc095a90	37	#include <asm/gdb-stub.h>
1da177e4	38	#include <asm/io.h>
fc095a90 MR	39	#include <asm/irq_cpu.h>
	40	#include <asm/msc01_ic.h>
	41
1da177e4 LT	42	#include <asm/mips-boards/atlas.h>
1da177e4 LT	43	#include <asm/mips-boards/atlasint.h>
fc095a90	44	#include <asm/mips-boards/generic.h>
1da177e4 LT	45
	46	static struct atlas_ictrl_regs *atlas_hw0_icregs;
	47
1da177e4 LT	48	#if 0
	49	#define DEBUG_INT(x...) printk(x)
	50	#else
	51	#define DEBUG_INT(x...)
	52	#endif
	53
	54	void disable_atlas_irq(unsigned int irq_nr)
	55	{
fc095a90	56	atlas_hw0_icregs->intrsten = 1 << (irq_nr - ATLAS_INT_BASE);
1da177e4 LT	57	iob();
	58	}
	59
	60	void enable_atlas_irq(unsigned int irq_nr)
	61	{
fc095a90	62	atlas_hw0_icregs->intseten = 1 << (irq_nr - ATLAS_INT_BASE);
1da177e4 LT	63	iob();
	64	}
	65
1da177e4 LT	66	static void end_atlas_irq(unsigned int irq)
	67	{
	68	if (!(irq_desc[irq].status & (IRQ_DISABLED\|IRQ_INPROGRESS)))
	69	enable_atlas_irq(irq);
	70	}
	71
94dee171	72	static struct irq_chip atlas_irq_type = {
70d21cde	73	.name = "Atlas",
1603b5ac AN	74	.ack = disable_atlas_irq,
	75	.mask = disable_atlas_irq,
	76	.mask_ack = disable_atlas_irq,
	77	.unmask = enable_atlas_irq,
1417836e	78	.eoi = enable_atlas_irq,
8ab00b9a	79	.end = end_atlas_irq,
1da177e4 LT	80	};
	81
	82	static inline int ls1bit32(unsigned int x)
	83	{
	84	int b = 31, s;
	85
	86	s = 16; if (x << 16 == 0) s = 0; b -= s; x <<= s;
	87	s = 8; if (x << 8 == 0) s = 0; b -= s; x <<= s;
	88	s = 4; if (x << 4 == 0) s = 0; b -= s; x <<= s;
	89	s = 2; if (x << 2 == 0) s = 0; b -= s; x <<= s;
	90	s = 1; if (x << 1 == 0) s = 0; b -= s;
	91
	92	return b;
	93	}
	94
937a8015	95	static inline void atlas_hw0_irqdispatch(void)
1da177e4 LT	96	{
	97	unsigned long int_status;
	98	int irq;
	99
	100	int_status = atlas_hw0_icregs->intstatus;
	101
	102	/* if int_status == 0, then the interrupt has already been cleared */
	103	if (unlikely(int_status == 0))
	104	return;
	105
fc095a90	106	irq = ATLAS_INT_BASE + ls1bit32(int_status);
1da177e4 LT	107
	108	DEBUG_INT("atlas_hw0_irqdispatch: irq=%d\n", irq);
	109
937a8015	110	do_IRQ(irq);
1da177e4 LT	111	}
1da177e4 LT	112
e4ac58af RB	113	static inline int clz(unsigned long x)
	114	{
	115	__asm__ (
	116	" .set push \n"
	117	" .set mips32 \n"
	118	" clz %0, %1 \n"
	119	" .set pop \n"
	120	: "=r" (x)
	121	: "r" (x));
	122
	123	return x;
	124	}
	125
	126	/*
	127	* Version of ffs that only looks at bits 12..15.
	128	*/
	129	static inline unsigned int irq_ffs(unsigned int pending)
	130	{
	131	#if defined(CONFIG_CPU_MIPS32) \|\| defined(CONFIG_CPU_MIPS64)
	132	return -clz(pending) + 31 - CAUSEB_IP;
	133	#else
	134	unsigned int a0 = 7;
	135	unsigned int t0;
	136
	137	t0 = s0 & 0xf000;
	138	t0 = t0 < 1;
	139	t0 = t0 << 2;
	140	a0 = a0 - t0;
	141	s0 = s0 << t0;
	142
	143	t0 = s0 & 0xc000;
	144	t0 = t0 < 1;
	145	t0 = t0 << 1;
	146	a0 = a0 - t0;
	147	s0 = s0 << t0;
	148
	149	t0 = s0 & 0x8000;
	150	t0 = t0 < 1;
	151	//t0 = t0 << 2;
	152	a0 = a0 - t0;
	153	//s0 = s0 << t0;
	154
	155	return a0;
	156	#endif
	157	}
	158
	159	/*
fc095a90 MR	160	* IRQs on the Atlas board look basically like (all external interrupt
fc095a90 MR	161	* sources are combined together on hardware interrupt 0 (MIPS IRQ 2)):
e4ac58af	162	*
fc095a90	163	* MIPS IRQ Source
e4ac58af	164	* -------- ------
fc095a90 MR	165	* 0 Software 0 (reschedule IPI on MT)
	166	* 1 Software 1 (remote call IPI on MT)
	167	* 2 Combined Atlas hardware interrupt (hw0)
e4ac58af RB	168	* 3 Hardware (ignored)
	169	* 4 Hardware (ignored)
	170	* 5 Hardware (ignored)
	171	* 6 Hardware (ignored)
	172	* 7 R4k timer (what we use)
	173	*
	174	* We handle the IRQ according to _our_ priority which is:
	175	*
	176	* Highest ---- R4k Timer
fc095a90	177	* Lowest ---- Software 0
e4ac58af RB	178	*
	179	* then we just return, if multiple IRQs are pending then we will just take
	180	* another exception, big deal.
	181	*/
937a8015	182	asmlinkage void plat_irq_dispatch(void)
e4ac58af RB	183	{
	184	unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
	185	int irq;
	186
	187	irq = irq_ffs(pending);
	188
	189	if (irq == MIPSCPU_INT_ATLAS)
937a8015	190	atlas_hw0_irqdispatch();
fc095a90	191	else if (irq >= 0)
937a8015	192	do_IRQ(MIPSCPU_INT_BASE + irq);
e4ac58af	193	else
937a8015	194	spurious_interrupt();
e4ac58af RB	195	}
e4ac58af RB	196
fc095a90	197	static inline void init_atlas_irqs (int base)
1da177e4 LT	198	{
	199	int i;
	200
fc095a90 MR	201	atlas_hw0_icregs = (struct atlas_ictrl_regs *)
	202	ioremap(ATLAS_ICTRL_REGS_BASE,
	203	sizeof(struct atlas_ictrl_regs *));
42a3b4f2	204
1da177e4 LT	205	/*
	206	* Mask out all interrupt by writing "1" to all bit position in
	207	* the interrupt reset reg.
	208	*/
	209	atlas_hw0_icregs->intrsten = 0xffffffff;
	210
1603b5ac	211	for (i = ATLAS_INT_BASE; i <= ATLAS_INT_END; i++)
1417836e	212	set_irq_chip_and_handler(i, &atlas_irq_type, handle_level_irq);
1da177e4	213	}
fc095a90 MR	214
	215	static struct irqaction atlasirq = {
	216	.handler = no_action,
	217	.name = "Atlas cascade"
	218	};
	219
	220	msc_irqmap_t __initdata msc_irqmap[] = {
	221	{MSC01C_INT_TMR, MSC01_IRQ_EDGE, 0},
	222	{MSC01C_INT_PCI, MSC01_IRQ_LEVEL, 0},
	223	};
25b8ac3b	224	int __initdata msc_nr_irqs = ARRAY_SIZE(msc_irqmap);
fc095a90 MR	225
	226	msc_irqmap_t __initdata msc_eicirqmap[] = {
	227	{MSC01E_INT_SW0, MSC01_IRQ_LEVEL, 0},
	228	{MSC01E_INT_SW1, MSC01_IRQ_LEVEL, 0},
	229	{MSC01E_INT_ATLAS, MSC01_IRQ_LEVEL, 0},
	230	{MSC01E_INT_TMR, MSC01_IRQ_EDGE, 0},
	231	{MSC01E_INT_PCI, MSC01_IRQ_LEVEL, 0},
	232	{MSC01E_INT_PERFCTR, MSC01_IRQ_LEVEL, 0},
	233	{MSC01E_INT_CPUCTR, MSC01_IRQ_LEVEL, 0}
	234	};
25b8ac3b	235	int __initdata msc_nr_eicirqs = ARRAY_SIZE(msc_eicirqmap);
fc095a90 MR	236
	237	void __init arch_init_irq(void)
	238	{
	239	init_atlas_irqs(ATLAS_INT_BASE);
	240
	241	if (!cpu_has_veic)
97dcb82d	242	mips_cpu_irq_init();
fc095a90 MR	243
	244	switch(mips_revision_corid) {
	245	case MIPS_REVISION_CORID_CORE_MSC:
	246	case MIPS_REVISION_CORID_CORE_FPGA2:
	247	case MIPS_REVISION_CORID_CORE_FPGA3:
	248	case MIPS_REVISION_CORID_CORE_24K:
	249	case MIPS_REVISION_CORID_CORE_EMUL_MSC:
	250	if (cpu_has_veic)
	251	init_msc_irqs (MSC01E_INT_BASE,
	252	msc_eicirqmap, msc_nr_eicirqs);
	253	else
	254	init_msc_irqs (MSC01C_INT_BASE,
	255	msc_irqmap, msc_nr_irqs);
	256	}
	257
	258
	259	if (cpu_has_veic) {
	260	set_vi_handler (MSC01E_INT_ATLAS, atlas_hw0_irqdispatch);
	261	setup_irq (MSC01E_INT_BASE + MSC01E_INT_ATLAS, &atlasirq);
	262	} else if (cpu_has_vint) {
	263	set_vi_handler (MIPSCPU_INT_ATLAS, atlas_hw0_irqdispatch);
	264	#ifdef CONFIG_MIPS_MT_SMTC
	265	setup_irq_smtc (MIPSCPU_INT_BASE + MIPSCPU_INT_ATLAS,
	266	&atlasirq, (0x100 << MIPSCPU_INT_ATLAS));
	267	#else /* Not SMTC */
	268	setup_irq(MIPSCPU_INT_BASE + MIPSCPU_INT_ATLAS, &atlasirq);
	269	#endif /* CONFIG_MIPS_MT_SMTC */
	270	} else
	271	setup_irq(MIPSCPU_INT_BASE + MIPSCPU_INT_ATLAS, &atlasirq);
	272	}