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[MIPS] Fixup printk in mips_srs_init.
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / mips / kernel / traps.c
CommitLineData
1da177e4
LT		 1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
36ccf1c0 6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
1da177e4
LT		 7 * Copyright (C) 1995, 1996 Paul M. Antoine
8 * Copyright (C) 1998 Ulf Carlsson
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
11 * Copyright (C) 2000, 01 MIPS Technologies, Inc.
3b2396d9 12 * Copyright (C) 2002, 2003, 2004, 2005 Maciej W. Rozycki
1da177e4
LT		 13 */
14#include <linux/config.h>
15#include <linux/init.h>
16#include <linux/mm.h>
17#include <linux/module.h>
18#include <linux/sched.h>
19#include <linux/smp.h>
20#include <linux/smp_lock.h>
21#include <linux/spinlock.h>
22#include <linux/kallsyms.h>
e01402b1 23#include <linux/bootmem.h>
1da177e4
LT		 24
25#include <asm/bootinfo.h>
26#include <asm/branch.h>
27#include <asm/break.h>
28#include <asm/cpu.h>
e50c0a8f 29#include <asm/dsp.h>
1da177e4 30#include <asm/fpu.h>
340ee4b9
RB		 31#include <asm/mipsregs.h>
32#include <asm/mipsmtregs.h>
1da177e4
LT		 33#include <asm/module.h>
34#include <asm/pgtable.h>
35#include <asm/ptrace.h>
36#include <asm/sections.h>
37#include <asm/system.h>
38#include <asm/tlbdebug.h>
39#include <asm/traps.h>
40#include <asm/uaccess.h>
41#include <asm/mmu_context.h>
42#include <asm/watch.h>
43#include <asm/types.h>
44
45extern asmlinkage void handle_tlbm(void);
46extern asmlinkage void handle_tlbl(void);
47extern asmlinkage void handle_tlbs(void);
48extern asmlinkage void handle_adel(void);
49extern asmlinkage void handle_ades(void);
50extern asmlinkage void handle_ibe(void);
51extern asmlinkage void handle_dbe(void);
52extern asmlinkage void handle_sys(void);
53extern asmlinkage void handle_bp(void);
54extern asmlinkage void handle_ri(void);
55extern asmlinkage void handle_cpu(void);
56extern asmlinkage void handle_ov(void);
57extern asmlinkage void handle_tr(void);
58extern asmlinkage void handle_fpe(void);
59extern asmlinkage void handle_mdmx(void);
60extern asmlinkage void handle_watch(void);
340ee4b9 61extern asmlinkage void handle_mt(void);
e50c0a8f 62extern asmlinkage void handle_dsp(void);
1da177e4
LT		 63extern asmlinkage void handle_mcheck(void);
64extern asmlinkage void handle_reserved(void);
65
12616ed2 66extern int fpu_emulator_cop1Handler(struct pt_regs *xcp,
1da177e4
LT		 67 struct mips_fpu_soft_struct *ctx);
68
69void (*board_be_init)(void);
70int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
e01402b1
RB		 71void (*board_nmi_handler_setup)(void);
72void (*board_ejtag_handler_setup)(void);
73void (*board_bind_eic_interrupt)(int irq, int regset);
1da177e4
LT		 74
75/*
76 * These constant is for searching for possible module text segments.
77 * MODULE_RANGE is a guess of how much space is likely to be vmalloced.
78 */
79#define MODULE_RANGE (8*1024*1024)
80
81/*
82 * This routine abuses get_user()/put_user() to reference pointers
83 * with at least a bit of error checking ...
84 */
85void show_stack(struct task_struct *task, unsigned long *sp)
86{
87 const int field = 2 * sizeof(unsigned long);
88 long stackdata;
89 int i;
90
91 if (!sp) {
92 if (task && task != current)
93 sp = (unsigned long *) task->thread.reg29;
94 else
95 sp = (unsigned long *) &sp;
96 }
97
98 printk("Stack :");
99 i = 0;
100 while ((unsigned long) sp & (PAGE_SIZE - 1)) {
101 if (i && ((i % (64 / field)) == 0))
102 printk("\n ");
103 if (i > 39) {
104 printk(" ...");
105 break;
106 }
107
108 if (__get_user(stackdata, sp++)) {
109 printk(" (Bad stack address)");
110 break;
111 }
112
113 printk(" %0*lx", field, stackdata);
114 i++;
115 }
116 printk("\n");
117}
118
119void show_trace(struct task_struct *task, unsigned long *stack)
120{
121 const int field = 2 * sizeof(unsigned long);
122 unsigned long addr;
123
124 if (!stack) {
125 if (task && task != current)
126 stack = (unsigned long *) task->thread.reg29;
127 else
128 stack = (unsigned long *) &stack;
129 }
130
131 printk("Call Trace:");
132#ifdef CONFIG_KALLSYMS
133 printk("\n");
134#endif
135 while (!kstack_end(stack)) {
136 addr = *stack++;
137 if (__kernel_text_address(addr)) {
138 printk(" [<%0*lx>] ", field, addr);
139 print_symbol("%s\n", addr);
140 }
141 }
142 printk("\n");
143}
144
145/*
146 * The architecture-independent dump_stack generator
147 */
148void dump_stack(void)
149{
150 unsigned long stack;
151
152 show_trace(current, &stack);
153}
154
155EXPORT_SYMBOL(dump_stack);
156
157void show_code(unsigned int *pc)
158{
159 long i;
160
161 printk("\nCode:");
162
163 for(i = -3 ; i < 6 ; i++) {
164 unsigned int insn;
165 if (__get_user(insn, pc + i)) {
166 printk(" (Bad address in epc)\n");
167 break;
168 }
169 printk("%c%08x%c", (i?' ':'<'), insn, (i?' ':'>'));
170 }
171}
172
173void show_regs(struct pt_regs *regs)
174{
175 const int field = 2 * sizeof(unsigned long);
176 unsigned int cause = regs->cp0_cause;
177 int i;
178
179 printk("Cpu %d\n", smp_processor_id());
180
181 /*
182 * Saved main processor registers
183 */
184 for (i = 0; i < 32; ) {
185 if ((i % 4) == 0)
186 printk("$%2d :", i);
187 if (i == 0)
188 printk(" %0*lx", field, 0UL);
189 else if (i == 26 || i == 27)
190 printk(" %*s", field, "");
191 else
192 printk(" %0*lx", field, regs->regs[i]);
193
194 i++;
195 if ((i % 4) == 0)
196 printk("\n");
197 }
198
199 printk("Hi : %0*lx\n", field, regs->hi);
200 printk("Lo : %0*lx\n", field, regs->lo);
201
202 /*
203 * Saved cp0 registers
204 */
205 printk("epc : %0*lx ", field, regs->cp0_epc);
206 print_symbol("%s ", regs->cp0_epc);
207 printk(" %s\n", print_tainted());
208 printk("ra : %0*lx ", field, regs->regs[31]);
209 print_symbol("%s\n", regs->regs[31]);
210
211 printk("Status: %08x ", (uint32_t) regs->cp0_status);
212
3b2396d9
MR		 213 if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) {
214 if (regs->cp0_status & ST0_KUO)
215 printk("KUo ");
216 if (regs->cp0_status & ST0_IEO)
217 printk("IEo ");
218 if (regs->cp0_status & ST0_KUP)
219 printk("KUp ");
220 if (regs->cp0_status & ST0_IEP)
221 printk("IEp ");
222 if (regs->cp0_status & ST0_KUC)
223 printk("KUc ");
224 if (regs->cp0_status & ST0_IEC)
225 printk("IEc ");
226 } else {
227 if (regs->cp0_status & ST0_KX)
228 printk("KX ");
229 if (regs->cp0_status & ST0_SX)
230 printk("SX ");
231 if (regs->cp0_status & ST0_UX)
232 printk("UX ");
233 switch (regs->cp0_status & ST0_KSU) {
234 case KSU_USER:
235 printk("USER ");
236 break;
237 case KSU_SUPERVISOR:
238 printk("SUPERVISOR ");
239 break;
240 case KSU_KERNEL:
241 printk("KERNEL ");
242 break;
243 default:
244 printk("BAD_MODE ");
245 break;
246 }
247 if (regs->cp0_status & ST0_ERL)
248 printk("ERL ");
249 if (regs->cp0_status & ST0_EXL)
250 printk("EXL ");
251 if (regs->cp0_status & ST0_IE)
252 printk("IE ");
1da177e4 253 }
1da177e4
LT		 254 printk("\n");
255
256 printk("Cause : %08x\n", cause);
257
258 cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
259 if (1 <= cause && cause <= 5)
260 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
261
262 printk("PrId : %08x\n", read_c0_prid());
263}
264
265void show_registers(struct pt_regs *regs)
266{
267 show_regs(regs);
268 print_modules();
269 printk("Process %s (pid: %d, threadinfo=%p, task=%p)\n",
270 current->comm, current->pid, current_thread_info(), current);
271 show_stack(current, (long *) regs->regs[29]);
272 show_trace(current, (long *) regs->regs[29]);
273 show_code((unsigned int *) regs->cp0_epc);
274 printk("\n");
275}
276
277static DEFINE_SPINLOCK(die_lock);
278
178086c8 279NORET_TYPE void ATTRIB_NORET die(const char * str, struct pt_regs * regs)
1da177e4
LT		 280{
281 static int die_counter;
282
283 console_verbose();
284 spin_lock_irq(&die_lock);
178086c8 285 printk("%s[#%d]:\n", str, ++die_counter);
1da177e4
LT		 286 show_registers(regs);
287 spin_unlock_irq(&die_lock);
288 do_exit(SIGSEGV);
289}
290
1da177e4
LT		 291extern const struct exception_table_entry __start___dbe_table[];
292extern const struct exception_table_entry __stop___dbe_table[];
293
294void __declare_dbe_table(void)
295{
296 __asm__ __volatile__(
297 ".section\t__dbe_table,\"a\"\n\t"
298 ".previous"
299 );
300}
301
302/* Given an address, look for it in the exception tables. */
303static const struct exception_table_entry *search_dbe_tables(unsigned long addr)
304{
305 const struct exception_table_entry *e;
306
307 e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr);
308 if (!e)
309 e = search_module_dbetables(addr);
310 return e;
311}
312
313asmlinkage void do_be(struct pt_regs *regs)
314{
315 const int field = 2 * sizeof(unsigned long);
316 const struct exception_table_entry *fixup = NULL;
317 int data = regs->cp0_cause & 4;
318 int action = MIPS_BE_FATAL;
319
320 /* XXX For now. Fixme, this searches the wrong table ... */
321 if (data && !user_mode(regs))
322 fixup = search_dbe_tables(exception_epc(regs));
323
324 if (fixup)
325 action = MIPS_BE_FIXUP;
326
327 if (board_be_handler)
328 action = board_be_handler(regs, fixup != 0);
329
330 switch (action) {
331 case MIPS_BE_DISCARD:
332 return;
333 case MIPS_BE_FIXUP:
334 if (fixup) {
335 regs->cp0_epc = fixup->nextinsn;
336 return;
337 }
338 break;
339 default:
340 break;
341 }
342
343 /*
344 * Assume it would be too dangerous to continue ...
345 */
346 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
347 data ? "Data" : "Instruction",
348 field, regs->cp0_epc, field, regs->regs[31]);
349 die_if_kernel("Oops", regs);
350 force_sig(SIGBUS, current);
351}
352
353static inline int get_insn_opcode(struct pt_regs *regs, unsigned int *opcode)
354{
fe00f943 355 unsigned int __user *epc;
1da177e4 356
fe00f943 357 epc = (unsigned int __user *) regs->cp0_epc +
1da177e4
LT		 358 ((regs->cp0_cause & CAUSEF_BD) != 0);
359 if (!get_user(*opcode, epc))
360 return 0;
361
362 force_sig(SIGSEGV, current);
363 return 1;
364}
365
366/*
367 * ll/sc emulation
368 */
369
370#define OPCODE 0xfc000000
371#define BASE 0x03e00000
372#define RT 0x001f0000
373#define OFFSET 0x0000ffff
374#define LL 0xc0000000
375#define SC 0xe0000000
3c37026d
RB		 376#define SPEC3 0x7c000000
377#define RD 0x0000f800
378#define FUNC 0x0000003f
379#define RDHWR 0x0000003b
1da177e4
LT		 380
381/*
382 * The ll_bit is cleared by r*_switch.S
383 */
384
385unsigned long ll_bit;
386
387static struct task_struct *ll_task = NULL;
388
389static inline void simulate_ll(struct pt_regs *regs, unsigned int opcode)
390{
fe00f943 391 unsigned long value, __user *vaddr;
1da177e4
LT		 392 long offset;
393 int signal = 0;
394
395 /*
396 * analyse the ll instruction that just caused a ri exception
397 * and put the referenced address to addr.
398 */
399
400 /* sign extend offset */
401 offset = opcode & OFFSET;
402 offset <<= 16;
403 offset >>= 16;
404
fe00f943
RB		 405 vaddr = (unsigned long __user *)
406 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
1da177e4
LT		 407
408 if ((unsigned long)vaddr & 3) {
409 signal = SIGBUS;
410 goto sig;
411 }
412 if (get_user(value, vaddr)) {
413 signal = SIGSEGV;
414 goto sig;
415 }
416
417 preempt_disable();
418
419 if (ll_task == NULL || ll_task == current) {
420 ll_bit = 1;
421 } else {
422 ll_bit = 0;
423 }
424 ll_task = current;
425
426 preempt_enable();
427
6dd04688
RB		 428 compute_return_epc(regs);
429
1da177e4
LT		 430 regs->regs[(opcode & RT) >> 16] = value;
431
1da177e4
LT		 432 return;
433
434sig:
435 force_sig(signal, current);
436}
437
438static inline void simulate_sc(struct pt_regs *regs, unsigned int opcode)
439{
fe00f943
RB		 440 unsigned long __user *vaddr;
441 unsigned long reg;
1da177e4
LT		 442 long offset;
443 int signal = 0;
444
445 /*
446 * analyse the sc instruction that just caused a ri exception
447 * and put the referenced address to addr.
448 */
449
450 /* sign extend offset */
451 offset = opcode & OFFSET;
452 offset <<= 16;
453 offset >>= 16;
454
fe00f943
RB		 455 vaddr = (unsigned long __user *)
456 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
1da177e4
LT		 457 reg = (opcode & RT) >> 16;
458
459 if ((unsigned long)vaddr & 3) {
460 signal = SIGBUS;
461 goto sig;
462 }
463
464 preempt_disable();
465
466 if (ll_bit == 0 || ll_task != current) {
05b8042a 467 compute_return_epc(regs);
1da177e4
LT		 468 regs->regs[reg] = 0;
469 preempt_enable();
1da177e4
LT		 470 return;
471 }
472
473 preempt_enable();
474
475 if (put_user(regs->regs[reg], vaddr)) {
476 signal = SIGSEGV;
477 goto sig;
478 }
479
6dd04688 480 compute_return_epc(regs);
1da177e4
LT		 481 regs->regs[reg] = 1;
482
1da177e4
LT		 483 return;
484
485sig:
486 force_sig(signal, current);
487}
488
489/*
490 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both
491 * opcodes are supposed to result in coprocessor unusable exceptions if
492 * executed on ll/sc-less processors. That's the theory. In practice a
493 * few processors such as NEC's VR4100 throw reserved instruction exceptions
494 * instead, so we're doing the emulation thing in both exception handlers.
495 */
496static inline int simulate_llsc(struct pt_regs *regs)
497{
498 unsigned int opcode;
499
500 if (unlikely(get_insn_opcode(regs, &opcode)))
501 return -EFAULT;
502
503 if ((opcode & OPCODE) == LL) {
504 simulate_ll(regs, opcode);
505 return 0;
506 }
507 if ((opcode & OPCODE) == SC) {
508 simulate_sc(regs, opcode);
509 return 0;
510 }
511
512 return -EFAULT; /* Strange things going on ... */
513}
514
3c37026d
RB		 515/*
516 * Simulate trapping 'rdhwr' instructions to provide user accessible
517 * registers not implemented in hardware. The only current use of this
518 * is the thread area pointer.
519 */
520static inline int simulate_rdhwr(struct pt_regs *regs)
521{
dc8f6029 522 struct thread_info *ti = task_thread_info(current);
3c37026d
RB		 523 unsigned int opcode;
524
525 if (unlikely(get_insn_opcode(regs, &opcode)))
526 return -EFAULT;
527
528 if (unlikely(compute_return_epc(regs)))
529 return -EFAULT;
530
531 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
532 int rd = (opcode & RD) >> 11;
533 int rt = (opcode & RT) >> 16;
534 switch (rd) {
535 case 29:
536 regs->regs[rt] = ti->tp_value;
56ebd51b 537 return 0;
3c37026d
RB		 538 default:
539 return -EFAULT;
540 }
541 }
542
56ebd51b
DJ		 543 /* Not ours. */
544 return -EFAULT;
3c37026d
RB		 545}
546
1da177e4
LT		 547asmlinkage void do_ov(struct pt_regs *regs)
548{
549 siginfo_t info;
550
36ccf1c0
RB		 551 die_if_kernel("Integer overflow", regs);
552
1da177e4
LT		 553 info.si_code = FPE_INTOVF;
554 info.si_signo = SIGFPE;
555 info.si_errno = 0;
fe00f943 556 info.si_addr = (void __user *) regs->cp0_epc;
1da177e4
LT		 557 force_sig_info(SIGFPE, &info, current);
558}
559
560/*
561 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
562 */
563asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
564{
565 if (fcr31 & FPU_CSR_UNI_X) {
566 int sig;
567
568 preempt_disable();
569
cd21dfcf
RB		 570#ifdef CONFIG_PREEMPT
571 if (!is_fpu_owner()) {
572 /* We might lose fpu before disabling preempt... */
573 own_fpu();
574 BUG_ON(!used_math());
575 restore_fp(current);
576 }
577#endif
1da177e4 578 /*
a3dddd56 579 * Unimplemented operation exception. If we've got the full
1da177e4
LT		 580 * software emulator on-board, let's use it...
581 *
582 * Force FPU to dump state into task/thread context. We're
583 * moving a lot of data here for what is probably a single
584 * instruction, but the alternative is to pre-decode the FP
585 * register operands before invoking the emulator, which seems
586 * a bit extreme for what should be an infrequent event.
587 */
588 save_fp(current);
cd21dfcf
RB		 589 /* Ensure 'resume' not overwrite saved fp context again. */
590 lose_fpu();
591
592 preempt_enable();
1da177e4
LT		 593
594 /* Run the emulator */
12616ed2 595 sig = fpu_emulator_cop1Handler (regs,
1da177e4
LT		 596 &current->thread.fpu.soft);
597
cd21dfcf
RB		 598 preempt_disable();
599
600 own_fpu(); /* Using the FPU again. */
1da177e4
LT		 601 /*
602 * We can't allow the emulated instruction to leave any of
603 * the cause bit set in $fcr31.
604 */
605 current->thread.fpu.soft.fcr31 &= ~FPU_CSR_ALL_X;
606
607 /* Restore the hardware register state */
608 restore_fp(current);
609
610 preempt_enable();
611
612 /* If something went wrong, signal */
613 if (sig)
614 force_sig(sig, current);
615
616 return;
617 }
618
619 force_sig(SIGFPE, current);
620}
621
622asmlinkage void do_bp(struct pt_regs *regs)
623{
624 unsigned int opcode, bcode;
625 siginfo_t info;
626
627 die_if_kernel("Break instruction in kernel code", regs);
628
629 if (get_insn_opcode(regs, &opcode))
630 return;
631
632 /*
633 * There is the ancient bug in the MIPS assemblers that the break
634 * code starts left to bit 16 instead to bit 6 in the opcode.
635 * Gas is bug-compatible, but not always, grrr...
636 * We handle both cases with a simple heuristics. --macro
637 */
638 bcode = ((opcode >> 6) & ((1 << 20) - 1));
639 if (bcode < (1 << 10))
640 bcode <<= 10;
641
642 /*
643 * (A short test says that IRIX 5.3 sends SIGTRAP for all break
644 * insns, even for break codes that indicate arithmetic failures.
645 * Weird ...)
646 * But should we continue the brokenness??? --macro
647 */
648 switch (bcode) {
649 case BRK_OVERFLOW << 10:
650 case BRK_DIVZERO << 10:
651 if (bcode == (BRK_DIVZERO << 10))
652 info.si_code = FPE_INTDIV;
653 else
654 info.si_code = FPE_INTOVF;
655 info.si_signo = SIGFPE;
656 info.si_errno = 0;
fe00f943 657 info.si_addr = (void __user *) regs->cp0_epc;
1da177e4
LT		 658 force_sig_info(SIGFPE, &info, current);
659 break;
660 default:
661 force_sig(SIGTRAP, current);
662 }
663}
664
665asmlinkage void do_tr(struct pt_regs *regs)
666{
667 unsigned int opcode, tcode = 0;
668 siginfo_t info;
669
670 die_if_kernel("Trap instruction in kernel code", regs);
671
672 if (get_insn_opcode(regs, &opcode))
673 return;
674
675 /* Immediate versions don't provide a code. */
676 if (!(opcode & OPCODE))
677 tcode = ((opcode >> 6) & ((1 << 10) - 1));
678
679 /*
680 * (A short test says that IRIX 5.3 sends SIGTRAP for all trap
681 * insns, even for trap codes that indicate arithmetic failures.
682 * Weird ...)
683 * But should we continue the brokenness??? --macro
684 */
685 switch (tcode) {
686 case BRK_OVERFLOW:
687 case BRK_DIVZERO:
688 if (tcode == BRK_DIVZERO)
689 info.si_code = FPE_INTDIV;
690 else
691 info.si_code = FPE_INTOVF;
692 info.si_signo = SIGFPE;
693 info.si_errno = 0;
fe00f943 694 info.si_addr = (void __user *) regs->cp0_epc;
1da177e4
LT		 695 force_sig_info(SIGFPE, &info, current);
696 break;
697 default:
698 force_sig(SIGTRAP, current);
699 }
700}
701
702asmlinkage void do_ri(struct pt_regs *regs)
703{
704 die_if_kernel("Reserved instruction in kernel code", regs);
705
706 if (!cpu_has_llsc)
707 if (!simulate_llsc(regs))
708 return;
709
3c37026d
RB		 710 if (!simulate_rdhwr(regs))
711 return;
712
1da177e4
LT		 713 force_sig(SIGILL, current);
714}
715
716asmlinkage void do_cpu(struct pt_regs *regs)
717{
718 unsigned int cpid;
719
720 die_if_kernel("do_cpu invoked from kernel context!", regs);
721
722 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
723
724 switch (cpid) {
725 case 0:
3c37026d
RB		 726 if (!cpu_has_llsc)
727 if (!simulate_llsc(regs))
728 return;
1da177e4 729
3c37026d 730 if (!simulate_rdhwr(regs))
1da177e4 731 return;
3c37026d 732
1da177e4
LT		 733 break;
734
735 case 1:
736 preempt_disable();
737
738 own_fpu();
739 if (used_math()) { /* Using the FPU again. */
740 restore_fp(current);
741 } else { /* First time FPU user. */
742 init_fpu();
743 set_used_math();
744 }
745
cd21dfcf
RB		 746 preempt_enable();
747
1da177e4 748 if (!cpu_has_fpu) {
12616ed2 749 int sig = fpu_emulator_cop1Handler(regs,
1da177e4
LT		 750 &current->thread.fpu.soft);
751 if (sig)
752 force_sig(sig, current);
753 }
754
1da177e4
LT		 755 return;
756
757 case 2:
758 case 3:
759 break;
760 }
761
762 force_sig(SIGILL, current);
763}
764
765asmlinkage void do_mdmx(struct pt_regs *regs)
766{
767 force_sig(SIGILL, current);
768}
769
770asmlinkage void do_watch(struct pt_regs *regs)
771{
772 /*
773 * We use the watch exception where available to detect stack
774 * overflows.
775 */
776 dump_tlb_all();
777 show_regs(regs);
778 panic("Caught WATCH exception - probably caused by stack overflow.");
779}
780
781asmlinkage void do_mcheck(struct pt_regs *regs)
782{
783 show_regs(regs);
784 dump_tlb_all();
785 /*
786 * Some chips may have other causes of machine check (e.g. SB1
787 * graduation timer)
788 */
789 panic("Caught Machine Check exception - %scaused by multiple "
790 "matching entries in the TLB.",
791 (regs->cp0_status & ST0_TS) ? "" : "not ");
792}
793
340ee4b9
RB		 794asmlinkage void do_mt(struct pt_regs *regs)
795{
796 die_if_kernel("MIPS MT Thread exception in kernel", regs);
797
798 force_sig(SIGILL, current);
799}
800
801
e50c0a8f
RB		 802asmlinkage void do_dsp(struct pt_regs *regs)
803{
804 if (cpu_has_dsp)
805 panic("Unexpected DSP exception\n");
806
807 force_sig(SIGILL, current);
808}
809
1da177e4
LT		 810asmlinkage void do_reserved(struct pt_regs *regs)
811{
812 /*
813 * Game over - no way to handle this if it ever occurs. Most probably
814 * caused by a new unknown cpu type or after another deadly
815 * hard/software error.
816 */
817 show_regs(regs);
818 panic("Caught reserved exception %ld - should not happen.",
819 (regs->cp0_cause & 0x7f) >> 2);
820}
821
e01402b1
RB		 822asmlinkage void do_default_vi(struct pt_regs *regs)
823{
824 show_regs(regs);
825 panic("Caught unexpected vectored interrupt.");
826}
827
1da177e4
LT		 828/*
829 * Some MIPS CPUs can enable/disable for cache parity detection, but do
830 * it different ways.
831 */
832static inline void parity_protection_init(void)
833{
834 switch (current_cpu_data.cputype) {
835 case CPU_24K:
1da177e4 836 case CPU_5KC:
14f18b7f
RB		 837 write_c0_ecc(0x80000000);
838 back_to_back_c0_hazard();
839 /* Set the PE bit (bit 31) in the c0_errctl register. */
840 printk(KERN_INFO "Cache parity protection %sabled\n",
841 (read_c0_ecc() & 0x80000000) ? "en" : "dis");
1da177e4
LT		 842 break;
843 case CPU_20KC:
844 case CPU_25KF:
845 /* Clear the DE bit (bit 16) in the c0_status register. */
846 printk(KERN_INFO "Enable cache parity protection for "
847 "MIPS 20KC/25KF CPUs.\n");
848 clear_c0_status(ST0_DE);
849 break;
850 default:
851 break;
852 }
853}
854
855asmlinkage void cache_parity_error(void)
856{
857 const int field = 2 * sizeof(unsigned long);
858 unsigned int reg_val;
859
860 /* For the moment, report the problem and hang. */
861 printk("Cache error exception:\n");
862 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
863 reg_val = read_c0_cacheerr();
864 printk("c0_cacheerr == %08x\n", reg_val);
865
866 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
867 reg_val & (1<<30) ? "secondary" : "primary",
868 reg_val & (1<<31) ? "data" : "insn");
869 printk("Error bits: %s%s%s%s%s%s%s\n",
870 reg_val & (1<<29) ? "ED " : "",
871 reg_val & (1<<28) ? "ET " : "",
872 reg_val & (1<<26) ? "EE " : "",
873 reg_val & (1<<25) ? "EB " : "",
874 reg_val & (1<<24) ? "EI " : "",
875 reg_val & (1<<23) ? "E1 " : "",
876 reg_val & (1<<22) ? "E0 " : "");
877 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
878
ec917c2c 879#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
1da177e4
LT		 880 if (reg_val & (1<<22))
881 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
882
883 if (reg_val & (1<<23))
884 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());
885#endif
886
887 panic("Can't handle the cache error!");
888}
889
890/*
891 * SDBBP EJTAG debug exception handler.
892 * We skip the instruction and return to the next instruction.
893 */
894void ejtag_exception_handler(struct pt_regs *regs)
895{
896 const int field = 2 * sizeof(unsigned long);
897 unsigned long depc, old_epc;
898 unsigned int debug;
899
900 printk("SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
901 depc = read_c0_depc();
902 debug = read_c0_debug();
903 printk("c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug);
904 if (debug & 0x80000000) {
905 /*
906 * In branch delay slot.
907 * We cheat a little bit here and use EPC to calculate the
908 * debug return address (DEPC). EPC is restored after the
909 * calculation.
910 */
911 old_epc = regs->cp0_epc;
912 regs->cp0_epc = depc;
913 __compute_return_epc(regs);
914 depc = regs->cp0_epc;
915 regs->cp0_epc = old_epc;
916 } else
917 depc += 4;
918 write_c0_depc(depc);
919
920#if 0
921 printk("\n\n----- Enable EJTAG single stepping ----\n\n");
922 write_c0_debug(debug | 0x100);
923#endif
924}
925
926/*
927 * NMI exception handler.
928 */
929void nmi_exception_handler(struct pt_regs *regs)
930{
931 printk("NMI taken!!!!\n");
932 die("NMI", regs);
933 while(1) ;
934}
935
e01402b1
RB		 936#define VECTORSPACING 0x100 /* for EI/VI mode */
937
938unsigned long ebase;
1da177e4 939unsigned long exception_handlers[32];
e01402b1 940unsigned long vi_handlers[64];
1da177e4
LT		 941
942/*
943 * As a side effect of the way this is implemented we're limited
944 * to interrupt handlers in the address range from
945 * KSEG0 <= x < KSEG0 + 256mb on the Nevada. Oh well ...
946 */
947void *set_except_vector(int n, void *addr)
948{
949 unsigned long handler = (unsigned long) addr;
950 unsigned long old_handler = exception_handlers[n];
951
952 exception_handlers[n] = handler;
953 if (n == 0 && cpu_has_divec) {
e01402b1 954 *(volatile u32 *)(ebase + 0x200) = 0x08000000 |
1da177e4 955 (0x03ffffff & (handler >> 2));
e01402b1
RB		 956 flush_icache_range(ebase + 0x200, ebase + 0x204);
957 }
958 return (void *)old_handler;
959}
960
961#ifdef CONFIG_CPU_MIPSR2
962/*
963 * Shadow register allocation
964 * FIXME: SMP...
965 */
966
967/* MIPSR2 shadow register sets */
968struct shadow_registers {
969 spinlock_t sr_lock; /* */
970 int sr_supported; /* Number of shadow register sets supported */
971 int sr_allocated; /* Bitmap of allocated shadow registers */
972} shadow_registers;
973
974void mips_srs_init(void)
975{
976#ifdef CONFIG_CPU_MIPSR2_SRS
977 shadow_registers.sr_supported = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
7acb783e
RB		 978 printk(KERN_INFO "%d MIPSR2 register sets available\n",
979 shadow_registers.sr_supported);
e01402b1
RB		 980#endif
981 shadow_registers.sr_allocated = 1; /* Set 0 used by kernel */
982 spin_lock_init(&shadow_registers.sr_lock);
983}
984
985int mips_srs_max(void)
986{
987 return shadow_registers.sr_supported;
988}
989
990int mips_srs_alloc (void)
991{
992 struct shadow_registers *sr = &shadow_registers;
993 unsigned long flags;
994 int set;
995
996 spin_lock_irqsave(&sr->sr_lock, flags);
997
998 for (set = 0; set < sr->sr_supported; set++) {
999 if ((sr->sr_allocated & (1 << set)) == 0) {
1000 sr->sr_allocated |= 1 << set;
1001 spin_unlock_irqrestore(&sr->sr_lock, flags);
1002 return set;
1003 }
1004 }
1005
1006 /* None available */
1007 spin_unlock_irqrestore(&sr->sr_lock, flags);
1008 return -1;
1009}
1010
1011void mips_srs_free (int set)
1012{
1013 struct shadow_registers *sr = &shadow_registers;
1014 unsigned long flags;
1015
1016 spin_lock_irqsave(&sr->sr_lock, flags);
1017 sr->sr_allocated &= ~(1 << set);
1018 spin_unlock_irqrestore(&sr->sr_lock, flags);
1019}
1020
b4d05cb9 1021static void *set_vi_srs_handler(int n, void *addr, int srs)
e01402b1
RB		 1022{
1023 unsigned long handler;
1024 unsigned long old_handler = vi_handlers[n];
1025 u32 *w;
1026 unsigned char *b;
1027
1028 if (!cpu_has_veic && !cpu_has_vint)
1029 BUG();
1030
1031 if (addr == NULL) {
1032 handler = (unsigned long) do_default_vi;
1033 srs = 0;
1034 }
1035 else
1036 handler = (unsigned long) addr;
1037 vi_handlers[n] = (unsigned long) addr;
1038
1039 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
1040
1041 if (srs >= mips_srs_max())
1042 panic("Shadow register set %d not supported", srs);
1043
1044 if (cpu_has_veic) {
1045 if (board_bind_eic_interrupt)
1046 board_bind_eic_interrupt (n, srs);
1047 }
1048 else if (cpu_has_vint) {
1049 /* SRSMap is only defined if shadow sets are implemented */
1050 if (mips_srs_max() > 1)
1051 change_c0_srsmap (0xf << n*4, srs << n*4);
1052 }
1053
1054 if (srs == 0) {
1055 /*
1056 * If no shadow set is selected then use the default handler
1057 * that does normal register saving and a standard interrupt exit
1058 */
1059
1060 extern char except_vec_vi, except_vec_vi_lui;
1061 extern char except_vec_vi_ori, except_vec_vi_end;
1062 const int handler_len = &except_vec_vi_end - &except_vec_vi;
1063 const int lui_offset = &except_vec_vi_lui - &except_vec_vi;
1064 const int ori_offset = &except_vec_vi_ori - &except_vec_vi;
1065
1066 if (handler_len > VECTORSPACING) {
1067 /*
1068 * Sigh... panicing won't help as the console
1069 * is probably not configured :(
1070 */
1071 panic ("VECTORSPACING too small");
1072 }
1073
1074 memcpy (b, &except_vec_vi, handler_len);
1075 w = (u32 *)(b + lui_offset);
1076 *w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff);
1077 w = (u32 *)(b + ori_offset);
1078 *w = (*w & 0xffff0000) | ((u32)handler & 0xffff);
1079 flush_icache_range((unsigned long)b, (unsigned long)(b+handler_len));
1080 }
1081 else {
1082 /*
1083 * In other cases jump directly to the interrupt handler
1084 *
1085 * It is the handlers responsibility to save registers if required
1086 * (eg hi/lo) and return from the exception using "eret"
1087 */
1088 w = (u32 *)b;
1089 *w++ = 0x08000000 | (((u32)handler >> 2) & 0x03fffff); /* j handler */
1090 *w = 0;
1091 flush_icache_range((unsigned long)b, (unsigned long)(b+8));
1da177e4 1092 }
e01402b1 1093
1da177e4
LT		 1094 return (void *)old_handler;
1095}
1096
e01402b1
RB		 1097void *set_vi_handler (int n, void *addr)
1098{
1099 return set_vi_srs_handler (n, addr, 0);
1100}
1101#endif
1102
1da177e4
LT		 1103/*
1104 * This is used by native signal handling
1105 */
1106asmlinkage int (*save_fp_context)(struct sigcontext *sc);
1107asmlinkage int (*restore_fp_context)(struct sigcontext *sc);
1108
1109extern asmlinkage int _save_fp_context(struct sigcontext *sc);
1110extern asmlinkage int _restore_fp_context(struct sigcontext *sc);
1111
1112extern asmlinkage int fpu_emulator_save_context(struct sigcontext *sc);
1113extern asmlinkage int fpu_emulator_restore_context(struct sigcontext *sc);
1114
1115static inline void signal_init(void)
1116{
1117 if (cpu_has_fpu) {
1118 save_fp_context = _save_fp_context;
1119 restore_fp_context = _restore_fp_context;
1120 } else {
1121 save_fp_context = fpu_emulator_save_context;
1122 restore_fp_context = fpu_emulator_restore_context;
1123 }
1124}
1125
1126#ifdef CONFIG_MIPS32_COMPAT
1127
1128/*
1129 * This is used by 32-bit signal stuff on the 64-bit kernel
1130 */
1131asmlinkage int (*save_fp_context32)(struct sigcontext32 *sc);
1132asmlinkage int (*restore_fp_context32)(struct sigcontext32 *sc);
1133
1134extern asmlinkage int _save_fp_context32(struct sigcontext32 *sc);
1135extern asmlinkage int _restore_fp_context32(struct sigcontext32 *sc);
1136
1137extern asmlinkage int fpu_emulator_save_context32(struct sigcontext32 *sc);
1138extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 *sc);
1139
1140static inline void signal32_init(void)
1141{
1142 if (cpu_has_fpu) {
1143 save_fp_context32 = _save_fp_context32;
1144 restore_fp_context32 = _restore_fp_context32;
1145 } else {
1146 save_fp_context32 = fpu_emulator_save_context32;
1147 restore_fp_context32 = fpu_emulator_restore_context32;
1148 }
1149}
1150#endif
1151
1152extern void cpu_cache_init(void);
1153extern void tlb_init(void);
1d40cfcd 1154extern void flush_tlb_handlers(void);
1da177e4
LT		 1155
1156void __init per_cpu_trap_init(void)
1157{
1158 unsigned int cpu = smp_processor_id();
1159 unsigned int status_set = ST0_CU0;
1160
1161 /*
1162 * Disable coprocessors and select 32-bit or 64-bit addressing
1163 * and the 16/32 or 32/32 FPR register model. Reset the BEV
1164 * flag that some firmware may have left set and the TS bit (for
1165 * IP27). Set XX for ISA IV code to work.
1166 */
875d43e7 1167#ifdef CONFIG_64BIT
1da177e4
LT		 1168 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
1169#endif
1170 if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV)
1171 status_set |= ST0_XX;
b38c7399 1172 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
1da177e4
LT		 1173 status_set);
1174
e50c0a8f
RB		 1175 if (cpu_has_dsp)
1176 set_c0_status(ST0_MX);
1177
e01402b1
RB		 1178#ifdef CONFIG_CPU_MIPSR2
1179 write_c0_hwrena (0x0000000f); /* Allow rdhwr to all registers */
1180#endif
1181
1da177e4 1182 /*
e01402b1 1183 * Interrupt handling.
1da177e4 1184 */
e01402b1
RB		 1185 if (cpu_has_veic || cpu_has_vint) {
1186 write_c0_ebase (ebase);
1187 /* Setting vector spacing enables EI/VI mode */
1188 change_c0_intctl (0x3e0, VECTORSPACING);
1189 }
d03d0a57
RB		 1190 if (cpu_has_divec) {
1191 if (cpu_has_mipsmt) {
1192 unsigned int vpflags = dvpe();
1193 set_c0_cause(CAUSEF_IV);
1194 evpe(vpflags);
1195 } else
1196 set_c0_cause(CAUSEF_IV);
1197 }
1da177e4
LT		 1198
1199 cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
1200 TLBMISS_HANDLER_SETUP();
1201
1202 atomic_inc(&init_mm.mm_count);
1203 current->active_mm = &init_mm;
1204 BUG_ON(current->mm);
1205 enter_lazy_tlb(&init_mm, current);
1206
1207 cpu_cache_init();
1208 tlb_init();
1209}
1210
e01402b1
RB		 1211/* Install CPU exception handler */
1212void __init set_handler (unsigned long offset, void *addr, unsigned long size)
1213{
1214 memcpy((void *)(ebase + offset), addr, size);
1215 flush_icache_range(ebase + offset, ebase + offset + size);
1216}
1217
1218/* Install uncached CPU exception handler */
1219void __init set_uncached_handler (unsigned long offset, void *addr, unsigned long size)
1220{
1221#ifdef CONFIG_32BIT
1222 unsigned long uncached_ebase = KSEG1ADDR(ebase);
1223#endif
1224#ifdef CONFIG_64BIT
1225 unsigned long uncached_ebase = TO_UNCAC(ebase);
1226#endif
1227
1228 memcpy((void *)(uncached_ebase + offset), addr, size);
1229}
1230
1da177e4
LT		 1231void __init trap_init(void)
1232{
1233 extern char except_vec3_generic, except_vec3_r4000;
1da177e4
LT		 1234 extern char except_vec4;
1235 unsigned long i;
1236
e01402b1
RB		 1237 if (cpu_has_veic || cpu_has_vint)
1238 ebase = (unsigned long) alloc_bootmem_low_pages (0x200 + VECTORSPACING*64);
1239 else
1240 ebase = CAC_BASE;
1241
1242#ifdef CONFIG_CPU_MIPSR2
1243 mips_srs_init();
1244#endif
1245
1da177e4
LT		 1246 per_cpu_trap_init();
1247
1248 /*
1249 * Copy the generic exception handlers to their final destination.
1250 * This will be overriden later as suitable for a particular
1251 * configuration.
1252 */
e01402b1 1253 set_handler(0x180, &except_vec3_generic, 0x80);
1da177e4
LT		 1254
1255 /*
1256 * Setup default vectors
1257 */
1258 for (i = 0; i <= 31; i++)
1259 set_except_vector(i, handle_reserved);
1260
1261 /*
1262 * Copy the EJTAG debug exception vector handler code to it's final
1263 * destination.
1264 */
e01402b1
RB		 1265 if (cpu_has_ejtag && board_ejtag_handler_setup)
1266 board_ejtag_handler_setup ();
1da177e4
LT		 1267
1268 /*
1269 * Only some CPUs have the watch exceptions.
1270 */
1271 if (cpu_has_watch)
1272 set_except_vector(23, handle_watch);
1273
1274 /*
e01402b1 1275 * Initialise interrupt handlers
1da177e4 1276 */
e01402b1
RB		 1277 if (cpu_has_veic || cpu_has_vint) {
1278 int nvec = cpu_has_veic ? 64 : 8;
1279 for (i = 0; i < nvec; i++)
1280 set_vi_handler (i, NULL);
1281 }
1282 else if (cpu_has_divec)
1283 set_handler(0x200, &except_vec4, 0x8);
1da177e4
LT		 1284
1285 /*
1286 * Some CPUs can enable/disable for cache parity detection, but does
1287 * it different ways.
1288 */
1289 parity_protection_init();
1290
1291 /*
1292 * The Data Bus Errors / Instruction Bus Errors are signaled
1293 * by external hardware. Therefore these two exceptions
1294 * may have board specific handlers.
1295 */
1296 if (board_be_init)
1297 board_be_init();
1298
1299 set_except_vector(1, handle_tlbm);
1300 set_except_vector(2, handle_tlbl);
1301 set_except_vector(3, handle_tlbs);
1302
1303 set_except_vector(4, handle_adel);
1304 set_except_vector(5, handle_ades);
1305
1306 set_except_vector(6, handle_ibe);
1307 set_except_vector(7, handle_dbe);
1308
1309 set_except_vector(8, handle_sys);
1310 set_except_vector(9, handle_bp);
1311 set_except_vector(10, handle_ri);
1312 set_except_vector(11, handle_cpu);
1313 set_except_vector(12, handle_ov);
1314 set_except_vector(13, handle_tr);
1da177e4
LT		 1315
1316 if (current_cpu_data.cputype == CPU_R6000 ||
1317 current_cpu_data.cputype == CPU_R6000A) {
1318 /*
1319 * The R6000 is the only R-series CPU that features a machine
1320 * check exception (similar to the R4000 cache error) and
1321 * unaligned ldc1/sdc1 exception. The handlers have not been
1322 * written yet. Well, anyway there is no R6000 machine on the
1323 * current list of targets for Linux/MIPS.
1324 * (Duh, crap, there is someone with a triple R6k machine)
1325 */
1326 //set_except_vector(14, handle_mc);
1327 //set_except_vector(15, handle_ndc);
1328 }
1329
e01402b1
RB		 1330
1331 if (board_nmi_handler_setup)
1332 board_nmi_handler_setup();
1333
e50c0a8f
RB		 1334 if (cpu_has_fpu && !cpu_has_nofpuex)
1335 set_except_vector(15, handle_fpe);
1336
1337 set_except_vector(22, handle_mdmx);
1338
1339 if (cpu_has_mcheck)
1340 set_except_vector(24, handle_mcheck);
1341
340ee4b9
RB		 1342 if (cpu_has_mipsmt)
1343 set_except_vector(25, handle_mt);
1344
e50c0a8f
RB		 1345 if (cpu_has_dsp)
1346 set_except_vector(26, handle_dsp);
1347
1348 if (cpu_has_vce)
1349 /* Special exception: R4[04]00 uses also the divec space. */
1350 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_r4000, 0x100);
1351 else if (cpu_has_4kex)
1352 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80);
1353 else
1354 memcpy((void *)(CAC_BASE + 0x080), &except_vec3_generic, 0x80);
1355
1da177e4
LT		 1356 signal_init();
1357#ifdef CONFIG_MIPS32_COMPAT
1358 signal32_init();
1359#endif
1360
e01402b1 1361 flush_icache_range(ebase, ebase + 0x400);
1d40cfcd 1362 flush_tlb_handlers();
1da177e4 1363}
kernel source for telekom puls (alcatel/mediatek)