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[MIPS] kpsd and other AP/SP improvements.
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / mips / kernel / traps.c
CommitLineData
1da177e4
LT		 1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
36ccf1c0 6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
1da177e4
LT		 7 * Copyright (C) 1995, 1996 Paul M. Antoine
8 * Copyright (C) 1998 Ulf Carlsson
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
11 * Copyright (C) 2000, 01 MIPS Technologies, Inc.
3b2396d9 12 * Copyright (C) 2002, 2003, 2004, 2005 Maciej W. Rozycki
1da177e4
LT		 13 */
14#include <linux/config.h>
15#include <linux/init.h>
16#include <linux/mm.h>
17#include <linux/module.h>
18#include <linux/sched.h>
19#include <linux/smp.h>
20#include <linux/smp_lock.h>
21#include <linux/spinlock.h>
22#include <linux/kallsyms.h>
e01402b1 23#include <linux/bootmem.h>
1da177e4
LT		 24
25#include <asm/bootinfo.h>
26#include <asm/branch.h>
27#include <asm/break.h>
28#include <asm/cpu.h>
e50c0a8f 29#include <asm/dsp.h>
1da177e4 30#include <asm/fpu.h>
340ee4b9
RB		 31#include <asm/mipsregs.h>
32#include <asm/mipsmtregs.h>
1da177e4
LT		 33#include <asm/module.h>
34#include <asm/pgtable.h>
35#include <asm/ptrace.h>
36#include <asm/sections.h>
37#include <asm/system.h>
38#include <asm/tlbdebug.h>
39#include <asm/traps.h>
40#include <asm/uaccess.h>
41#include <asm/mmu_context.h>
42#include <asm/watch.h>
43#include <asm/types.h>
44
e4ac58af 45extern asmlinkage void handle_int(void);
1da177e4
LT		 46extern asmlinkage void handle_tlbm(void);
47extern asmlinkage void handle_tlbl(void);
48extern asmlinkage void handle_tlbs(void);
49extern asmlinkage void handle_adel(void);
50extern asmlinkage void handle_ades(void);
51extern asmlinkage void handle_ibe(void);
52extern asmlinkage void handle_dbe(void);
53extern asmlinkage void handle_sys(void);
54extern asmlinkage void handle_bp(void);
55extern asmlinkage void handle_ri(void);
56extern asmlinkage void handle_cpu(void);
57extern asmlinkage void handle_ov(void);
58extern asmlinkage void handle_tr(void);
59extern asmlinkage void handle_fpe(void);
60extern asmlinkage void handle_mdmx(void);
61extern asmlinkage void handle_watch(void);
340ee4b9 62extern asmlinkage void handle_mt(void);
e50c0a8f 63extern asmlinkage void handle_dsp(void);
1da177e4
LT		 64extern asmlinkage void handle_mcheck(void);
65extern asmlinkage void handle_reserved(void);
66
12616ed2 67extern int fpu_emulator_cop1Handler(struct pt_regs *xcp,
1da177e4
LT		 68 struct mips_fpu_soft_struct *ctx);
69
70void (*board_be_init)(void);
71int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
e01402b1
RB		 72void (*board_nmi_handler_setup)(void);
73void (*board_ejtag_handler_setup)(void);
74void (*board_bind_eic_interrupt)(int irq, int regset);
1da177e4
LT		 75
76/*
77 * These constant is for searching for possible module text segments.
78 * MODULE_RANGE is a guess of how much space is likely to be vmalloced.
79 */
80#define MODULE_RANGE (8*1024*1024)
81
82/*
83 * This routine abuses get_user()/put_user() to reference pointers
84 * with at least a bit of error checking ...
85 */
86void show_stack(struct task_struct *task, unsigned long *sp)
87{
88 const int field = 2 * sizeof(unsigned long);
89 long stackdata;
90 int i;
91
92 if (!sp) {
93 if (task && task != current)
94 sp = (unsigned long *) task->thread.reg29;
95 else
96 sp = (unsigned long *) &sp;
97 }
98
99 printk("Stack :");
100 i = 0;
101 while ((unsigned long) sp & (PAGE_SIZE - 1)) {
102 if (i && ((i % (64 / field)) == 0))
103 printk("\n ");
104 if (i > 39) {
105 printk(" ...");
106 break;
107 }
108
109 if (__get_user(stackdata, sp++)) {
110 printk(" (Bad stack address)");
111 break;
112 }
113
114 printk(" %0*lx", field, stackdata);
115 i++;
116 }
117 printk("\n");
118}
119
120void show_trace(struct task_struct *task, unsigned long *stack)
121{
122 const int field = 2 * sizeof(unsigned long);
123 unsigned long addr;
124
125 if (!stack) {
126 if (task && task != current)
127 stack = (unsigned long *) task->thread.reg29;
128 else
129 stack = (unsigned long *) &stack;
130 }
131
132 printk("Call Trace:");
133#ifdef CONFIG_KALLSYMS
134 printk("\n");
135#endif
136 while (!kstack_end(stack)) {
137 addr = *stack++;
138 if (__kernel_text_address(addr)) {
139 printk(" [<%0*lx>] ", field, addr);
140 print_symbol("%s\n", addr);
141 }
142 }
143 printk("\n");
144}
145
146/*
147 * The architecture-independent dump_stack generator
148 */
149void dump_stack(void)
150{
151 unsigned long stack;
152
153 show_trace(current, &stack);
154}
155
156EXPORT_SYMBOL(dump_stack);
157
158void show_code(unsigned int *pc)
159{
160 long i;
161
162 printk("\nCode:");
163
164 for(i = -3 ; i < 6 ; i++) {
165 unsigned int insn;
166 if (__get_user(insn, pc + i)) {
167 printk(" (Bad address in epc)\n");
168 break;
169 }
170 printk("%c%08x%c", (i?' ':'<'), insn, (i?' ':'>'));
171 }
172}
173
174void show_regs(struct pt_regs *regs)
175{
176 const int field = 2 * sizeof(unsigned long);
177 unsigned int cause = regs->cp0_cause;
178 int i;
179
180 printk("Cpu %d\n", smp_processor_id());
181
182 /*
183 * Saved main processor registers
184 */
185 for (i = 0; i < 32; ) {
186 if ((i % 4) == 0)
187 printk("$%2d :", i);
188 if (i == 0)
189 printk(" %0*lx", field, 0UL);
190 else if (i == 26 || i == 27)
191 printk(" %*s", field, "");
192 else
193 printk(" %0*lx", field, regs->regs[i]);
194
195 i++;
196 if ((i % 4) == 0)
197 printk("\n");
198 }
199
200 printk("Hi : %0*lx\n", field, regs->hi);
201 printk("Lo : %0*lx\n", field, regs->lo);
202
203 /*
204 * Saved cp0 registers
205 */
206 printk("epc : %0*lx ", field, regs->cp0_epc);
207 print_symbol("%s ", regs->cp0_epc);
208 printk(" %s\n", print_tainted());
209 printk("ra : %0*lx ", field, regs->regs[31]);
210 print_symbol("%s\n", regs->regs[31]);
211
212 printk("Status: %08x ", (uint32_t) regs->cp0_status);
213
3b2396d9
MR		 214 if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) {
215 if (regs->cp0_status & ST0_KUO)
216 printk("KUo ");
217 if (regs->cp0_status & ST0_IEO)
218 printk("IEo ");
219 if (regs->cp0_status & ST0_KUP)
220 printk("KUp ");
221 if (regs->cp0_status & ST0_IEP)
222 printk("IEp ");
223 if (regs->cp0_status & ST0_KUC)
224 printk("KUc ");
225 if (regs->cp0_status & ST0_IEC)
226 printk("IEc ");
227 } else {
228 if (regs->cp0_status & ST0_KX)
229 printk("KX ");
230 if (regs->cp0_status & ST0_SX)
231 printk("SX ");
232 if (regs->cp0_status & ST0_UX)
233 printk("UX ");
234 switch (regs->cp0_status & ST0_KSU) {
235 case KSU_USER:
236 printk("USER ");
237 break;
238 case KSU_SUPERVISOR:
239 printk("SUPERVISOR ");
240 break;
241 case KSU_KERNEL:
242 printk("KERNEL ");
243 break;
244 default:
245 printk("BAD_MODE ");
246 break;
247 }
248 if (regs->cp0_status & ST0_ERL)
249 printk("ERL ");
250 if (regs->cp0_status & ST0_EXL)
251 printk("EXL ");
252 if (regs->cp0_status & ST0_IE)
253 printk("IE ");
1da177e4 254 }
1da177e4
LT		 255 printk("\n");
256
257 printk("Cause : %08x\n", cause);
258
259 cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
260 if (1 <= cause && cause <= 5)
261 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
262
263 printk("PrId : %08x\n", read_c0_prid());
264}
265
266void show_registers(struct pt_regs *regs)
267{
268 show_regs(regs);
269 print_modules();
270 printk("Process %s (pid: %d, threadinfo=%p, task=%p)\n",
271 current->comm, current->pid, current_thread_info(), current);
272 show_stack(current, (long *) regs->regs[29]);
273 show_trace(current, (long *) regs->regs[29]);
274 show_code((unsigned int *) regs->cp0_epc);
275 printk("\n");
276}
277
278static DEFINE_SPINLOCK(die_lock);
279
178086c8 280NORET_TYPE void ATTRIB_NORET die(const char * str, struct pt_regs * regs)
1da177e4
LT		 281{
282 static int die_counter;
283
284 console_verbose();
285 spin_lock_irq(&die_lock);
178086c8 286 printk("%s[#%d]:\n", str, ++die_counter);
1da177e4
LT		 287 show_registers(regs);
288 spin_unlock_irq(&die_lock);
289 do_exit(SIGSEGV);
290}
291
1da177e4
LT		 292extern const struct exception_table_entry __start___dbe_table[];
293extern const struct exception_table_entry __stop___dbe_table[];
294
295void __declare_dbe_table(void)
296{
297 __asm__ __volatile__(
298 ".section\t__dbe_table,\"a\"\n\t"
299 ".previous"
300 );
301}
302
303/* Given an address, look for it in the exception tables. */
304static const struct exception_table_entry *search_dbe_tables(unsigned long addr)
305{
306 const struct exception_table_entry *e;
307
308 e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr);
309 if (!e)
310 e = search_module_dbetables(addr);
311 return e;
312}
313
314asmlinkage void do_be(struct pt_regs *regs)
315{
316 const int field = 2 * sizeof(unsigned long);
317 const struct exception_table_entry *fixup = NULL;
318 int data = regs->cp0_cause & 4;
319 int action = MIPS_BE_FATAL;
320
321 /* XXX For now. Fixme, this searches the wrong table ... */
322 if (data && !user_mode(regs))
323 fixup = search_dbe_tables(exception_epc(regs));
324
325 if (fixup)
326 action = MIPS_BE_FIXUP;
327
328 if (board_be_handler)
329 action = board_be_handler(regs, fixup != 0);
330
331 switch (action) {
332 case MIPS_BE_DISCARD:
333 return;
334 case MIPS_BE_FIXUP:
335 if (fixup) {
336 regs->cp0_epc = fixup->nextinsn;
337 return;
338 }
339 break;
340 default:
341 break;
342 }
343
344 /*
345 * Assume it would be too dangerous to continue ...
346 */
347 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
348 data ? "Data" : "Instruction",
349 field, regs->cp0_epc, field, regs->regs[31]);
350 die_if_kernel("Oops", regs);
351 force_sig(SIGBUS, current);
352}
353
354static inline int get_insn_opcode(struct pt_regs *regs, unsigned int *opcode)
355{
fe00f943 356 unsigned int __user *epc;
1da177e4 357
fe00f943 358 epc = (unsigned int __user *) regs->cp0_epc +
1da177e4
LT		 359 ((regs->cp0_cause & CAUSEF_BD) != 0);
360 if (!get_user(*opcode, epc))
361 return 0;
362
363 force_sig(SIGSEGV, current);
364 return 1;
365}
366
367/*
368 * ll/sc emulation
369 */
370
371#define OPCODE 0xfc000000
372#define BASE 0x03e00000
373#define RT 0x001f0000
374#define OFFSET 0x0000ffff
375#define LL 0xc0000000
376#define SC 0xe0000000
3c37026d
RB		 377#define SPEC3 0x7c000000
378#define RD 0x0000f800
379#define FUNC 0x0000003f
380#define RDHWR 0x0000003b
1da177e4
LT		 381
382/*
383 * The ll_bit is cleared by r*_switch.S
384 */
385
386unsigned long ll_bit;
387
388static struct task_struct *ll_task = NULL;
389
390static inline void simulate_ll(struct pt_regs *regs, unsigned int opcode)
391{
fe00f943 392 unsigned long value, __user *vaddr;
1da177e4
LT		 393 long offset;
394 int signal = 0;
395
396 /*
397 * analyse the ll instruction that just caused a ri exception
398 * and put the referenced address to addr.
399 */
400
401 /* sign extend offset */
402 offset = opcode & OFFSET;
403 offset <<= 16;
404 offset >>= 16;
405
fe00f943
RB		 406 vaddr = (unsigned long __user *)
407 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
1da177e4
LT		 408
409 if ((unsigned long)vaddr & 3) {
410 signal = SIGBUS;
411 goto sig;
412 }
413 if (get_user(value, vaddr)) {
414 signal = SIGSEGV;
415 goto sig;
416 }
417
418 preempt_disable();
419
420 if (ll_task == NULL || ll_task == current) {
421 ll_bit = 1;
422 } else {
423 ll_bit = 0;
424 }
425 ll_task = current;
426
427 preempt_enable();
428
6dd04688
RB		 429 compute_return_epc(regs);
430
1da177e4
LT		 431 regs->regs[(opcode & RT) >> 16] = value;
432
1da177e4
LT		 433 return;
434
435sig:
436 force_sig(signal, current);
437}
438
439static inline void simulate_sc(struct pt_regs *regs, unsigned int opcode)
440{
fe00f943
RB		 441 unsigned long __user *vaddr;
442 unsigned long reg;
1da177e4
LT		 443 long offset;
444 int signal = 0;
445
446 /*
447 * analyse the sc instruction that just caused a ri exception
448 * and put the referenced address to addr.
449 */
450
451 /* sign extend offset */
452 offset = opcode & OFFSET;
453 offset <<= 16;
454 offset >>= 16;
455
fe00f943
RB		 456 vaddr = (unsigned long __user *)
457 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
1da177e4
LT		 458 reg = (opcode & RT) >> 16;
459
460 if ((unsigned long)vaddr & 3) {
461 signal = SIGBUS;
462 goto sig;
463 }
464
465 preempt_disable();
466
467 if (ll_bit == 0 || ll_task != current) {
05b8042a 468 compute_return_epc(regs);
1da177e4
LT		 469 regs->regs[reg] = 0;
470 preempt_enable();
1da177e4
LT		 471 return;
472 }
473
474 preempt_enable();
475
476 if (put_user(regs->regs[reg], vaddr)) {
477 signal = SIGSEGV;
478 goto sig;
479 }
480
6dd04688 481 compute_return_epc(regs);
1da177e4
LT		 482 regs->regs[reg] = 1;
483
1da177e4
LT		 484 return;
485
486sig:
487 force_sig(signal, current);
488}
489
490/*
491 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both
492 * opcodes are supposed to result in coprocessor unusable exceptions if
493 * executed on ll/sc-less processors. That's the theory. In practice a
494 * few processors such as NEC's VR4100 throw reserved instruction exceptions
495 * instead, so we're doing the emulation thing in both exception handlers.
496 */
497static inline int simulate_llsc(struct pt_regs *regs)
498{
499 unsigned int opcode;
500
501 if (unlikely(get_insn_opcode(regs, &opcode)))
502 return -EFAULT;
503
504 if ((opcode & OPCODE) == LL) {
505 simulate_ll(regs, opcode);
506 return 0;
507 }
508 if ((opcode & OPCODE) == SC) {
509 simulate_sc(regs, opcode);
510 return 0;
511 }
512
513 return -EFAULT; /* Strange things going on ... */
514}
515
3c37026d
RB		 516/*
517 * Simulate trapping 'rdhwr' instructions to provide user accessible
518 * registers not implemented in hardware. The only current use of this
519 * is the thread area pointer.
520 */
521static inline int simulate_rdhwr(struct pt_regs *regs)
522{
dc8f6029 523 struct thread_info *ti = task_thread_info(current);
3c37026d
RB		 524 unsigned int opcode;
525
526 if (unlikely(get_insn_opcode(regs, &opcode)))
527 return -EFAULT;
528
529 if (unlikely(compute_return_epc(regs)))
530 return -EFAULT;
531
532 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
533 int rd = (opcode & RD) >> 11;
534 int rt = (opcode & RT) >> 16;
535 switch (rd) {
536 case 29:
537 regs->regs[rt] = ti->tp_value;
56ebd51b 538 return 0;
3c37026d
RB		 539 default:
540 return -EFAULT;
541 }
542 }
543
56ebd51b
DJ		 544 /* Not ours. */
545 return -EFAULT;
3c37026d
RB		 546}
547
1da177e4
LT		 548asmlinkage void do_ov(struct pt_regs *regs)
549{
550 siginfo_t info;
551
36ccf1c0
RB		 552 die_if_kernel("Integer overflow", regs);
553
1da177e4
LT		 554 info.si_code = FPE_INTOVF;
555 info.si_signo = SIGFPE;
556 info.si_errno = 0;
fe00f943 557 info.si_addr = (void __user *) regs->cp0_epc;
1da177e4
LT		 558 force_sig_info(SIGFPE, &info, current);
559}
560
561/*
562 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
563 */
564asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
565{
566 if (fcr31 & FPU_CSR_UNI_X) {
567 int sig;
568
569 preempt_disable();
570
cd21dfcf
RB		 571#ifdef CONFIG_PREEMPT
572 if (!is_fpu_owner()) {
573 /* We might lose fpu before disabling preempt... */
574 own_fpu();
575 BUG_ON(!used_math());
576 restore_fp(current);
577 }
578#endif
1da177e4 579 /*
a3dddd56 580 * Unimplemented operation exception. If we've got the full
1da177e4
LT		 581 * software emulator on-board, let's use it...
582 *
583 * Force FPU to dump state into task/thread context. We're
584 * moving a lot of data here for what is probably a single
585 * instruction, but the alternative is to pre-decode the FP
586 * register operands before invoking the emulator, which seems
587 * a bit extreme for what should be an infrequent event.
588 */
589 save_fp(current);
cd21dfcf
RB		 590 /* Ensure 'resume' not overwrite saved fp context again. */
591 lose_fpu();
592
593 preempt_enable();
1da177e4
LT		 594
595 /* Run the emulator */
12616ed2 596 sig = fpu_emulator_cop1Handler (regs,
1da177e4
LT		 597 &current->thread.fpu.soft);
598
cd21dfcf
RB		 599 preempt_disable();
600
601 own_fpu(); /* Using the FPU again. */
1da177e4
LT		 602 /*
603 * We can't allow the emulated instruction to leave any of
604 * the cause bit set in $fcr31.
605 */
606 current->thread.fpu.soft.fcr31 &= ~FPU_CSR_ALL_X;
607
608 /* Restore the hardware register state */
609 restore_fp(current);
610
611 preempt_enable();
612
613 /* If something went wrong, signal */
614 if (sig)
615 force_sig(sig, current);
616
617 return;
618 }
619
620 force_sig(SIGFPE, current);
621}
622
623asmlinkage void do_bp(struct pt_regs *regs)
624{
625 unsigned int opcode, bcode;
626 siginfo_t info;
627
628 die_if_kernel("Break instruction in kernel code", regs);
629
630 if (get_insn_opcode(regs, &opcode))
631 return;
632
633 /*
634 * There is the ancient bug in the MIPS assemblers that the break
635 * code starts left to bit 16 instead to bit 6 in the opcode.
636 * Gas is bug-compatible, but not always, grrr...
637 * We handle both cases with a simple heuristics. --macro
638 */
639 bcode = ((opcode >> 6) & ((1 << 20) - 1));
640 if (bcode < (1 << 10))
641 bcode <<= 10;
642
643 /*
644 * (A short test says that IRIX 5.3 sends SIGTRAP for all break
645 * insns, even for break codes that indicate arithmetic failures.
646 * Weird ...)
647 * But should we continue the brokenness??? --macro
648 */
649 switch (bcode) {
650 case BRK_OVERFLOW << 10:
651 case BRK_DIVZERO << 10:
652 if (bcode == (BRK_DIVZERO << 10))
653 info.si_code = FPE_INTDIV;
654 else
655 info.si_code = FPE_INTOVF;
656 info.si_signo = SIGFPE;
657 info.si_errno = 0;
fe00f943 658 info.si_addr = (void __user *) regs->cp0_epc;
1da177e4
LT		 659 force_sig_info(SIGFPE, &info, current);
660 break;
661 default:
662 force_sig(SIGTRAP, current);
663 }
664}
665
666asmlinkage void do_tr(struct pt_regs *regs)
667{
668 unsigned int opcode, tcode = 0;
669 siginfo_t info;
670
671 die_if_kernel("Trap instruction in kernel code", regs);
672
673 if (get_insn_opcode(regs, &opcode))
674 return;
675
676 /* Immediate versions don't provide a code. */
677 if (!(opcode & OPCODE))
678 tcode = ((opcode >> 6) & ((1 << 10) - 1));
679
680 /*
681 * (A short test says that IRIX 5.3 sends SIGTRAP for all trap
682 * insns, even for trap codes that indicate arithmetic failures.
683 * Weird ...)
684 * But should we continue the brokenness??? --macro
685 */
686 switch (tcode) {
687 case BRK_OVERFLOW:
688 case BRK_DIVZERO:
689 if (tcode == BRK_DIVZERO)
690 info.si_code = FPE_INTDIV;
691 else
692 info.si_code = FPE_INTOVF;
693 info.si_signo = SIGFPE;
694 info.si_errno = 0;
fe00f943 695 info.si_addr = (void __user *) regs->cp0_epc;
1da177e4
LT		 696 force_sig_info(SIGFPE, &info, current);
697 break;
698 default:
699 force_sig(SIGTRAP, current);
700 }
701}
702
703asmlinkage void do_ri(struct pt_regs *regs)
704{
705 die_if_kernel("Reserved instruction in kernel code", regs);
706
707 if (!cpu_has_llsc)
708 if (!simulate_llsc(regs))
709 return;
710
3c37026d
RB		 711 if (!simulate_rdhwr(regs))
712 return;
713
1da177e4
LT		 714 force_sig(SIGILL, current);
715}
716
717asmlinkage void do_cpu(struct pt_regs *regs)
718{
719 unsigned int cpid;
720
721 die_if_kernel("do_cpu invoked from kernel context!", regs);
722
723 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
724
725 switch (cpid) {
726 case 0:
3c37026d
RB		 727 if (!cpu_has_llsc)
728 if (!simulate_llsc(regs))
729 return;
1da177e4 730
3c37026d 731 if (!simulate_rdhwr(regs))
1da177e4 732 return;
3c37026d 733
1da177e4
LT		 734 break;
735
736 case 1:
737 preempt_disable();
738
739 own_fpu();
740 if (used_math()) { /* Using the FPU again. */
741 restore_fp(current);
742 } else { /* First time FPU user. */
743 init_fpu();
744 set_used_math();
745 }
746
cd21dfcf
RB		 747 preempt_enable();
748
1da177e4 749 if (!cpu_has_fpu) {
12616ed2 750 int sig = fpu_emulator_cop1Handler(regs,
1da177e4
LT		 751 &current->thread.fpu.soft);
752 if (sig)
753 force_sig(sig, current);
754 }
755
1da177e4
LT		 756 return;
757
758 case 2:
759 case 3:
760 break;
761 }
762
763 force_sig(SIGILL, current);
764}
765
766asmlinkage void do_mdmx(struct pt_regs *regs)
767{
768 force_sig(SIGILL, current);
769}
770
771asmlinkage void do_watch(struct pt_regs *regs)
772{
773 /*
774 * We use the watch exception where available to detect stack
775 * overflows.
776 */
777 dump_tlb_all();
778 show_regs(regs);
779 panic("Caught WATCH exception - probably caused by stack overflow.");
780}
781
782asmlinkage void do_mcheck(struct pt_regs *regs)
783{
784 show_regs(regs);
785 dump_tlb_all();
786 /*
787 * Some chips may have other causes of machine check (e.g. SB1
788 * graduation timer)
789 */
790 panic("Caught Machine Check exception - %scaused by multiple "
791 "matching entries in the TLB.",
792 (regs->cp0_status & ST0_TS) ? "" : "not ");
793}
794
340ee4b9
RB		 795asmlinkage void do_mt(struct pt_regs *regs)
796{
797 die_if_kernel("MIPS MT Thread exception in kernel", regs);
798
799 force_sig(SIGILL, current);
800}
801
802
e50c0a8f
RB		 803asmlinkage void do_dsp(struct pt_regs *regs)
804{
805 if (cpu_has_dsp)
806 panic("Unexpected DSP exception\n");
807
808 force_sig(SIGILL, current);
809}
810
1da177e4
LT		 811asmlinkage void do_reserved(struct pt_regs *regs)
812{
813 /*
814 * Game over - no way to handle this if it ever occurs. Most probably
815 * caused by a new unknown cpu type or after another deadly
816 * hard/software error.
817 */
818 show_regs(regs);
819 panic("Caught reserved exception %ld - should not happen.",
820 (regs->cp0_cause & 0x7f) >> 2);
821}
822
e01402b1
RB		 823asmlinkage void do_default_vi(struct pt_regs *regs)
824{
825 show_regs(regs);
826 panic("Caught unexpected vectored interrupt.");
827}
828
1da177e4
LT		 829/*
830 * Some MIPS CPUs can enable/disable for cache parity detection, but do
831 * it different ways.
832 */
833static inline void parity_protection_init(void)
834{
835 switch (current_cpu_data.cputype) {
836 case CPU_24K:
1da177e4 837 case CPU_5KC:
14f18b7f
RB		 838 write_c0_ecc(0x80000000);
839 back_to_back_c0_hazard();
840 /* Set the PE bit (bit 31) in the c0_errctl register. */
841 printk(KERN_INFO "Cache parity protection %sabled\n",
842 (read_c0_ecc() & 0x80000000) ? "en" : "dis");
1da177e4
LT		 843 break;
844 case CPU_20KC:
845 case CPU_25KF:
846 /* Clear the DE bit (bit 16) in the c0_status register. */
847 printk(KERN_INFO "Enable cache parity protection for "
848 "MIPS 20KC/25KF CPUs.\n");
849 clear_c0_status(ST0_DE);
850 break;
851 default:
852 break;
853 }
854}
855
856asmlinkage void cache_parity_error(void)
857{
858 const int field = 2 * sizeof(unsigned long);
859 unsigned int reg_val;
860
861 /* For the moment, report the problem and hang. */
862 printk("Cache error exception:\n");
863 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
864 reg_val = read_c0_cacheerr();
865 printk("c0_cacheerr == %08x\n", reg_val);
866
867 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
868 reg_val & (1<<30) ? "secondary" : "primary",
869 reg_val & (1<<31) ? "data" : "insn");
870 printk("Error bits: %s%s%s%s%s%s%s\n",
871 reg_val & (1<<29) ? "ED " : "",
872 reg_val & (1<<28) ? "ET " : "",
873 reg_val & (1<<26) ? "EE " : "",
874 reg_val & (1<<25) ? "EB " : "",
875 reg_val & (1<<24) ? "EI " : "",
876 reg_val & (1<<23) ? "E1 " : "",
877 reg_val & (1<<22) ? "E0 " : "");
878 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
879
ec917c2c 880#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
1da177e4
LT		 881 if (reg_val & (1<<22))
882 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
883
884 if (reg_val & (1<<23))
885 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());
886#endif
887
888 panic("Can't handle the cache error!");
889}
890
891/*
892 * SDBBP EJTAG debug exception handler.
893 * We skip the instruction and return to the next instruction.
894 */
895void ejtag_exception_handler(struct pt_regs *regs)
896{
897 const int field = 2 * sizeof(unsigned long);
898 unsigned long depc, old_epc;
899 unsigned int debug;
900
901 printk("SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
902 depc = read_c0_depc();
903 debug = read_c0_debug();
904 printk("c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug);
905 if (debug & 0x80000000) {
906 /*
907 * In branch delay slot.
908 * We cheat a little bit here and use EPC to calculate the
909 * debug return address (DEPC). EPC is restored after the
910 * calculation.
911 */
912 old_epc = regs->cp0_epc;
913 regs->cp0_epc = depc;
914 __compute_return_epc(regs);
915 depc = regs->cp0_epc;
916 regs->cp0_epc = old_epc;
917 } else
918 depc += 4;
919 write_c0_depc(depc);
920
921#if 0
922 printk("\n\n----- Enable EJTAG single stepping ----\n\n");
923 write_c0_debug(debug | 0x100);
924#endif
925}
926
927/*
928 * NMI exception handler.
929 */
930void nmi_exception_handler(struct pt_regs *regs)
931{
932 printk("NMI taken!!!!\n");
933 die("NMI", regs);
934 while(1) ;
935}
936
e01402b1
RB		 937#define VECTORSPACING 0x100 /* for EI/VI mode */
938
939unsigned long ebase;
1da177e4 940unsigned long exception_handlers[32];
e01402b1 941unsigned long vi_handlers[64];
1da177e4
LT		 942
943/*
944 * As a side effect of the way this is implemented we're limited
945 * to interrupt handlers in the address range from
946 * KSEG0 <= x < KSEG0 + 256mb on the Nevada. Oh well ...
947 */
948void *set_except_vector(int n, void *addr)
949{
950 unsigned long handler = (unsigned long) addr;
951 unsigned long old_handler = exception_handlers[n];
952
953 exception_handlers[n] = handler;
954 if (n == 0 && cpu_has_divec) {
e01402b1 955 *(volatile u32 *)(ebase + 0x200) = 0x08000000 |
1da177e4 956 (0x03ffffff & (handler >> 2));
e01402b1
RB		 957 flush_icache_range(ebase + 0x200, ebase + 0x204);
958 }
959 return (void *)old_handler;
960}
961
962#ifdef CONFIG_CPU_MIPSR2
963/*
193dd2ce 964 * MIPSR2 shadow register set allocation
e01402b1
RB		 965 * FIXME: SMP...
966 */
967
193dd2ce
RB		 968static struct shadow_registers {
969 /*
970 * Number of shadow register sets supported
971 */
972 unsigned long sr_supported;
973 /*
974 * Bitmap of allocated shadow registers
975 */
976 unsigned long sr_allocated;
e01402b1
RB		 977} shadow_registers;
978
979void mips_srs_init(void)
980{
981#ifdef CONFIG_CPU_MIPSR2_SRS
982 shadow_registers.sr_supported = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
7acb783e
RB		 983 printk(KERN_INFO "%d MIPSR2 register sets available\n",
984 shadow_registers.sr_supported);
e01402b1
RB		 985#endif
986 shadow_registers.sr_allocated = 1; /* Set 0 used by kernel */
e01402b1
RB		 987}
988
989int mips_srs_max(void)
990{
991 return shadow_registers.sr_supported;
992}
993
ff3eab2a 994int mips_srs_alloc(void)
e01402b1
RB		 995{
996 struct shadow_registers *sr = &shadow_registers;
e01402b1
RB		 997 int set;
998
193dd2ce
RB		 999again:
1000 set = find_first_zero_bit(&sr->sr_allocated, sr->sr_supported);
1001 if (set >= sr->sr_supported)
1002 return -1;
e01402b1 1003
193dd2ce
RB		 1004 if (test_and_set_bit(set, &sr->sr_allocated))
1005 goto again;
e01402b1 1006
193dd2ce 1007 return set;
e01402b1
RB		 1008}
1009
1010void mips_srs_free (int set)
1011{
1012 struct shadow_registers *sr = &shadow_registers;
e01402b1 1013
193dd2ce 1014 clear_bit(set, &sr->sr_allocated);
e01402b1
RB		 1015}
1016
b4d05cb9 1017static void *set_vi_srs_handler(int n, void *addr, int srs)
e01402b1
RB		 1018{
1019 unsigned long handler;
1020 unsigned long old_handler = vi_handlers[n];
1021 u32 *w;
1022 unsigned char *b;
1023
1024 if (!cpu_has_veic && !cpu_has_vint)
1025 BUG();
1026
1027 if (addr == NULL) {
1028 handler = (unsigned long) do_default_vi;
1029 srs = 0;
1030 }
1031 else
1032 handler = (unsigned long) addr;
1033 vi_handlers[n] = (unsigned long) addr;
1034
1035 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
1036
1037 if (srs >= mips_srs_max())
1038 panic("Shadow register set %d not supported", srs);
1039
1040 if (cpu_has_veic) {
1041 if (board_bind_eic_interrupt)
1042 board_bind_eic_interrupt (n, srs);
1043 }
1044 else if (cpu_has_vint) {
1045 /* SRSMap is only defined if shadow sets are implemented */
1046 if (mips_srs_max() > 1)
1047 change_c0_srsmap (0xf << n*4, srs << n*4);
1048 }
1049
1050 if (srs == 0) {
1051 /*
1052 * If no shadow set is selected then use the default handler
1053 * that does normal register saving and a standard interrupt exit
1054 */
1055
1056 extern char except_vec_vi, except_vec_vi_lui;
1057 extern char except_vec_vi_ori, except_vec_vi_end;
1058 const int handler_len = &except_vec_vi_end - &except_vec_vi;
1059 const int lui_offset = &except_vec_vi_lui - &except_vec_vi;
1060 const int ori_offset = &except_vec_vi_ori - &except_vec_vi;
1061
1062 if (handler_len > VECTORSPACING) {
1063 /*
1064 * Sigh... panicing won't help as the console
1065 * is probably not configured :(
1066 */
1067 panic ("VECTORSPACING too small");
1068 }
1069
1070 memcpy (b, &except_vec_vi, handler_len);
1071 w = (u32 *)(b + lui_offset);
1072 *w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff);
1073 w = (u32 *)(b + ori_offset);
1074 *w = (*w & 0xffff0000) | ((u32)handler & 0xffff);
1075 flush_icache_range((unsigned long)b, (unsigned long)(b+handler_len));
1076 }
1077 else {
1078 /*
1079 * In other cases jump directly to the interrupt handler
1080 *
1081 * It is the handlers responsibility to save registers if required
1082 * (eg hi/lo) and return from the exception using "eret"
1083 */
1084 w = (u32 *)b;
1085 *w++ = 0x08000000 | (((u32)handler >> 2) & 0x03fffff); /* j handler */
1086 *w = 0;
1087 flush_icache_range((unsigned long)b, (unsigned long)(b+8));
1da177e4 1088 }
e01402b1 1089
1da177e4
LT		 1090 return (void *)old_handler;
1091}
1092
e01402b1
RB		 1093void *set_vi_handler (int n, void *addr)
1094{
ff3eab2a 1095 return set_vi_srs_handler(n, addr, 0);
e01402b1
RB		 1096}
1097#endif
1098
1da177e4
LT		 1099/*
1100 * This is used by native signal handling
1101 */
1102asmlinkage int (*save_fp_context)(struct sigcontext *sc);
1103asmlinkage int (*restore_fp_context)(struct sigcontext *sc);
1104
1105extern asmlinkage int _save_fp_context(struct sigcontext *sc);
1106extern asmlinkage int _restore_fp_context(struct sigcontext *sc);
1107
1108extern asmlinkage int fpu_emulator_save_context(struct sigcontext *sc);
1109extern asmlinkage int fpu_emulator_restore_context(struct sigcontext *sc);
1110
1111static inline void signal_init(void)
1112{
1113 if (cpu_has_fpu) {
1114 save_fp_context = _save_fp_context;
1115 restore_fp_context = _restore_fp_context;
1116 } else {
1117 save_fp_context = fpu_emulator_save_context;
1118 restore_fp_context = fpu_emulator_restore_context;
1119 }
1120}
1121
1122#ifdef CONFIG_MIPS32_COMPAT
1123
1124/*
1125 * This is used by 32-bit signal stuff on the 64-bit kernel
1126 */
1127asmlinkage int (*save_fp_context32)(struct sigcontext32 *sc);
1128asmlinkage int (*restore_fp_context32)(struct sigcontext32 *sc);
1129
1130extern asmlinkage int _save_fp_context32(struct sigcontext32 *sc);
1131extern asmlinkage int _restore_fp_context32(struct sigcontext32 *sc);
1132
1133extern asmlinkage int fpu_emulator_save_context32(struct sigcontext32 *sc);
1134extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 *sc);
1135
1136static inline void signal32_init(void)
1137{
1138 if (cpu_has_fpu) {
1139 save_fp_context32 = _save_fp_context32;
1140 restore_fp_context32 = _restore_fp_context32;
1141 } else {
1142 save_fp_context32 = fpu_emulator_save_context32;
1143 restore_fp_context32 = fpu_emulator_restore_context32;
1144 }
1145}
1146#endif
1147
1148extern void cpu_cache_init(void);
1149extern void tlb_init(void);
1d40cfcd 1150extern void flush_tlb_handlers(void);
1da177e4
LT		 1151
1152void __init per_cpu_trap_init(void)
1153{
1154 unsigned int cpu = smp_processor_id();
1155 unsigned int status_set = ST0_CU0;
1156
1157 /*
1158 * Disable coprocessors and select 32-bit or 64-bit addressing
1159 * and the 16/32 or 32/32 FPR register model. Reset the BEV
1160 * flag that some firmware may have left set and the TS bit (for
1161 * IP27). Set XX for ISA IV code to work.
1162 */
875d43e7 1163#ifdef CONFIG_64BIT
1da177e4
LT		 1164 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
1165#endif
1166 if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV)
1167 status_set |= ST0_XX;
b38c7399 1168 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
1da177e4
LT		 1169 status_set);
1170
e50c0a8f
RB		 1171 if (cpu_has_dsp)
1172 set_c0_status(ST0_MX);
1173
e01402b1
RB		 1174#ifdef CONFIG_CPU_MIPSR2
1175 write_c0_hwrena (0x0000000f); /* Allow rdhwr to all registers */
1176#endif
1177
1da177e4 1178 /*
e01402b1 1179 * Interrupt handling.
1da177e4 1180 */
e01402b1
RB		 1181 if (cpu_has_veic || cpu_has_vint) {
1182 write_c0_ebase (ebase);
1183 /* Setting vector spacing enables EI/VI mode */
1184 change_c0_intctl (0x3e0, VECTORSPACING);
1185 }
d03d0a57
RB		 1186 if (cpu_has_divec) {
1187 if (cpu_has_mipsmt) {
1188 unsigned int vpflags = dvpe();
1189 set_c0_cause(CAUSEF_IV);
1190 evpe(vpflags);
1191 } else
1192 set_c0_cause(CAUSEF_IV);
1193 }
1da177e4
LT		 1194
1195 cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
1196 TLBMISS_HANDLER_SETUP();
1197
1198 atomic_inc(&init_mm.mm_count);
1199 current->active_mm = &init_mm;
1200 BUG_ON(current->mm);
1201 enter_lazy_tlb(&init_mm, current);
1202
1203 cpu_cache_init();
1204 tlb_init();
1205}
1206
e01402b1
RB		 1207/* Install CPU exception handler */
1208void __init set_handler (unsigned long offset, void *addr, unsigned long size)
1209{
1210 memcpy((void *)(ebase + offset), addr, size);
1211 flush_icache_range(ebase + offset, ebase + offset + size);
1212}
1213
1214/* Install uncached CPU exception handler */
1215void __init set_uncached_handler (unsigned long offset, void *addr, unsigned long size)
1216{
1217#ifdef CONFIG_32BIT
1218 unsigned long uncached_ebase = KSEG1ADDR(ebase);
1219#endif
1220#ifdef CONFIG_64BIT
1221 unsigned long uncached_ebase = TO_UNCAC(ebase);
1222#endif
1223
1224 memcpy((void *)(uncached_ebase + offset), addr, size);
1225}
1226
1da177e4
LT		 1227void __init trap_init(void)
1228{
1229 extern char except_vec3_generic, except_vec3_r4000;
1da177e4
LT		 1230 extern char except_vec4;
1231 unsigned long i;
1232
e01402b1
RB		 1233 if (cpu_has_veic || cpu_has_vint)
1234 ebase = (unsigned long) alloc_bootmem_low_pages (0x200 + VECTORSPACING*64);
1235 else
1236 ebase = CAC_BASE;
1237
1238#ifdef CONFIG_CPU_MIPSR2
1239 mips_srs_init();
1240#endif
1241
1da177e4
LT		 1242 per_cpu_trap_init();
1243
1244 /*
1245 * Copy the generic exception handlers to their final destination.
1246 * This will be overriden later as suitable for a particular
1247 * configuration.
1248 */
e01402b1 1249 set_handler(0x180, &except_vec3_generic, 0x80);
1da177e4
LT		 1250
1251 /*
1252 * Setup default vectors
1253 */
1254 for (i = 0; i <= 31; i++)
1255 set_except_vector(i, handle_reserved);
1256
1257 /*
1258 * Copy the EJTAG debug exception vector handler code to it's final
1259 * destination.
1260 */
e01402b1
RB		 1261 if (cpu_has_ejtag && board_ejtag_handler_setup)
1262 board_ejtag_handler_setup ();
1da177e4
LT		 1263
1264 /*
1265 * Only some CPUs have the watch exceptions.
1266 */
1267 if (cpu_has_watch)
1268 set_except_vector(23, handle_watch);
1269
1270 /*
e01402b1 1271 * Initialise interrupt handlers
1da177e4 1272 */
e01402b1
RB		 1273 if (cpu_has_veic || cpu_has_vint) {
1274 int nvec = cpu_has_veic ? 64 : 8;
1275 for (i = 0; i < nvec; i++)
ff3eab2a 1276 set_vi_handler(i, NULL);
e01402b1
RB		 1277 }
1278 else if (cpu_has_divec)
1279 set_handler(0x200, &except_vec4, 0x8);
1da177e4
LT		 1280
1281 /*
1282 * Some CPUs can enable/disable for cache parity detection, but does
1283 * it different ways.
1284 */
1285 parity_protection_init();
1286
1287 /*
1288 * The Data Bus Errors / Instruction Bus Errors are signaled
1289 * by external hardware. Therefore these two exceptions
1290 * may have board specific handlers.
1291 */
1292 if (board_be_init)
1293 board_be_init();
1294
e4ac58af 1295 set_except_vector(0, handle_int);
1da177e4
LT		 1296 set_except_vector(1, handle_tlbm);
1297 set_except_vector(2, handle_tlbl);
1298 set_except_vector(3, handle_tlbs);
1299
1300 set_except_vector(4, handle_adel);
1301 set_except_vector(5, handle_ades);
1302
1303 set_except_vector(6, handle_ibe);
1304 set_except_vector(7, handle_dbe);
1305
1306 set_except_vector(8, handle_sys);
1307 set_except_vector(9, handle_bp);
1308 set_except_vector(10, handle_ri);
1309 set_except_vector(11, handle_cpu);
1310 set_except_vector(12, handle_ov);
1311 set_except_vector(13, handle_tr);
1da177e4
LT		 1312
1313 if (current_cpu_data.cputype == CPU_R6000 ||
1314 current_cpu_data.cputype == CPU_R6000A) {
1315 /*
1316 * The R6000 is the only R-series CPU that features a machine
1317 * check exception (similar to the R4000 cache error) and
1318 * unaligned ldc1/sdc1 exception. The handlers have not been
1319 * written yet. Well, anyway there is no R6000 machine on the
1320 * current list of targets for Linux/MIPS.
1321 * (Duh, crap, there is someone with a triple R6k machine)
1322 */
1323 //set_except_vector(14, handle_mc);
1324 //set_except_vector(15, handle_ndc);
1325 }
1326
e01402b1
RB		 1327
1328 if (board_nmi_handler_setup)
1329 board_nmi_handler_setup();
1330
e50c0a8f
RB		 1331 if (cpu_has_fpu && !cpu_has_nofpuex)
1332 set_except_vector(15, handle_fpe);
1333
1334 set_except_vector(22, handle_mdmx);
1335
1336 if (cpu_has_mcheck)
1337 set_except_vector(24, handle_mcheck);
1338
340ee4b9
RB		 1339 if (cpu_has_mipsmt)
1340 set_except_vector(25, handle_mt);
1341
e50c0a8f
RB		 1342 if (cpu_has_dsp)
1343 set_except_vector(26, handle_dsp);
1344
1345 if (cpu_has_vce)
1346 /* Special exception: R4[04]00 uses also the divec space. */
1347 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_r4000, 0x100);
1348 else if (cpu_has_4kex)
1349 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80);
1350 else
1351 memcpy((void *)(CAC_BASE + 0x080), &except_vec3_generic, 0x80);
1352
1da177e4
LT		 1353 signal_init();
1354#ifdef CONFIG_MIPS32_COMPAT
1355 signal32_init();
1356#endif
1357
e01402b1 1358 flush_icache_range(ebase, ebase + 0x400);
1d40cfcd 1359 flush_tlb_handlers();
1da177e4 1360}
kernel source for telekom puls (alcatel/mediatek)