[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / mips / kernel / proc.c

/*
 *  linux/arch/mips/kernel/proc.c
 *
 *  Copyright (C) 1995, 1996, 2001  Ralf Baechle
 *  Copyright (C) 2001, 2004  MIPS Technologies, Inc.
 *  Copyright (C) 2004  Maciej W. Rozycki
 */
#include <linux/config.h>
#include <linux/delay.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/seq_file.h>
#include <asm/bootinfo.h>
#include <asm/cpu.h>
#include <asm/cpu-features.h>
#include <asm/mipsregs.h>
#include <asm/processor.h>
#include <asm/watch.h>

unsigned int vced_count, vcei_count;

static const char *cpu_name[] = {
	[CPU_UNKNOWN]	= "unknown",
	[CPU_R2000]	= "R2000",
	[CPU_R3000]	= "R3000",
	[CPU_R3000A]	= "R3000A",
	[CPU_R3041]	= "R3041",
	[CPU_R3051]	= "R3051",
	[CPU_R3052]	= "R3052",
	[CPU_R3081]	= "R3081",
	[CPU_R3081E]	= "R3081E",
	[CPU_R4000PC]	= "R4000PC",
	[CPU_R4000SC]	= "R4000SC",
	[CPU_R4000MC]	= "R4000MC",
        [CPU_R4200]	= "R4200",
	[CPU_R4400PC]	= "R4400PC",
	[CPU_R4400SC]	= "R4400SC",
	[CPU_R4400MC]	= "R4400MC",
	[CPU_R4600]	= "R4600",
	[CPU_R6000]	= "R6000",
        [CPU_R6000A]	= "R6000A",
	[CPU_R8000]	= "R8000",
	[CPU_R10000]	= "R10000",
	[CPU_R12000]	= "R12000",
	[CPU_R4300]	= "R4300",
	[CPU_R4650]	= "R4650",
	[CPU_R4700]	= "R4700",
	[CPU_R5000]	= "R5000",
        [CPU_R5000A]	= "R5000A",
	[CPU_R4640]	= "R4640",
	[CPU_NEVADA]	= "Nevada",
	[CPU_RM7000]	= "RM7000",
	[CPU_RM9000]	= "RM9000",
	[CPU_R5432]	= "R5432",
	[CPU_4KC]	= "MIPS 4Kc",
        [CPU_5KC]	= "MIPS 5Kc",
	[CPU_R4310]	= "R4310",
	[CPU_SB1]	= "SiByte SB1",
	[CPU_TX3912]	= "TX3912",
	[CPU_TX3922]	= "TX3922",
	[CPU_TX3927]	= "TX3927",
	[CPU_AU1000]	= "Au1000",
	[CPU_AU1500]	= "Au1500",
	[CPU_AU1100]	= "Au1100",
	[CPU_AU1550]	= "Au1550",
	[CPU_AU1200]	= "Au1200",
	[CPU_4KEC]	= "MIPS 4KEc",
	[CPU_4KSC]	= "MIPS 4KSc",
	[CPU_VR41XX]	= "NEC Vr41xx",
	[CPU_R5500]	= "R5500",
	[CPU_TX49XX]	= "TX49xx",
	[CPU_20KC]	= "MIPS 20Kc",
	[CPU_24K]	= "MIPS 24K",
	[CPU_25KF]	= "MIPS 25Kf",
	[CPU_34K]	= "MIPS 34K",
	[CPU_VR4111]	= "NEC VR4111",
	[CPU_VR4121]	= "NEC VR4121",
	[CPU_VR4122]	= "NEC VR4122",
	[CPU_VR4131]	= "NEC VR4131",
	[CPU_VR4133]	= "NEC VR4133",
	[CPU_VR4181]	= "NEC VR4181",
	[CPU_VR4181A]	= "NEC VR4181A",
	[CPU_SR71000]	= "Sandcraft SR71000"
};


static int show_cpuinfo(struct seq_file *m, void *v)
{
	unsigned int version = current_cpu_data.processor_id;
	unsigned int fp_vers = current_cpu_data.fpu_id;
	unsigned long n = (unsigned long) v - 1;
	char fmt [64];

#ifdef CONFIG_SMP
	if (!cpu_isset(n, cpu_online_map))
		return 0;
#endif

	/*
	 * For the first processor also print the system type
	 */
	if (n == 0)
		seq_printf(m, "system type\t\t: %s\n", get_system_type());

	seq_printf(m, "processor\t\t: %ld\n", n);
	sprintf(fmt, "cpu model\t\t: %%s V%%d.%%d%s\n",
	        cpu_has_fpu ? "  FPU V%d.%d" : "");
	seq_printf(m, fmt, cpu_name[current_cpu_data.cputype <= CPU_LAST ?
	                            current_cpu_data.cputype : CPU_UNKNOWN],
	                           (version >> 4) & 0x0f, version & 0x0f,
	                           (fp_vers >> 4) & 0x0f, fp_vers & 0x0f);
	seq_printf(m, "BogoMIPS\t\t: %lu.%02lu\n",
	              cpu_data[n].udelay_val / (500000/HZ),
	              (cpu_data[n].udelay_val / (5000/HZ)) % 100);
	seq_printf(m, "wait instruction\t: %s\n", cpu_wait ? "yes" : "no");
	seq_printf(m, "microsecond timers\t: %s\n",
	              cpu_has_counter ? "yes" : "no");
	seq_printf(m, "tlb_entries\t\t: %d\n", current_cpu_data.tlbsize);
	seq_printf(m, "extra interrupt vector\t: %s\n",
	              cpu_has_divec ? "yes" : "no");
	seq_printf(m, "hardware watchpoint\t: %s\n",
	              cpu_has_watch ? "yes" : "no");
	seq_printf(m, "ASEs implemented\t:%s%s%s%s\n",
		      cpu_has_mips16 ? " mips16" : "",
		      cpu_has_mdmx ? " mdmx" : "",
		      cpu_has_mips3d ? " mips3d" : "",
		      cpu_has_smartmips ? " smartmips" : "");

	sprintf(fmt, "VCE%%c exceptions\t\t: %s\n",
	        cpu_has_vce ? "%u" : "not available");
	seq_printf(m, fmt, 'D', vced_count);
	seq_printf(m, fmt, 'I', vcei_count);

	return 0;
}

static void *c_start(struct seq_file *m, loff_t *pos)
{
	unsigned long i = *pos;

	return i < NR_CPUS ? (void *) (i + 1) : NULL;
}

static void *c_next(struct seq_file *m, void *v, loff_t *pos)
{
	++*pos;
	return c_start(m, pos);
}

static void c_stop(struct seq_file *m, void *v)
{
}

struct seq_operations cpuinfo_op = {
	.start	= c_start,
	.next	= c_next,
	.stop	= c_stop,
	.show	= show_cpuinfo,
};
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/mips/kernel/proc.c
	3	*
	4	* Copyright (C) 1995, 1996, 2001 Ralf Baechle
4194318c RB	5	* Copyright (C) 2001, 2004 MIPS Technologies, Inc.
4194318c RB	6	* Copyright (C) 2004 Maciej W. Rozycki
1da177e4 LT	7	*/
	8	#include <linux/config.h>
	9	#include <linux/delay.h>
	10	#include <linux/kernel.h>
	11	#include <linux/sched.h>
	12	#include <linux/seq_file.h>
	13	#include <asm/bootinfo.h>
	14	#include <asm/cpu.h>
	15	#include <asm/cpu-features.h>
	16	#include <asm/mipsregs.h>
	17	#include <asm/processor.h>
	18	#include <asm/watch.h>
	19
	20	unsigned int vced_count, vcei_count;
	21
	22	static const char *cpu_name[] = {
0f04afb5 RB	23	[CPU_UNKNOWN] = "unknown",
	24	[CPU_R2000] = "R2000",
	25	[CPU_R3000] = "R3000",
	26	[CPU_R3000A] = "R3000A",
	27	[CPU_R3041] = "R3041",
	28	[CPU_R3051] = "R3051",
	29	[CPU_R3052] = "R3052",
	30	[CPU_R3081] = "R3081",
	31	[CPU_R3081E] = "R3081E",
	32	[CPU_R4000PC] = "R4000PC",
	33	[CPU_R4000SC] = "R4000SC",
	34	[CPU_R4000MC] = "R4000MC",
	35	[CPU_R4200] = "R4200",
	36	[CPU_R4400PC] = "R4400PC",
	37	[CPU_R4400SC] = "R4400SC",
	38	[CPU_R4400MC] = "R4400MC",
	39	[CPU_R4600] = "R4600",
	40	[CPU_R6000] = "R6000",
	41	[CPU_R6000A] = "R6000A",
	42	[CPU_R8000] = "R8000",
	43	[CPU_R10000] = "R10000",
	44	[CPU_R12000] = "R12000",
	45	[CPU_R4300] = "R4300",
	46	[CPU_R4650] = "R4650",
	47	[CPU_R4700] = "R4700",
	48	[CPU_R5000] = "R5000",
	49	[CPU_R5000A] = "R5000A",
	50	[CPU_R4640] = "R4640",
	51	[CPU_NEVADA] = "Nevada",
	52	[CPU_RM7000] = "RM7000",
	53	[CPU_RM9000] = "RM9000",
	54	[CPU_R5432] = "R5432",
	55	[CPU_4KC] = "MIPS 4Kc",
	56	[CPU_5KC] = "MIPS 5Kc",
	57	[CPU_R4310] = "R4310",
	58	[CPU_SB1] = "SiByte SB1",
	59	[CPU_TX3912] = "TX3912",
	60	[CPU_TX3922] = "TX3922",
	61	[CPU_TX3927] = "TX3927",
	62	[CPU_AU1000] = "Au1000",
	63	[CPU_AU1500] = "Au1500",
	64	[CPU_AU1100] = "Au1100",
	65	[CPU_AU1550] = "Au1550",
	66	[CPU_AU1200] = "Au1200",
	67	[CPU_4KEC] = "MIPS 4KEc",
	68	[CPU_4KSC] = "MIPS 4KSc",
	69	[CPU_VR41XX] = "NEC Vr41xx",
	70	[CPU_R5500] = "R5500",
	71	[CPU_TX49XX] = "TX49xx",
	72	[CPU_20KC] = "MIPS 20Kc",
	73	[CPU_24K] = "MIPS 24K",
	74	[CPU_25KF] = "MIPS 25Kf",
bbc7f22f	75	[CPU_34K] = "MIPS 34K",
0f04afb5 RB	76	[CPU_VR4111] = "NEC VR4111",
	77	[CPU_VR4121] = "NEC VR4121",
	78	[CPU_VR4122] = "NEC VR4122",
	79	[CPU_VR4131] = "NEC VR4131",
	80	[CPU_VR4133] = "NEC VR4133",
	81	[CPU_VR4181] = "NEC VR4181",
	82	[CPU_VR4181A] = "NEC VR4181A",
	83	[CPU_SR71000] = "Sandcraft SR71000"
1da177e4 LT	84	};
	85
	86
	87	static int show_cpuinfo(struct seq_file m, void v)
	88	{
	89	unsigned int version = current_cpu_data.processor_id;
	90	unsigned int fp_vers = current_cpu_data.fpu_id;
	91	unsigned long n = (unsigned long) v - 1;
	92	char fmt [64];
	93
	94	#ifdef CONFIG_SMP
	95	if (!cpu_isset(n, cpu_online_map))
	96	return 0;
	97	#endif
	98
	99	/*
	100	* For the first processor also print the system type
	101	*/
	102	if (n == 0)
	103	seq_printf(m, "system type\t\t: %s\n", get_system_type());
	104
	105	seq_printf(m, "processor\t\t: %ld\n", n);
	106	sprintf(fmt, "cpu model\t\t: %%s V%%d.%%d%s\n",
	107	cpu_has_fpu ? " FPU V%d.%d" : "");
	108	seq_printf(m, fmt, cpu_name[current_cpu_data.cputype <= CPU_LAST ?
	109	current_cpu_data.cputype : CPU_UNKNOWN],
	110	(version >> 4) & 0x0f, version & 0x0f,
	111	(fp_vers >> 4) & 0x0f, fp_vers & 0x0f);
	112	seq_printf(m, "BogoMIPS\t\t: %lu.%02lu\n",
0ac35480 RB	113	cpu_data[n].udelay_val / (500000/HZ),
0ac35480 RB	114	(cpu_data[n].udelay_val / (5000/HZ)) % 100);
1da177e4 LT	115	seq_printf(m, "wait instruction\t: %s\n", cpu_wait ? "yes" : "no");
	116	seq_printf(m, "microsecond timers\t: %s\n",
	117	cpu_has_counter ? "yes" : "no");
	118	seq_printf(m, "tlb_entries\t\t: %d\n", current_cpu_data.tlbsize);
	119	seq_printf(m, "extra interrupt vector\t: %s\n",
	120	cpu_has_divec ? "yes" : "no");
	121	seq_printf(m, "hardware watchpoint\t: %s\n",
	122	cpu_has_watch ? "yes" : "no");
4194318c RB	123	seq_printf(m, "ASEs implemented\t:%s%s%s%s\n",
	124	cpu_has_mips16 ? " mips16" : "",
	125	cpu_has_mdmx ? " mdmx" : "",
	126	cpu_has_mips3d ? " mips3d" : "",
	127	cpu_has_smartmips ? " smartmips" : "");
1da177e4 LT	128
	129	sprintf(fmt, "VCE%%c exceptions\t\t: %s\n",
	130	cpu_has_vce ? "%u" : "not available");
	131	seq_printf(m, fmt, 'D', vced_count);
	132	seq_printf(m, fmt, 'I', vcei_count);
	133
	134	return 0;
	135	}
	136
	137	static void c_start(struct seq_file m, loff_t *pos)
	138	{
	139	unsigned long i = *pos;
	140
	141	return i < NR_CPUS ? (void *) (i + 1) : NULL;
	142	}
	143
	144	static void c_next(struct seq_file m, void v, loff_t pos)
	145	{
	146	++*pos;
	147	return c_start(m, pos);
	148	}
	149
	150	static void c_stop(struct seq_file m, void v)
	151	{
	152	}
	153
	154	struct seq_operations cpuinfo_op = {
	155	.start = c_start,
	156	.next = c_next,
	157	.stop = c_stop,
	158	.show = show_cpuinfo,
	159	};