[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / mips / kernel / cpu-bugs64.c

/*
 * Copyright (C) 2003, 2004  Maciej W. Rozycki
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */
#include <linux/config.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/ptrace.h>
#include <linux/stddef.h>

#include <asm/bugs.h>
#include <asm/compiler.h>
#include <asm/cpu.h>
#include <asm/fpu.h>
#include <asm/mipsregs.h>
#include <asm/system.h>

static inline void align_mod(const int align, const int mod)
{
	asm volatile(
		".set	push\n\t"
		".set	noreorder\n\t"
		".balign %0\n\t"
		".rept	%1\n\t"
		"nop\n\t"
		".endr\n\t"
		".set	pop"
		:
		: "n" (align), "n" (mod));
}

static inline void mult_sh_align_mod(long *v1, long *v2, long *w,
				     const int align, const int mod)
{
	unsigned long flags;
	int m1, m2;
	long p, s, lv1, lv2, lw;

	/*
	 * We want the multiply and the shift to be isolated from the
	 * rest of the code to disable gcc optimizations.  Hence the
	 * asm statements that execute nothing, but make gcc not know
	 * what the values of m1, m2 and s are and what lv2 and p are
	 * used for.
	 */

	local_irq_save(flags);
	/*
	 * The following code leads to a wrong result of the first
	 * dsll32 when executed on R4000 rev. 2.2 or 3.0 (PRId
	 * 00000422 or 00000430, respectively).
	 *
	 * See "MIPS R4000PC/SC Errata, Processor Revision 2.2 and
	 * 3.0" by MIPS Technologies, Inc., errata #16 and #28 for
	 * details.  I got no permission to duplicate them here,
	 * sigh... --macro
	 */
	asm volatile(
		""
		: "=r" (m1), "=r" (m2), "=r" (s)
		: "0" (5), "1" (8), "2" (5));
	align_mod(align, mod);
	/*
	 * The trailing nop is needed to fullfill the two-instruction
	 * requirement between reading hi/lo and staring a mult/div.
	 * Leaving it out may cause gas insert a nop itself breaking
	 * the desired alignment of the next chunk.
	 */
	asm volatile(
		".set	push\n\t"
		".set	noat\n\t"
		".set	noreorder\n\t"
		".set	nomacro\n\t"
		"mult	%2, %3\n\t"
		"dsll32	%0, %4, %5\n\t"
		"mflo	$0\n\t"
		"dsll32	%1, %4, %5\n\t"
		"nop\n\t"
		".set	pop"
		: "=&r" (lv1), "=r" (lw)
		: "r" (m1), "r" (m2), "r" (s), "I" (0)
		: "hi", "lo", GCC_REG_ACCUM);
	/* We have to use single integers for m1 and m2 and a double
	 * one for p to be sure the mulsidi3 gcc's RTL multiplication
	 * instruction has the workaround applied.  Older versions of
	 * gcc have correct umulsi3 and mulsi3, but other
	 * multiplication variants lack the workaround.
	 */
	asm volatile(
		""
		: "=r" (m1), "=r" (m2), "=r" (s)
		: "0" (m1), "1" (m2), "2" (s));
	align_mod(align, mod);
	p = m1 * m2;
	lv2 = s << 32;
	asm volatile(
		""
		: "=r" (lv2)
		: "0" (lv2), "r" (p));
	local_irq_restore(flags);

	*v1 = lv1;
	*v2 = lv2;
	*w = lw;
}

static inline void check_mult_sh(void)
{
	long v1[8], v2[8], w[8];
	int bug, fix, i;

	printk("Checking for the multiply/shift bug... ");

	/*
	 * Testing discovered false negatives for certain code offsets
	 * into cache lines.  Hence we test all possible offsets for
	 * the worst assumption of an R4000 I-cache line width of 32
	 * bytes.
	 *
	 * We can't use a loop as alignment directives need to be
	 * immediates.
	 */
	mult_sh_align_mod(&v1[0], &v2[0], &w[0], 32, 0);
	mult_sh_align_mod(&v1[1], &v2[1], &w[1], 32, 1);
	mult_sh_align_mod(&v1[2], &v2[2], &w[2], 32, 2);
	mult_sh_align_mod(&v1[3], &v2[3], &w[3], 32, 3);
	mult_sh_align_mod(&v1[4], &v2[4], &w[4], 32, 4);
	mult_sh_align_mod(&v1[5], &v2[5], &w[5], 32, 5);
	mult_sh_align_mod(&v1[6], &v2[6], &w[6], 32, 6);
	mult_sh_align_mod(&v1[7], &v2[7], &w[7], 32, 7);

	bug = 0;
	for (i = 0; i < 8; i++)
		if (v1[i] != w[i])
			bug = 1;

	if (bug == 0) {
		printk("no.\n");
		return;
	}

	printk("yes, workaround... ");

	fix = 1;
	for (i = 0; i < 8; i++)
		if (v2[i] != w[i])
			fix = 0;

	if (fix == 1) {
		printk("yes.\n");
		return;
	}

	printk("no.\n");
	panic("Reliable operation impossible!\n"
#ifndef CONFIG_CPU_R4000
	      "Configure for R4000 to enable the workaround."
#else
	      "Please report to <linux-mips@linux-mips.org>."
#endif
	      );
}

static volatile int daddi_ov __initdata = 0;

asmlinkage void __init do_daddi_ov(struct pt_regs *regs)
{
	daddi_ov = 1;
	regs->cp0_epc += 4;
}

static inline void check_daddi(void)
{
	extern asmlinkage void handle_daddi_ov(void);
	unsigned long flags;
	void *handler;
	long v, tmp;

	printk("Checking for the daddi bug... ");

	local_irq_save(flags);
	handler = set_except_vector(12, handle_daddi_ov);
	/*
	 * The following code fails to trigger an overflow exception
	 * when executed on R4000 rev. 2.2 or 3.0 (PRId 00000422 or
	 * 00000430, respectively).
	 *
	 * See "MIPS R4000PC/SC Errata, Processor Revision 2.2 and
	 * 3.0" by MIPS Technologies, Inc., erratum #23 for details.
	 * I got no permission to duplicate it here, sigh... --macro
	 */
	asm volatile(
		".set	push\n\t"
		".set	noat\n\t"
		".set	noreorder\n\t"
		".set	nomacro\n\t"
		"addiu	%1, $0, %2\n\t"
		"dsrl	%1, %1, 1\n\t"
#ifdef HAVE_AS_SET_DADDI
		".set	daddi\n\t"
#endif
		"daddi	%0, %1, %3\n\t"
		".set	pop"
		: "=r" (v), "=&r" (tmp)
		: "I" (0xffffffffffffdb9aUL), "I" (0x1234));
	set_except_vector(12, handler);
	local_irq_restore(flags);

	if (daddi_ov) {
		printk("no.\n");
		return;
	}

	printk("yes, workaround... ");

	local_irq_save(flags);
	handler = set_except_vector(12, handle_daddi_ov);
	asm volatile(
		"addiu	%1, $0, %2\n\t"
		"dsrl	%1, %1, 1\n\t"
		"daddi	%0, %1, %3"
		: "=r" (v), "=&r" (tmp)
		: "I" (0xffffffffffffdb9aUL), "I" (0x1234));
	set_except_vector(12, handler);
	local_irq_restore(flags);

	if (daddi_ov) {
		printk("yes.\n");
		return;
	}

	printk("no.\n");
	panic("Reliable operation impossible!\n"
#if !defined(CONFIG_CPU_R4000) && !defined(CONFIG_CPU_R4400)
	      "Configure for R4000 or R4400 to enable the workaround."
#else
	      "Please report to <linux-mips@linux-mips.org>."
#endif
	      );
}

static inline void check_daddiu(void)
{
	long v, w, tmp;

	printk("Checking for the daddiu bug... ");

	/*
	 * The following code leads to a wrong result of daddiu when
	 * executed on R4400 rev. 1.0 (PRId 00000440).
	 *
	 * See "MIPS R4400PC/SC Errata, Processor Revision 1.0" by
	 * MIPS Technologies, Inc., erratum #7 for details.
	 *
	 * According to "MIPS R4000PC/SC Errata, Processor Revision
	 * 2.2 and 3.0" by MIPS Technologies, Inc., erratum #41 this
	 * problem affects R4000 rev. 2.2 and 3.0 (PRId 00000422 and
	 * 00000430, respectively), too.  Testing failed to trigger it
	 * so far.
	 *
	 * I got no permission to duplicate the errata here, sigh...
	 * --macro
	 */
	asm volatile(
		".set	push\n\t"
		".set	noat\n\t"
		".set	noreorder\n\t"
		".set	nomacro\n\t"
		"addiu	%2, $0, %3\n\t"
		"dsrl	%2, %2, 1\n\t"
#ifdef HAVE_AS_SET_DADDI
		".set	daddi\n\t"
#endif
		"daddiu	%0, %2, %4\n\t"
		"addiu	%1, $0, %4\n\t"
		"daddu	%1, %2\n\t"
		".set	pop"
		: "=&r" (v), "=&r" (w), "=&r" (tmp)
		: "I" (0xffffffffffffdb9aUL), "I" (0x1234));

	if (v == w) {
		printk("no.\n");
		return;
	}

	printk("yes, workaround... ");

	asm volatile(
		"addiu	%2, $0, %3\n\t"
		"dsrl	%2, %2, 1\n\t"
		"daddiu	%0, %2, %4\n\t"
		"addiu	%1, $0, %4\n\t"
		"daddu	%1, %2"
		: "=&r" (v), "=&r" (w), "=&r" (tmp)
		: "I" (0xffffffffffffdb9aUL), "I" (0x1234));

	if (v == w) {
		printk("yes.\n");
		return;
	}

	printk("no.\n");
	panic("Reliable operation impossible!\n"
#if !defined(CONFIG_CPU_R4000) && !defined(CONFIG_CPU_R4400)
	      "Configure for R4000 or R4400 to enable the workaround."
#else
	      "Please report to <linux-mips@linux-mips.org>."
#endif
	      );
}

void __init check_bugs64(void)
{
	check_mult_sh();
	check_daddi();
	check_daddiu();
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Copyright (C) 2003, 2004 Maciej W. Rozycki
	3	*
	4	* This program is free software; you can redistribute it and/or
	5	* modify it under the terms of the GNU General Public License
	6	* as published by the Free Software Foundation; either version
	7	* 2 of the License, or (at your option) any later version.
	8	*/
	9	#include <linux/config.h>
	10	#include <linux/init.h>
	11	#include <linux/kernel.h>
	12	#include <linux/ptrace.h>
	13	#include <linux/stddef.h>
	14
	15	#include <asm/bugs.h>
	16	#include <asm/compiler.h>
	17	#include <asm/cpu.h>
	18	#include <asm/fpu.h>
	19	#include <asm/mipsregs.h>
	20	#include <asm/system.h>
	21
	22	static inline void align_mod(const int align, const int mod)
	23	{
	24	asm volatile(
	25	".set push\n\t"
	26	".set noreorder\n\t"
	27	".balign %0\n\t"
	28	".rept %1\n\t"
	29	"nop\n\t"
	30	".endr\n\t"
	31	".set pop"
	32	:
	33	: "n" (align), "n" (mod));
	34	}
	35
	36	static inline void mult_sh_align_mod(long v1, long v2, long *w,
	37	const int align, const int mod)
	38	{
	39	unsigned long flags;
	40	int m1, m2;
	41	long p, s, lv1, lv2, lw;
	42
	43	/*
	44	* We want the multiply and the shift to be isolated from the
	45	* rest of the code to disable gcc optimizations. Hence the
	46	* asm statements that execute nothing, but make gcc not know
	47	* what the values of m1, m2 and s are and what lv2 and p are
	48	* used for.
	49	*/
	50
	51	local_irq_save(flags);
	52	/*
	53	* The following code leads to a wrong result of the first
	54	* dsll32 when executed on R4000 rev. 2.2 or 3.0 (PRId
	55	* 00000422 or 00000430, respectively).
	56	*
	57	* See "MIPS R4000PC/SC Errata, Processor Revision 2.2 and
	58	* 3.0" by MIPS Technologies, Inc., errata #16 and #28 for
	59	* details. I got no permission to duplicate them here,
	60	* sigh... --macro
	61	*/
	62	asm volatile(
	63	""
	64	: "=r" (m1), "=r" (m2), "=r" (s)
65	: "0" (5), "1" (8), "2" (5));
66	align_mod(align, mod);
67	/*
68	* The trailing nop is needed to fullfill the two-instruction
69	* requirement between reading hi/lo and staring a mult/div.
70	* Leaving it out may cause gas insert a nop itself breaking
71	* the desired alignment of the next chunk.
72	*/
73	asm volatile(
74	".set push\n\t"
75	".set noat\n\t"
76	".set noreorder\n\t"
77	".set nomacro\n\t"
78	"mult %2, %3\n\t"
79	"dsll32 %0, %4, %5\n\t"
80	"mflo $0\n\t"
81	"dsll32 %1, %4, %5\n\t"
82	"nop\n\t"
83	".set pop"
84	: "=&r" (lv1), "=r" (lw)
85	: "r" (m1), "r" (m2), "r" (s), "I" (0)
86	: "hi", "lo", GCC_REG_ACCUM);
87	/* We have to use single integers for m1 and m2 and a double
88	* one for p to be sure the mulsidi3 gcc's RTL multiplication
89	* instruction has the workaround applied. Older versions of
90	* gcc have correct umulsi3 and mulsi3, but other
91	* multiplication variants lack the workaround.
92	*/
93	asm volatile(
94	""
95	: "=r" (m1), "=r" (m2), "=r" (s)
96	: "0" (m1), "1" (m2), "2" (s));
97	align_mod(align, mod);
98	p = m1 * m2;
99	lv2 = s << 32;
100	asm volatile(
101	""
102	: "=r" (lv2)
103	: "0" (lv2), "r" (p));
104	local_irq_restore(flags);
105
106	*v1 = lv1;
107	*v2 = lv2;
108	*w = lw;
109	}
110
111	static inline void check_mult_sh(void)
112	{
113	long v1[8], v2[8], w[8];
114	int bug, fix, i;
115
116	printk("Checking for the multiply/shift bug... ");
117
118	/*
119	* Testing discovered false negatives for certain code offsets
120	* into cache lines. Hence we test all possible offsets for
121	* the worst assumption of an R4000 I-cache line width of 32
122	* bytes.
123	*
124	* We can't use a loop as alignment directives need to be
125	* immediates.
126	*/
127	mult_sh_align_mod(&v1[0], &v2[0], &w[0], 32, 0);
128	mult_sh_align_mod(&v1[1], &v2[1], &w[1], 32, 1);
129	mult_sh_align_mod(&v1[2], &v2[2], &w[2], 32, 2);
130	mult_sh_align_mod(&v1[3], &v2[3], &w[3], 32, 3);
131	mult_sh_align_mod(&v1[4], &v2[4], &w[4], 32, 4);
132	mult_sh_align_mod(&v1[5], &v2[5], &w[5], 32, 5);
133	mult_sh_align_mod(&v1[6], &v2[6], &w[6], 32, 6);
134	mult_sh_align_mod(&v1[7], &v2[7], &w[7], 32, 7);
135
136	bug = 0;
137	for (i = 0; i < 8; i++)
138	if (v1[i] != w[i])
139	bug = 1;
42a3b4f2	140
1da177e4 LT	141	if (bug == 0) {
	142	printk("no.\n");
	143	return;
	144	}
	145
	146	printk("yes, workaround... ");
	147
	148	fix = 1;
	149	for (i = 0; i < 8; i++)
	150	if (v2[i] != w[i])
	151	fix = 0;
42a3b4f2	152
1da177e4 LT	153	if (fix == 1) {
	154	printk("yes.\n");
	155	return;
	156	}
	157
	158	printk("no.\n");
	159	panic("Reliable operation impossible!\n"
	160	#ifndef CONFIG_CPU_R4000
	161	"Configure for R4000 to enable the workaround."
	162	#else
	163	"Please report to <linux-mips@linux-mips.org>."
	164	#endif
	165	);
	166	}
	167
	168	static volatile int daddi_ov __initdata = 0;
	169
	170	asmlinkage void __init do_daddi_ov(struct pt_regs *regs)
	171	{
	172	daddi_ov = 1;
	173	regs->cp0_epc += 4;
	174	}
	175
	176	static inline void check_daddi(void)
	177	{
	178	extern asmlinkage void handle_daddi_ov(void);
	179	unsigned long flags;
	180	void *handler;
	181	long v, tmp;
	182
	183	printk("Checking for the daddi bug... ");
	184
	185	local_irq_save(flags);
	186	handler = set_except_vector(12, handle_daddi_ov);
	187	/*
	188	* The following code fails to trigger an overflow exception
	189	* when executed on R4000 rev. 2.2 or 3.0 (PRId 00000422 or
	190	* 00000430, respectively).
	191	*
	192	* See "MIPS R4000PC/SC Errata, Processor Revision 2.2 and
	193	* 3.0" by MIPS Technologies, Inc., erratum #23 for details.
	194	* I got no permission to duplicate it here, sigh... --macro
	195	*/
	196	asm volatile(
	197	".set push\n\t"
	198	".set noat\n\t"
	199	".set noreorder\n\t"
	200	".set nomacro\n\t"
	201	"addiu %1, $0, %2\n\t"
	202	"dsrl %1, %1, 1\n\t"
	203	#ifdef HAVE_AS_SET_DADDI
	204	".set daddi\n\t"
	205	#endif
	206	"daddi %0, %1, %3\n\t"
	207	".set pop"
	208	: "=r" (v), "=&r" (tmp)
460c0422	209	: "I" (0xffffffffffffdb9aUL), "I" (0x1234));
1da177e4 LT	210	set_except_vector(12, handler);
	211	local_irq_restore(flags);
	212
	213	if (daddi_ov) {
	214	printk("no.\n");
	215	return;
	216	}
	217
	218	printk("yes, workaround... ");
	219
	220	local_irq_save(flags);
	221	handler = set_except_vector(12, handle_daddi_ov);
	222	asm volatile(
	223	"addiu %1, $0, %2\n\t"
	224	"dsrl %1, %1, 1\n\t"
	225	"daddi %0, %1, %3"
	226	: "=r" (v), "=&r" (tmp)
460c0422	227	: "I" (0xffffffffffffdb9aUL), "I" (0x1234));
1da177e4 LT	228	set_except_vector(12, handler);
	229	local_irq_restore(flags);
	230
	231	if (daddi_ov) {
	232	printk("yes.\n");
	233	return;
	234	}
	235
	236	printk("no.\n");
	237	panic("Reliable operation impossible!\n"
	238	#if !defined(CONFIG_CPU_R4000) && !defined(CONFIG_CPU_R4400)
	239	"Configure for R4000 or R4400 to enable the workaround."
	240	#else
	241	"Please report to <linux-mips@linux-mips.org>."
	242	#endif
	243	);
	244	}
	245
	246	static inline void check_daddiu(void)
	247	{
	248	long v, w, tmp;
	249
	250	printk("Checking for the daddiu bug... ");
	251
	252	/*
	253	* The following code leads to a wrong result of daddiu when
	254	* executed on R4400 rev. 1.0 (PRId 00000440).
	255	*
	256	* See "MIPS R4400PC/SC Errata, Processor Revision 1.0" by
	257	* MIPS Technologies, Inc., erratum #7 for details.
	258	*
	259	* According to "MIPS R4000PC/SC Errata, Processor Revision
	260	* 2.2 and 3.0" by MIPS Technologies, Inc., erratum #41 this
	261	* problem affects R4000 rev. 2.2 and 3.0 (PRId 00000422 and
	262	* 00000430, respectively), too. Testing failed to trigger it
	263	* so far.
	264	*
	265	* I got no permission to duplicate the errata here, sigh...
	266	* --macro
	267	*/
	268	asm volatile(
	269	".set push\n\t"
	270	".set noat\n\t"
	271	".set noreorder\n\t"
	272	".set nomacro\n\t"
	273	"addiu %2, $0, %3\n\t"
	274	"dsrl %2, %2, 1\n\t"
	275	#ifdef HAVE_AS_SET_DADDI
	276	".set daddi\n\t"
	277	#endif
	278	"daddiu %0, %2, %4\n\t"
	279	"addiu %1, $0, %4\n\t"
	280	"daddu %1, %2\n\t"
	281	".set pop"
	282	: "=&r" (v), "=&r" (w), "=&r" (tmp)
460c0422	283	: "I" (0xffffffffffffdb9aUL), "I" (0x1234));
1da177e4 LT	284
	285	if (v == w) {
	286	printk("no.\n");
	287	return;
	288	}
	289
	290	printk("yes, workaround... ");
	291
	292	asm volatile(
	293	"addiu %2, $0, %3\n\t"
	294	"dsrl %2, %2, 1\n\t"
	295	"daddiu %0, %2, %4\n\t"
	296	"addiu %1, $0, %4\n\t"
	297	"daddu %1, %2"
	298	: "=&r" (v), "=&r" (w), "=&r" (tmp)
460c0422	299	: "I" (0xffffffffffffdb9aUL), "I" (0x1234));
1da177e4 LT	300
	301	if (v == w) {
	302	printk("yes.\n");
	303	return;
	304	}
	305
	306	printk("no.\n");
	307	panic("Reliable operation impossible!\n"
	308	#if !defined(CONFIG_CPU_R4000) && !defined(CONFIG_CPU_R4400)
	309	"Configure for R4000 or R4400 to enable the workaround."
	310	#else
	311	"Please report to <linux-mips@linux-mips.org>."
	312	#endif
	313	);
	314	}
	315
	316	void __init check_bugs64(void)
	317	{
	318	check_mult_sh();
	319	check_daddi();
	320	check_daddiu();
	321	}