[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / mips / include / asm / processor.h

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1994 Waldorf GMBH
 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
 * Copyright (C) 1996 Paul M. Antoine
 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
 */
#ifndef _ASM_PROCESSOR_H
#define _ASM_PROCESSOR_H

#include <linux/cpumask.h>
#include <linux/threads.h>

#include <asm/cachectl.h>
#include <asm/cpu.h>
#include <asm/cpu-info.h>
#include <asm/mipsregs.h>
#include <asm/prefetch.h>

/*
 * Return current * instruction pointer ("program counter").
 */
#define current_text_addr() ({ __label__ _l; _l: &&_l;})

/*
 * System setup and hardware flags..
 */
extern void (*cpu_wait)(void);

extern unsigned int vced_count, vcei_count;

/*
 * MIPS does have an arch_pick_mmap_layout()
 */
#define HAVE_ARCH_PICK_MMAP_LAYOUT 1

/*
 * A special page (the vdso) is mapped into all processes at the very
 * top of the virtual memory space.
 */
#define SPECIAL_PAGES_SIZE PAGE_SIZE

#ifdef CONFIG_32BIT
/*
 * User space process size: 2GB. This is hardcoded into a few places,
 * so don't change it unless you know what you are doing.
 */
#define TASK_SIZE	0x7fff8000UL

#ifdef __KERNEL__
#define STACK_TOP_MAX	TASK_SIZE
#endif

#define TASK_IS_32BIT_ADDR 1

#endif

#ifdef CONFIG_64BIT
/*
 * User space process size: 1TB. This is hardcoded into a few places,
 * so don't change it unless you know what you are doing.  TASK_SIZE
 * is limited to 1TB by the R4000 architecture; R10000 and better can
 * support 16TB; the architectural reserve for future expansion is
 * 8192EB ...
 */
#define TASK_SIZE32	0x7fff8000UL
#define TASK_SIZE64	0x10000000000UL
#define TASK_SIZE (test_thread_flag(TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64)

#ifdef __KERNEL__
#define STACK_TOP_MAX	TASK_SIZE64
#endif


#define TASK_SIZE_OF(tsk)						\
	(test_tsk_thread_flag(tsk, TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64)

#define TASK_IS_32BIT_ADDR test_thread_flag(TIF_32BIT_ADDR)

#endif

#define STACK_TOP	((TASK_SIZE & PAGE_MASK) - SPECIAL_PAGES_SIZE)

/*
 * This decides where the kernel will search for a free chunk of vm
 * space during mmap's.
 */
#define TASK_UNMAPPED_BASE PAGE_ALIGN(TASK_SIZE / 3)


#define NUM_FPU_REGS	32

typedef __u64 fpureg_t;

/*
 * It would be nice to add some more fields for emulator statistics, but there
 * are a number of fixed offsets in offset.h and elsewhere that would have to
 * be recalculated by hand.  So the additional information will be private to
 * the FPU emulator for now.  See asm-mips/fpu_emulator.h.
 */

struct mips_fpu_struct {
	fpureg_t	fpr[NUM_FPU_REGS];
	unsigned int	fcr31;
};

#define NUM_DSP_REGS   6

typedef __u32 dspreg_t;

struct mips_dsp_state {
	dspreg_t	dspr[NUM_DSP_REGS];
	unsigned int	dspcontrol;
};

#define INIT_CPUMASK { \
	{0,} \
}

struct mips3264_watch_reg_state {
	/* The width of watchlo is 32 in a 32 bit kernel and 64 in a
	   64 bit kernel.  We use unsigned long as it has the same
	   property. */
	unsigned long watchlo[NUM_WATCH_REGS];
	/* Only the mask and IRW bits from watchhi. */
	u16 watchhi[NUM_WATCH_REGS];
};

union mips_watch_reg_state {
	struct mips3264_watch_reg_state mips3264;
};

#ifdef CONFIG_CPU_CAVIUM_OCTEON

struct octeon_cop2_state {
	/* DMFC2 rt, 0x0201 */
	unsigned long	cop2_crc_iv;
	/* DMFC2 rt, 0x0202 (Set with DMTC2 rt, 0x1202) */
	unsigned long	cop2_crc_length;
	/* DMFC2 rt, 0x0200 (set with DMTC2 rt, 0x4200) */
	unsigned long	cop2_crc_poly;
	/* DMFC2 rt, 0x0402; DMFC2 rt, 0x040A */
	unsigned long	cop2_llm_dat[2];
       /* DMFC2 rt, 0x0084 */
	unsigned long	cop2_3des_iv;
	/* DMFC2 rt, 0x0080; DMFC2 rt, 0x0081; DMFC2 rt, 0x0082 */
	unsigned long	cop2_3des_key[3];
	/* DMFC2 rt, 0x0088 (Set with DMTC2 rt, 0x0098) */
	unsigned long	cop2_3des_result;
	/* DMFC2 rt, 0x0111 (FIXME: Read Pass1 Errata) */
	unsigned long	cop2_aes_inp0;
	/* DMFC2 rt, 0x0102; DMFC2 rt, 0x0103 */
	unsigned long	cop2_aes_iv[2];
	/* DMFC2 rt, 0x0104; DMFC2 rt, 0x0105; DMFC2 rt, 0x0106; DMFC2
	 * rt, 0x0107 */
	unsigned long	cop2_aes_key[4];
	/* DMFC2 rt, 0x0110 */
	unsigned long	cop2_aes_keylen;
	/* DMFC2 rt, 0x0100; DMFC2 rt, 0x0101 */
	unsigned long	cop2_aes_result[2];
	/* DMFC2 rt, 0x0240; DMFC2 rt, 0x0241; DMFC2 rt, 0x0242; DMFC2
	 * rt, 0x0243; DMFC2 rt, 0x0244; DMFC2 rt, 0x0245; DMFC2 rt,
	 * 0x0246; DMFC2 rt, 0x0247; DMFC2 rt, 0x0248; DMFC2 rt,
	 * 0x0249; DMFC2 rt, 0x024A; DMFC2 rt, 0x024B; DMFC2 rt,
	 * 0x024C; DMFC2 rt, 0x024D; DMFC2 rt, 0x024E - Pass2 */
	unsigned long	cop2_hsh_datw[15];
	/* DMFC2 rt, 0x0250; DMFC2 rt, 0x0251; DMFC2 rt, 0x0252; DMFC2
	 * rt, 0x0253; DMFC2 rt, 0x0254; DMFC2 rt, 0x0255; DMFC2 rt,
	 * 0x0256; DMFC2 rt, 0x0257 - Pass2 */
	unsigned long	cop2_hsh_ivw[8];
	/* DMFC2 rt, 0x0258; DMFC2 rt, 0x0259 - Pass2 */
	unsigned long	cop2_gfm_mult[2];
	/* DMFC2 rt, 0x025E - Pass2 */
	unsigned long	cop2_gfm_poly;
	/* DMFC2 rt, 0x025A; DMFC2 rt, 0x025B - Pass2 */
	unsigned long	cop2_gfm_result[2];
};
#define INIT_OCTEON_COP2 {0,}

struct octeon_cvmseg_state {
	unsigned long cvmseg[CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE]
			    [cpu_dcache_line_size() / sizeof(unsigned long)];
};

#endif

typedef struct {
	unsigned long seg;
} mm_segment_t;

#define ARCH_MIN_TASKALIGN	8

struct mips_abi;

/*
 * If you change thread_struct remember to change the #defines below too!
 */
struct thread_struct {
	/* Saved main processor registers. */
	unsigned long reg16;
	unsigned long reg17, reg18, reg19, reg20, reg21, reg22, reg23;
	unsigned long reg29, reg30, reg31;

	/* Saved cp0 stuff. */
	unsigned long cp0_status;

	/* Saved fpu/fpu emulator stuff. */
	struct mips_fpu_struct fpu;
#ifdef CONFIG_MIPS_MT_FPAFF
	/* Emulated instruction count */
	unsigned long emulated_fp;
	/* Saved per-thread scheduler affinity mask */
	cpumask_t user_cpus_allowed;
#endif /* CONFIG_MIPS_MT_FPAFF */

	/* Saved state of the DSP ASE, if available. */
	struct mips_dsp_state dsp;

	/* Saved watch register state, if available. */
	union mips_watch_reg_state watch;

	/* Other stuff associated with the thread. */
	unsigned long cp0_badvaddr;	/* Last user fault */
	unsigned long cp0_baduaddr;	/* Last kernel fault accessing USEG */
	unsigned long error_code;
#ifdef CONFIG_CPU_CAVIUM_OCTEON
    struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128)));
    struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128)));
#endif
	struct mips_abi *abi;
};

#ifdef CONFIG_MIPS_MT_FPAFF
#define FPAFF_INIT						\
	.emulated_fp			= 0,			\
	.user_cpus_allowed		= INIT_CPUMASK,
#else
#define FPAFF_INIT
#endif /* CONFIG_MIPS_MT_FPAFF */

#ifdef CONFIG_CPU_CAVIUM_OCTEON
#define OCTEON_INIT						\
	.cp2			= INIT_OCTEON_COP2,
#else
#define OCTEON_INIT
#endif /* CONFIG_CPU_CAVIUM_OCTEON */

#define INIT_THREAD  {						\
	/*							\
	 * Saved main processor registers			\
	 */							\
	.reg16			= 0,				\
	.reg17			= 0,				\
	.reg18			= 0,				\
	.reg19			= 0,				\
	.reg20			= 0,				\
	.reg21			= 0,				\
	.reg22			= 0,				\
	.reg23			= 0,				\
	.reg29			= 0,				\
	.reg30			= 0,				\
	.reg31			= 0,				\
	/*							\
	 * Saved cp0 stuff					\
	 */							\
	.cp0_status		= 0,				\
	/*							\
	 * Saved FPU/FPU emulator stuff				\
	 */							\
	.fpu			= {				\
		.fpr		= {0,},				\
		.fcr31		= 0,				\
	},							\
	/*							\
	 * FPU affinity state (null if not FPAFF)		\
	 */							\
	FPAFF_INIT						\
	/*							\
	 * Saved DSP stuff					\
	 */							\
	.dsp			= {				\
		.dspr		= {0, },			\
		.dspcontrol	= 0,				\
	},							\
	/*							\
	 * saved watch register stuff				\
	 */							\
	.watch = {{{0,},},},					\
	/*							\
	 * Other stuff associated with the process		\
	 */							\
	.cp0_badvaddr		= 0,				\
	.cp0_baduaddr		= 0,				\
	.error_code		= 0,				\
	/*							\
	 * Cavium Octeon specifics (null if not Octeon)		\
	 */							\
	OCTEON_INIT						\
}

struct task_struct;

/* Free all resources held by a thread. */
#define release_thread(thread) do { } while(0)

extern unsigned long thread_saved_pc(struct task_struct *tsk);

/*
 * Do necessary setup to start up a newly executed thread.
 */
extern void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp);

unsigned long get_wchan(struct task_struct *p);

#define __KSTK_TOS(tsk) ((unsigned long)task_stack_page(tsk) + \
			 THREAD_SIZE - 32 - sizeof(struct pt_regs))
#define task_pt_regs(tsk) ((struct pt_regs *)__KSTK_TOS(tsk))
#define KSTK_EIP(tsk) (task_pt_regs(tsk)->cp0_epc)
#define KSTK_ESP(tsk) (task_pt_regs(tsk)->regs[29])
#define KSTK_STATUS(tsk) (task_pt_regs(tsk)->cp0_status)

#define cpu_relax()	barrier()

/*
 * Return_address is a replacement for __builtin_return_address(count)
 * which on certain architectures cannot reasonably be implemented in GCC
 * (MIPS, Alpha) or is unusable with -fomit-frame-pointer (i386).
 * Note that __builtin_return_address(x>=1) is forbidden because GCC
 * aborts compilation on some CPUs.  It's simply not possible to unwind
 * some CPU's stackframes.
 *
 * __builtin_return_address works only for non-leaf functions.	We avoid the
 * overhead of a function call by forcing the compiler to save the return
 * address register on the stack.
 */
#define return_address() ({__asm__ __volatile__("":::"$31");__builtin_return_address(0);})

#ifdef CONFIG_CPU_HAS_PREFETCH

#define ARCH_HAS_PREFETCH
#define prefetch(x) __builtin_prefetch((x), 0, 1)

#define ARCH_HAS_PREFETCHW
#define prefetchw(x) __builtin_prefetch((x), 1, 1)

/*
 * See Documentation/scheduler/sched-arch.txt; prevents deadlock on SMP
 * systems.
 */
#define __ARCH_WANT_UNLOCKED_CTXSW

#endif

#endif /* _ASM_PROCESSOR_H */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 1994 Waldorf GMBH
	7	* Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
	8	* Copyright (C) 1996 Paul M. Antoine
	9	* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
	10	*/
	11	#ifndef _ASM_PROCESSOR_H
	12	#define _ASM_PROCESSOR_H
	13
41c594ab	14	#include <linux/cpumask.h>
1da177e4 LT	15	#include <linux/threads.h>
	16
	17	#include <asm/cachectl.h>
	18	#include <asm/cpu.h>
	19	#include <asm/cpu-info.h>
	20	#include <asm/mipsregs.h>
	21	#include <asm/prefetch.h>
1da177e4 LT	22
	23	/*
	24	* Return current * instruction pointer ("program counter").
	25	*/
	26	#define current_text_addr() ({ __label__ _l; _l: &&_l;})
	27
	28	/*
	29	* System setup and hardware flags..
	30	*/
	31	extern void (*cpu_wait)(void);
	32
	33	extern unsigned int vced_count, vcei_count;
	34
1091458d DD	35	/*
	36	* MIPS does have an arch_pick_mmap_layout()
	37	*/
	38	#define HAVE_ARCH_PICK_MMAP_LAYOUT 1
	39
c52d0d30 DD	40	/*
	41	* A special page (the vdso) is mapped into all processes at the very
	42	* top of the virtual memory space.
	43	*/
	44	#define SPECIAL_PAGES_SIZE PAGE_SIZE
	45
875d43e7	46	#ifdef CONFIG_32BIT
1da177e4 LT	47	/*
	48	* User space process size: 2GB. This is hardcoded into a few places,
	49	* so don't change it unless you know what you are doing.
	50	*/
	51	#define TASK_SIZE 0x7fff8000UL
	52
949e51be DD	53	#ifdef __KERNEL__
	54	#define STACK_TOP_MAX TASK_SIZE
	55	#endif
1091458d DD	56
	57	#define TASK_IS_32BIT_ADDR 1
	58
1da177e4 LT	59	#endif
1da177e4 LT	60
875d43e7	61	#ifdef CONFIG_64BIT
1da177e4 LT	62	/*
	63	* User space process size: 1TB. This is hardcoded into a few places,
	64	* so don't change it unless you know what you are doing. TASK_SIZE
	65	* is limited to 1TB by the R4000 architecture; R10000 and better can
	66	* support 16TB; the architectural reserve for future expansion is
	67	* 8192EB ...
	68	*/
	69	#define TASK_SIZE32 0x7fff8000UL
949e51be DD	70	#define TASK_SIZE64 0x10000000000UL
	71	#define TASK_SIZE (test_thread_flag(TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64)
	72
	73	#ifdef __KERNEL__
	74	#define STACK_TOP_MAX TASK_SIZE64
	75	#endif
	76
1da177e4	77
82455257	78	#define TASK_SIZE_OF(tsk) \
949e51be	79	(test_tsk_thread_flag(tsk, TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64)
1091458d DD	80
	81	#define TASK_IS_32BIT_ADDR test_thread_flag(TIF_32BIT_ADDR)
	82
1da177e4 LT	83	#endif
1da177e4 LT	84
949e51be DD	85	#define STACK_TOP ((TASK_SIZE & PAGE_MASK) - SPECIAL_PAGES_SIZE)
	86
	87	/*
	88	* This decides where the kernel will search for a free chunk of vm
	89	* space during mmap's.
	90	*/
	91	#define TASK_UNMAPPED_BASE PAGE_ALIGN(TASK_SIZE / 3)
	92
922a70d3	93
1da177e4 LT	94	#define NUM_FPU_REGS 32
	95
	96	typedef __u64 fpureg_t;
	97
1da177e4 LT	98	/*
	99	* It would be nice to add some more fields for emulator statistics, but there
	100	* are a number of fixed offsets in offset.h and elsewhere that would have to
	101	* be recalculated by hand. So the additional information will be private to
	102	* the FPU emulator for now. See asm-mips/fpu_emulator.h.
	103	*/
	104
eae89076	105	struct mips_fpu_struct {
1da177e4 LT	106	fpureg_t fpr[NUM_FPU_REGS];
	107	unsigned int fcr31;
	108	};
	109
e50c0a8f RB	110	#define NUM_DSP_REGS 6
	111
	112	typedef __u32 dspreg_t;
	113
	114	struct mips_dsp_state {
70342287 RB	115	dspreg_t dspr[NUM_DSP_REGS];
70342287 RB	116	unsigned int dspcontrol;
e50c0a8f RB	117	};
e50c0a8f RB	118
41c594ab RB	119	#define INIT_CPUMASK { \
	120	{0,} \
	121	}
	122
6aa3524c DD	123	struct mips3264_watch_reg_state {
	124	/* The width of watchlo is 32 in a 32 bit kernel and 64 in a
	125	64 bit kernel. We use unsigned long as it has the same
	126	property. */
	127	unsigned long watchlo[NUM_WATCH_REGS];
	128	/* Only the mask and IRW bits from watchhi. */
	129	u16 watchhi[NUM_WATCH_REGS];
	130	};
	131
	132	union mips_watch_reg_state {
	133	struct mips3264_watch_reg_state mips3264;
	134	};
	135
b5e00af8 DD	136	#ifdef CONFIG_CPU_CAVIUM_OCTEON
	137
	138	struct octeon_cop2_state {
	139	/* DMFC2 rt, 0x0201 */
70342287	140	unsigned long cop2_crc_iv;
b5e00af8	141	/* DMFC2 rt, 0x0202 (Set with DMTC2 rt, 0x1202) */
70342287	142	unsigned long cop2_crc_length;
b5e00af8	143	/* DMFC2 rt, 0x0200 (set with DMTC2 rt, 0x4200) */
70342287	144	unsigned long cop2_crc_poly;
b5e00af8	145	/* DMFC2 rt, 0x0402; DMFC2 rt, 0x040A */
70342287	146	unsigned long cop2_llm_dat[2];
b5e00af8	147	/* DMFC2 rt, 0x0084 */
70342287	148	unsigned long cop2_3des_iv;
b5e00af8	149	/* DMFC2 rt, 0x0080; DMFC2 rt, 0x0081; DMFC2 rt, 0x0082 */
70342287	150	unsigned long cop2_3des_key[3];
b5e00af8	151	/* DMFC2 rt, 0x0088 (Set with DMTC2 rt, 0x0098) */
70342287	152	unsigned long cop2_3des_result;
b5e00af8	153	/* DMFC2 rt, 0x0111 (FIXME: Read Pass1 Errata) */
70342287	154	unsigned long cop2_aes_inp0;
b5e00af8	155	/* DMFC2 rt, 0x0102; DMFC2 rt, 0x0103 */
70342287	156	unsigned long cop2_aes_iv[2];
b5e00af8 DD	157	/* DMFC2 rt, 0x0104; DMFC2 rt, 0x0105; DMFC2 rt, 0x0106; DMFC2
b5e00af8 DD	158	* rt, 0x0107 */
70342287	159	unsigned long cop2_aes_key[4];
b5e00af8	160	/* DMFC2 rt, 0x0110 */
70342287	161	unsigned long cop2_aes_keylen;
b5e00af8	162	/* DMFC2 rt, 0x0100; DMFC2 rt, 0x0101 */
70342287	163	unsigned long cop2_aes_result[2];
b5e00af8 DD	164	/* DMFC2 rt, 0x0240; DMFC2 rt, 0x0241; DMFC2 rt, 0x0242; DMFC2
	165	* rt, 0x0243; DMFC2 rt, 0x0244; DMFC2 rt, 0x0245; DMFC2 rt,
	166	* 0x0246; DMFC2 rt, 0x0247; DMFC2 rt, 0x0248; DMFC2 rt,
	167	* 0x0249; DMFC2 rt, 0x024A; DMFC2 rt, 0x024B; DMFC2 rt,
	168	* 0x024C; DMFC2 rt, 0x024D; DMFC2 rt, 0x024E - Pass2 */
70342287	169	unsigned long cop2_hsh_datw[15];
b5e00af8 DD	170	/* DMFC2 rt, 0x0250; DMFC2 rt, 0x0251; DMFC2 rt, 0x0252; DMFC2
	171	* rt, 0x0253; DMFC2 rt, 0x0254; DMFC2 rt, 0x0255; DMFC2 rt,
	172	* 0x0256; DMFC2 rt, 0x0257 - Pass2 */
70342287	173	unsigned long cop2_hsh_ivw[8];
b5e00af8	174	/* DMFC2 rt, 0x0258; DMFC2 rt, 0x0259 - Pass2 */
70342287	175	unsigned long cop2_gfm_mult[2];
b5e00af8	176	/* DMFC2 rt, 0x025E - Pass2 */
70342287	177	unsigned long cop2_gfm_poly;
b5e00af8	178	/* DMFC2 rt, 0x025A; DMFC2 rt, 0x025B - Pass2 */
70342287	179	unsigned long cop2_gfm_result[2];
b5e00af8 DD	180	};
	181	#define INIT_OCTEON_COP2 {0,}
	182
	183	struct octeon_cvmseg_state {
	184	unsigned long cvmseg[CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE]
	185	[cpu_dcache_line_size() / sizeof(unsigned long)];
	186	};
	187
	188	#endif
	189
1da177e4 LT	190	typedef struct {
	191	unsigned long seg;
	192	} mm_segment_t;
	193
	194	#define ARCH_MIN_TASKALIGN 8
	195
e50c0a8f RB	196	struct mips_abi;
e50c0a8f RB	197
1da177e4 LT	198	/*
	199	* If you change thread_struct remember to change the #defines below too!
	200	*/
	201	struct thread_struct {
	202	/* Saved main processor registers. */
	203	unsigned long reg16;
	204	unsigned long reg17, reg18, reg19, reg20, reg21, reg22, reg23;
	205	unsigned long reg29, reg30, reg31;
	206
	207	/* Saved cp0 stuff. */
	208	unsigned long cp0_status;
	209
	210	/* Saved fpu/fpu emulator stuff. */
eae89076	211	struct mips_fpu_struct fpu;
f088fc84 RB	212	#ifdef CONFIG_MIPS_MT_FPAFF
	213	/* Emulated instruction count */
	214	unsigned long emulated_fp;
	215	/* Saved per-thread scheduler affinity mask */
	216	cpumask_t user_cpus_allowed;
	217	#endif /* CONFIG_MIPS_MT_FPAFF */
1da177e4	218
e50c0a8f RB	219	/* Saved state of the DSP ASE, if available. */
	220	struct mips_dsp_state dsp;
	221
6aa3524c DD	222	/* Saved watch register state, if available. */
	223	union mips_watch_reg_state watch;
	224
1da177e4 LT	225	/* Other stuff associated with the thread. */
	226	unsigned long cp0_badvaddr; /* Last user fault */
	227	unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */
	228	unsigned long error_code;
b5e00af8 DD	229	#ifdef CONFIG_CPU_CAVIUM_OCTEON
	230	struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128)));
	231	struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128)));
	232	#endif
e50c0a8f	233	struct mips_abi *abi;
1da177e4 LT	234	};
1da177e4 LT	235
f088fc84	236	#ifdef CONFIG_MIPS_MT_FPAFF
fee578fa RB	237	#define FPAFF_INIT \
	238	.emulated_fp = 0, \
	239	.user_cpus_allowed = INIT_CPUMASK,
f088fc84 RB	240	#else
	241	#define FPAFF_INIT
	242	#endif /* CONFIG_MIPS_MT_FPAFF */
	243
b5e00af8 DD	244	#ifdef CONFIG_CPU_CAVIUM_OCTEON
	245	#define OCTEON_INIT \
	246	.cp2 = INIT_OCTEON_COP2,
	247	#else
	248	#define OCTEON_INIT
	249	#endif /* CONFIG_CPU_CAVIUM_OCTEON */
	250
fee578fa	251	#define INIT_THREAD { \
70342287 RB	252	/* \
	253	* Saved main processor registers \
	254	*/ \
fee578fa RB	255	.reg16 = 0, \
	256	.reg17 = 0, \
	257	.reg18 = 0, \
	258	.reg19 = 0, \
	259	.reg20 = 0, \
	260	.reg21 = 0, \
	261	.reg22 = 0, \
	262	.reg23 = 0, \
	263	.reg29 = 0, \
	264	.reg30 = 0, \
	265	.reg31 = 0, \
	266	/* \
	267	* Saved cp0 stuff \
	268	*/ \
	269	.cp0_status = 0, \
	270	/* \
	271	* Saved FPU/FPU emulator stuff \
	272	*/ \
	273	.fpu = { \
	274	.fpr = {0,}, \
	275	.fcr31 = 0, \
	276	}, \
	277	/* \
	278	* FPU affinity state (null if not FPAFF) \
	279	*/ \
	280	FPAFF_INIT \
	281	/* \
	282	* Saved DSP stuff \
	283	*/ \
	284	.dsp = { \
	285	.dspr = {0, }, \
	286	.dspcontrol = 0, \
	287	}, \
6aa3524c DD	288	/* \
	289	* saved watch register stuff \
	290	*/ \
	291	.watch = {{{0,},},}, \
fee578fa RB	292	/* \
	293	* Other stuff associated with the process \
	294	*/ \
	295	.cp0_badvaddr = 0, \
	296	.cp0_baduaddr = 0, \
	297	.error_code = 0, \
b5e00af8 DD	298	/* \
	299	* Cavium Octeon specifics (null if not Octeon) \
	300	*/ \
	301	OCTEON_INIT \
1da177e4 LT	302	}
	303
	304	struct task_struct;
	305
	306	/* Free all resources held by a thread. */
	307	#define release_thread(thread) do { } while(0)
	308
1da177e4 LT	309	extern unsigned long thread_saved_pc(struct task_struct *tsk);
	310
	311	/*
	312	* Do necessary setup to start up a newly executed thread.
	313	*/
	314	extern void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp);
	315
	316	unsigned long get_wchan(struct task_struct *p);
	317
484889fc DD	318	#define __KSTK_TOS(tsk) ((unsigned long)task_stack_page(tsk) + \
	319	THREAD_SIZE - 32 - sizeof(struct pt_regs))
	320	#define task_pt_regs(tsk) ((struct pt_regs *)__KSTK_TOS(tsk))
40bc9c67 AV	321	#define KSTK_EIP(tsk) (task_pt_regs(tsk)->cp0_epc)
	322	#define KSTK_ESP(tsk) (task_pt_regs(tsk)->regs[29])
	323	#define KSTK_STATUS(tsk) (task_pt_regs(tsk)->cp0_status)
1da177e4 LT	324
	325	#define cpu_relax() barrier()
	326
	327	/*
	328	* Return_address is a replacement for __builtin_return_address(count)
	329	* which on certain architectures cannot reasonably be implemented in GCC
25985edc	330	* (MIPS, Alpha) or is unusable with -fomit-frame-pointer (i386).
1da177e4 LT	331	* Note that __builtin_return_address(x>=1) is forbidden because GCC
	332	* aborts compilation on some CPUs. It's simply not possible to unwind
	333	* some CPU's stackframes.
	334	*
70342287	335	* __builtin_return_address works only for non-leaf functions. We avoid the
1da177e4 LT	336	* overhead of a function call by forcing the compiler to save the return
	337	* address register on the stack.
	338	*/
	339	#define return_address() ({__asm__ __volatile__("":::"$31");__builtin_return_address(0);})
	340
	341	#ifdef CONFIG_CPU_HAS_PREFETCH
	342
	343	#define ARCH_HAS_PREFETCH
0453fb3c	344	#define prefetch(x) __builtin_prefetch((x), 0, 1)
1da177e4	345
0453fb3c DD	346	#define ARCH_HAS_PREFETCHW
0453fb3c DD	347	#define prefetchw(x) __builtin_prefetch((x), 1, 1)
1da177e4	348
b81947c6 DH	349	/*
	350	* See Documentation/scheduler/sched-arch.txt; prevents deadlock on SMP
	351	* systems.
	352	*/
	353	#define __ARCH_WANT_UNLOCKED_CTXSW
	354
1da177e4 LT	355	#endif
	356
	357	#endif /* _ASM_PROCESSOR_H */