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1 | /***********************license start*************** |
2 | * Author: Cavium Networks | |
3 | * | |
4 | * Contact: support@caviumnetworks.com | |
5 | * This file is part of the OCTEON SDK | |
6 | * | |
b8db85b5 | 7 | * Copyright (c) 2003-2010 Cavium Networks |
58f07778 DD |
8 | * |
9 | * This file is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License, Version 2, as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This file is distributed in the hope that it will be useful, but | |
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | |
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | |
16 | * NONINFRINGEMENT. See the GNU General Public License for more | |
17 | * details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this file; if not, write to the Free Software | |
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
22 | * or visit http://www.gnu.org/licenses/. | |
23 | * | |
24 | * This file may also be available under a different license from Cavium. | |
25 | * Contact Cavium Networks for more information | |
26 | ***********************license end**************************************/ | |
27 | ||
28 | /* | |
58f07778 DD |
29 | * Interface to the Level 2 Cache (L2C) control, measurement, and debugging |
30 | * facilities. | |
31 | */ | |
32 | ||
33 | #ifndef __CVMX_L2C_H__ | |
34 | #define __CVMX_L2C_H__ | |
35 | ||
b8db85b5 DD |
36 | #define CVMX_L2_ASSOC cvmx_l2c_get_num_assoc() /* Deprecated macro, use function */ |
37 | #define CVMX_L2_SET_BITS cvmx_l2c_get_set_bits() /* Deprecated macro, use function */ | |
38 | #define CVMX_L2_SETS cvmx_l2c_get_num_sets() /* Deprecated macro, use function */ | |
58f07778 | 39 | |
58f07778 DD |
40 | |
41 | #define CVMX_L2C_IDX_ADDR_SHIFT 7 /* based on 128 byte cache line size */ | |
42 | #define CVMX_L2C_IDX_MASK (cvmx_l2c_get_num_sets() - 1) | |
43 | ||
44 | /* Defines for index aliasing computations */ | |
b8db85b5 DD |
45 | #define CVMX_L2C_TAG_ADDR_ALIAS_SHIFT (CVMX_L2C_IDX_ADDR_SHIFT + cvmx_l2c_get_set_bits()) |
46 | #define CVMX_L2C_ALIAS_MASK (CVMX_L2C_IDX_MASK << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) | |
47 | #define CVMX_L2C_MEMBANK_SELECT_SIZE 4096 | |
58f07778 | 48 | |
b8db85b5 DD |
49 | /* Defines for Virtualizations, valid only from Octeon II onwards. */ |
50 | #define CVMX_L2C_VRT_MAX_VIRTID_ALLOWED ((OCTEON_IS_MODEL(OCTEON_CN63XX)) ? 64 : 0) | |
51 | #define CVMX_L2C_VRT_MAX_MEMSZ_ALLOWED ((OCTEON_IS_MODEL(OCTEON_CN63XX)) ? 32 : 0) | |
58f07778 DD |
52 | |
53 | union cvmx_l2c_tag { | |
54 | uint64_t u64; | |
55 | struct { | |
56 | uint64_t reserved:28; | |
b8db85b5 DD |
57 | uint64_t V:1; /* Line valid */ |
58 | uint64_t D:1; /* Line dirty */ | |
59 | uint64_t L:1; /* Line locked */ | |
60 | uint64_t U:1; /* Use, LRU eviction */ | |
58f07778 DD |
61 | uint64_t addr:32; /* Phys mem (not all bits valid) */ |
62 | } s; | |
63 | }; | |
64 | ||
b8db85b5 DD |
65 | /* Number of L2C Tag-and-data sections (TADs) that are connected to LMC. */ |
66 | #define CVMX_L2C_TADS 1 | |
67 | ||
58f07778 DD |
68 | /* L2C Performance Counter events. */ |
69 | enum cvmx_l2c_event { | |
b8db85b5 DD |
70 | CVMX_L2C_EVENT_CYCLES = 0, |
71 | CVMX_L2C_EVENT_INSTRUCTION_MISS = 1, | |
72 | CVMX_L2C_EVENT_INSTRUCTION_HIT = 2, | |
73 | CVMX_L2C_EVENT_DATA_MISS = 3, | |
74 | CVMX_L2C_EVENT_DATA_HIT = 4, | |
75 | CVMX_L2C_EVENT_MISS = 5, | |
76 | CVMX_L2C_EVENT_HIT = 6, | |
77 | CVMX_L2C_EVENT_VICTIM_HIT = 7, | |
78 | CVMX_L2C_EVENT_INDEX_CONFLICT = 8, | |
79 | CVMX_L2C_EVENT_TAG_PROBE = 9, | |
80 | CVMX_L2C_EVENT_TAG_UPDATE = 10, | |
81 | CVMX_L2C_EVENT_TAG_COMPLETE = 11, | |
82 | CVMX_L2C_EVENT_TAG_DIRTY = 12, | |
83 | CVMX_L2C_EVENT_DATA_STORE_NOP = 13, | |
84 | CVMX_L2C_EVENT_DATA_STORE_READ = 14, | |
58f07778 | 85 | CVMX_L2C_EVENT_DATA_STORE_WRITE = 15, |
b8db85b5 DD |
86 | CVMX_L2C_EVENT_FILL_DATA_VALID = 16, |
87 | CVMX_L2C_EVENT_WRITE_REQUEST = 17, | |
88 | CVMX_L2C_EVENT_READ_REQUEST = 18, | |
58f07778 | 89 | CVMX_L2C_EVENT_WRITE_DATA_VALID = 19, |
b8db85b5 DD |
90 | CVMX_L2C_EVENT_XMC_NOP = 20, |
91 | CVMX_L2C_EVENT_XMC_LDT = 21, | |
92 | CVMX_L2C_EVENT_XMC_LDI = 22, | |
93 | CVMX_L2C_EVENT_XMC_LDD = 23, | |
94 | CVMX_L2C_EVENT_XMC_STF = 24, | |
95 | CVMX_L2C_EVENT_XMC_STT = 25, | |
96 | CVMX_L2C_EVENT_XMC_STP = 26, | |
97 | CVMX_L2C_EVENT_XMC_STC = 27, | |
98 | CVMX_L2C_EVENT_XMC_DWB = 28, | |
99 | CVMX_L2C_EVENT_XMC_PL2 = 29, | |
100 | CVMX_L2C_EVENT_XMC_PSL1 = 30, | |
101 | CVMX_L2C_EVENT_XMC_IOBLD = 31, | |
102 | CVMX_L2C_EVENT_XMC_IOBST = 32, | |
103 | CVMX_L2C_EVENT_XMC_IOBDMA = 33, | |
104 | CVMX_L2C_EVENT_XMC_IOBRSP = 34, | |
105 | CVMX_L2C_EVENT_XMC_BUS_VALID = 35, | |
106 | CVMX_L2C_EVENT_XMC_MEM_DATA = 36, | |
107 | CVMX_L2C_EVENT_XMC_REFL_DATA = 37, | |
108 | CVMX_L2C_EVENT_XMC_IOBRSP_DATA = 38, | |
109 | CVMX_L2C_EVENT_RSC_NOP = 39, | |
110 | CVMX_L2C_EVENT_RSC_STDN = 40, | |
111 | CVMX_L2C_EVENT_RSC_FILL = 41, | |
112 | CVMX_L2C_EVENT_RSC_REFL = 42, | |
113 | CVMX_L2C_EVENT_RSC_STIN = 43, | |
114 | CVMX_L2C_EVENT_RSC_SCIN = 44, | |
115 | CVMX_L2C_EVENT_RSC_SCFL = 45, | |
116 | CVMX_L2C_EVENT_RSC_SCDN = 46, | |
117 | CVMX_L2C_EVENT_RSC_DATA_VALID = 47, | |
118 | CVMX_L2C_EVENT_RSC_VALID_FILL = 48, | |
119 | CVMX_L2C_EVENT_RSC_VALID_STRSP = 49, | |
120 | CVMX_L2C_EVENT_RSC_VALID_REFL = 50, | |
121 | CVMX_L2C_EVENT_LRF_REQ = 51, | |
122 | CVMX_L2C_EVENT_DT_RD_ALLOC = 52, | |
123 | CVMX_L2C_EVENT_DT_WR_INVAL = 53, | |
124 | CVMX_L2C_EVENT_MAX | |
125 | }; | |
126 | ||
127 | /* L2C Performance Counter events for Octeon2. */ | |
128 | enum cvmx_l2c_tad_event { | |
129 | CVMX_L2C_TAD_EVENT_NONE = 0, | |
130 | CVMX_L2C_TAD_EVENT_TAG_HIT = 1, | |
131 | CVMX_L2C_TAD_EVENT_TAG_MISS = 2, | |
132 | CVMX_L2C_TAD_EVENT_TAG_NOALLOC = 3, | |
133 | CVMX_L2C_TAD_EVENT_TAG_VICTIM = 4, | |
134 | CVMX_L2C_TAD_EVENT_SC_FAIL = 5, | |
135 | CVMX_L2C_TAD_EVENT_SC_PASS = 6, | |
136 | CVMX_L2C_TAD_EVENT_LFB_VALID = 7, | |
137 | CVMX_L2C_TAD_EVENT_LFB_WAIT_LFB = 8, | |
138 | CVMX_L2C_TAD_EVENT_LFB_WAIT_VAB = 9, | |
139 | CVMX_L2C_TAD_EVENT_QUAD0_INDEX = 128, | |
140 | CVMX_L2C_TAD_EVENT_QUAD0_READ = 129, | |
141 | CVMX_L2C_TAD_EVENT_QUAD0_BANK = 130, | |
142 | CVMX_L2C_TAD_EVENT_QUAD0_WDAT = 131, | |
143 | CVMX_L2C_TAD_EVENT_QUAD1_INDEX = 144, | |
144 | CVMX_L2C_TAD_EVENT_QUAD1_READ = 145, | |
145 | CVMX_L2C_TAD_EVENT_QUAD1_BANK = 146, | |
146 | CVMX_L2C_TAD_EVENT_QUAD1_WDAT = 147, | |
147 | CVMX_L2C_TAD_EVENT_QUAD2_INDEX = 160, | |
148 | CVMX_L2C_TAD_EVENT_QUAD2_READ = 161, | |
149 | CVMX_L2C_TAD_EVENT_QUAD2_BANK = 162, | |
150 | CVMX_L2C_TAD_EVENT_QUAD2_WDAT = 163, | |
151 | CVMX_L2C_TAD_EVENT_QUAD3_INDEX = 176, | |
152 | CVMX_L2C_TAD_EVENT_QUAD3_READ = 177, | |
153 | CVMX_L2C_TAD_EVENT_QUAD3_BANK = 178, | |
154 | CVMX_L2C_TAD_EVENT_QUAD3_WDAT = 179, | |
155 | CVMX_L2C_TAD_EVENT_MAX | |
58f07778 DD |
156 | }; |
157 | ||
158 | /** | |
159 | * Configure one of the four L2 Cache performance counters to capture event | |
25985edc | 160 | * occurrences. |
58f07778 DD |
161 | * |
162 | * @counter: The counter to configure. Range 0..3. | |
163 | * @event: The type of L2 Cache event occurrence to count. | |
164 | * @clear_on_read: When asserted, any read of the performance counter | |
165 | * clears the counter. | |
166 | * | |
b8db85b5 | 167 | * @note The routine does not clear the counter. |
58f07778 | 168 | */ |
b8db85b5 DD |
169 | void cvmx_l2c_config_perf(uint32_t counter, enum cvmx_l2c_event event, uint32_t clear_on_read); |
170 | ||
58f07778 DD |
171 | /** |
172 | * Read the given L2 Cache performance counter. The counter must be configured | |
173 | * before reading, but this routine does not enforce this requirement. | |
174 | * | |
175 | * @counter: The counter to configure. Range 0..3. | |
176 | * | |
177 | * Returns The current counter value. | |
178 | */ | |
179 | uint64_t cvmx_l2c_read_perf(uint32_t counter); | |
180 | ||
181 | /** | |
182 | * Return the L2 Cache way partitioning for a given core. | |
183 | * | |
184 | * @core: The core processor of interest. | |
185 | * | |
186 | * Returns The mask specifying the partitioning. 0 bits in mask indicates | |
187 | * the cache 'ways' that a core can evict from. | |
188 | * -1 on error | |
189 | */ | |
190 | int cvmx_l2c_get_core_way_partition(uint32_t core); | |
191 | ||
192 | /** | |
193 | * Partitions the L2 cache for a core | |
194 | * | |
b8db85b5 DD |
195 | * @core: The core that the partitioning applies to. |
196 | * @mask: The partitioning of the ways expressed as a binary | |
197 | * mask. A 0 bit allows the core to evict cache lines from | |
198 | * a way, while a 1 bit blocks the core from evicting any | |
199 | * lines from that way. There must be at least one allowed | |
200 | * way (0 bit) in the mask. | |
58f07778 | 201 | * |
b8db85b5 DD |
202 | |
203 | * @note If any ways are blocked for all cores and the HW blocks, then | |
204 | * those ways will never have any cache lines evicted from them. | |
205 | * All cores and the hardware blocks are free to read from all | |
206 | * ways regardless of the partitioning. | |
58f07778 DD |
207 | */ |
208 | int cvmx_l2c_set_core_way_partition(uint32_t core, uint32_t mask); | |
209 | ||
210 | /** | |
211 | * Return the L2 Cache way partitioning for the hw blocks. | |
212 | * | |
213 | * Returns The mask specifying the reserved way. 0 bits in mask indicates | |
214 | * the cache 'ways' that a core can evict from. | |
215 | * -1 on error | |
216 | */ | |
217 | int cvmx_l2c_get_hw_way_partition(void); | |
218 | ||
219 | /** | |
220 | * Partitions the L2 cache for the hardware blocks. | |
221 | * | |
b8db85b5 DD |
222 | * @mask: The partitioning of the ways expressed as a binary |
223 | * mask. A 0 bit allows the core to evict cache lines from | |
224 | * a way, while a 1 bit blocks the core from evicting any | |
225 | * lines from that way. There must be at least one allowed | |
226 | * way (0 bit) in the mask. | |
58f07778 | 227 | * |
b8db85b5 DD |
228 | |
229 | * @note If any ways are blocked for all cores and the HW blocks, then | |
230 | * those ways will never have any cache lines evicted from them. | |
231 | * All cores and the hardware blocks are free to read from all | |
232 | * ways regardless of the partitioning. | |
58f07778 DD |
233 | */ |
234 | int cvmx_l2c_set_hw_way_partition(uint32_t mask); | |
235 | ||
b8db85b5 | 236 | |
58f07778 DD |
237 | /** |
238 | * Locks a line in the L2 cache at the specified physical address | |
239 | * | |
240 | * @addr: physical address of line to lock | |
241 | * | |
242 | * Returns 0 on success, | |
243 | * 1 if line not locked. | |
244 | */ | |
245 | int cvmx_l2c_lock_line(uint64_t addr); | |
246 | ||
247 | /** | |
248 | * Locks a specified memory region in the L2 cache. | |
249 | * | |
250 | * Note that if not all lines can be locked, that means that all | |
251 | * but one of the ways (associations) available to the locking | |
252 | * core are locked. Having only 1 association available for | |
253 | * normal caching may have a significant adverse affect on performance. | |
254 | * Care should be taken to ensure that enough of the L2 cache is left | |
255 | * unlocked to allow for normal caching of DRAM. | |
256 | * | |
257 | * @start: Physical address of the start of the region to lock | |
258 | * @len: Length (in bytes) of region to lock | |
259 | * | |
260 | * Returns Number of requested lines that where not locked. | |
261 | * 0 on success (all locked) | |
262 | */ | |
263 | int cvmx_l2c_lock_mem_region(uint64_t start, uint64_t len); | |
264 | ||
265 | /** | |
266 | * Unlock and flush a cache line from the L2 cache. | |
267 | * IMPORTANT: Must only be run by one core at a time due to use | |
268 | * of L2C debug features. | |
269 | * Note that this function will flush a matching but unlocked cache line. | |
270 | * (If address is not in L2, no lines are flushed.) | |
271 | * | |
272 | * @address: Physical address to unlock | |
273 | * | |
274 | * Returns 0: line not unlocked | |
275 | * 1: line unlocked | |
276 | */ | |
277 | int cvmx_l2c_unlock_line(uint64_t address); | |
278 | ||
279 | /** | |
280 | * Unlocks a region of memory that is locked in the L2 cache | |
281 | * | |
282 | * @start: start physical address | |
283 | * @len: length (in bytes) to unlock | |
284 | * | |
285 | * Returns Number of locked lines that the call unlocked | |
286 | */ | |
287 | int cvmx_l2c_unlock_mem_region(uint64_t start, uint64_t len); | |
288 | ||
289 | /** | |
290 | * Read the L2 controller tag for a given location in L2 | |
291 | * | |
292 | * @association: | |
293 | * Which association to read line from | |
294 | * @index: Which way to read from. | |
295 | * | |
296 | * Returns l2c tag structure for line requested. | |
297 | */ | |
298 | union cvmx_l2c_tag cvmx_l2c_get_tag(uint32_t association, uint32_t index); | |
299 | ||
b8db85b5 DD |
300 | /* Wrapper providing a deprecated old function name */ |
301 | static inline union cvmx_l2c_tag cvmx_get_l2c_tag(uint32_t association, uint32_t index) __attribute__((deprecated)); | |
302 | static inline union cvmx_l2c_tag cvmx_get_l2c_tag(uint32_t association, uint32_t index) | |
58f07778 DD |
303 | { |
304 | return cvmx_l2c_get_tag(association, index); | |
305 | } | |
306 | ||
b8db85b5 | 307 | |
58f07778 DD |
308 | /** |
309 | * Returns the cache index for a given physical address | |
310 | * | |
311 | * @addr: physical address | |
312 | * | |
313 | * Returns L2 cache index | |
314 | */ | |
315 | uint32_t cvmx_l2c_address_to_index(uint64_t addr); | |
316 | ||
317 | /** | |
318 | * Flushes (and unlocks) the entire L2 cache. | |
319 | * IMPORTANT: Must only be run by one core at a time due to use | |
320 | * of L2C debug features. | |
321 | */ | |
322 | void cvmx_l2c_flush(void); | |
323 | ||
324 | /** | |
325 | * | |
326 | * Returns Returns the size of the L2 cache in bytes, | |
327 | * -1 on error (unrecognized model) | |
328 | */ | |
329 | int cvmx_l2c_get_cache_size_bytes(void); | |
330 | ||
331 | /** | |
332 | * Return the number of sets in the L2 Cache | |
333 | * | |
334 | * Returns | |
335 | */ | |
336 | int cvmx_l2c_get_num_sets(void); | |
337 | ||
338 | /** | |
339 | * Return log base 2 of the number of sets in the L2 cache | |
340 | * Returns | |
341 | */ | |
342 | int cvmx_l2c_get_set_bits(void); | |
343 | /** | |
344 | * Return the number of associations in the L2 Cache | |
345 | * | |
346 | * Returns | |
347 | */ | |
348 | int cvmx_l2c_get_num_assoc(void); | |
349 | ||
350 | /** | |
351 | * Flush a line from the L2 cache | |
352 | * This should only be called from one core at a time, as this routine | |
353 | * sets the core to the 'debug' core in order to flush the line. | |
354 | * | |
355 | * @assoc: Association (or way) to flush | |
356 | * @index: Index to flush | |
357 | */ | |
358 | void cvmx_l2c_flush_line(uint32_t assoc, uint32_t index); | |
359 | ||
360 | #endif /* __CVMX_L2C_H__ */ |