[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / mips / include / asm / mips-boards / generic.h

/*
 * Carsten Langgaard, carstenl@mips.com
 * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
 *
 * This program is free software; you can distribute it and/or modify it
 * under the terms of the GNU General Public License (Version 2) as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 * for more details.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, write to the Free Software Foundation, Inc.,
 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
 *
 * Defines of the MIPS boards specific address-MAP, registers, etc.
 */
#ifndef __ASM_MIPS_BOARDS_GENERIC_H
#define __ASM_MIPS_BOARDS_GENERIC_H

#include <asm/addrspace.h>
#include <asm/byteorder.h>
#include <asm/mips-boards/bonito64.h>

/*
 * Display register base.
 */
#define ASCII_DISPLAY_WORD_BASE    0x1f000410
#define ASCII_DISPLAY_POS_BASE     0x1f000418


/*
 * Yamon Prom print address.
 */
#define YAMON_PROM_PRINT_ADDR      0x1fc00504


/*
 * Reset register.
 */
#define SOFTRES_REG       0x1f000500
#define GORESET           0x42

/*
 * Revision register.
 */
#define MIPS_REVISION_REG                  0x1fc00010
#define MIPS_REVISION_CORID_QED_RM5261     0
#define MIPS_REVISION_CORID_CORE_LV        1
#define MIPS_REVISION_CORID_BONITO64       2
#define MIPS_REVISION_CORID_CORE_20K       3
#define MIPS_REVISION_CORID_CORE_FPGA      4
#define MIPS_REVISION_CORID_CORE_MSC       5
#define MIPS_REVISION_CORID_CORE_EMUL      6
#define MIPS_REVISION_CORID_CORE_FPGA2     7
#define MIPS_REVISION_CORID_CORE_FPGAR2    8
#define MIPS_REVISION_CORID_CORE_FPGA3     9
#define MIPS_REVISION_CORID_CORE_24K       10
#define MIPS_REVISION_CORID_CORE_FPGA4     11
#define MIPS_REVISION_CORID_CORE_FPGA5     12

/**** Artificial corid defines ****/
/*
 *  CoreEMUL with   Bonito   System Controller is treated like a Core20K
 *  CoreEMUL with SOC-it 101 System Controller is treated like a CoreMSC
 */
#define MIPS_REVISION_CORID_CORE_EMUL_BON  -1
#define MIPS_REVISION_CORID_CORE_EMUL_MSC  -2

#define MIPS_REVISION_CORID (((*(volatile u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 10) & 0x3f)

#define MIPS_REVISION_SCON_OTHER	   0
#define MIPS_REVISION_SCON_SOCITSC	   1
#define MIPS_REVISION_SCON_SOCITSCP	   2

/* Artificial SCON defines for MIPS_REVISION_SCON_OTHER */
#define MIPS_REVISION_SCON_UNKNOWN	   -1
#define MIPS_REVISION_SCON_GT64120	   -2
#define MIPS_REVISION_SCON_BONITO	   -3
#define MIPS_REVISION_SCON_BRTL		   -4
#define MIPS_REVISION_SCON_SOCIT	   -5
#define MIPS_REVISION_SCON_ROCIT	   -6

#define MIPS_REVISION_SCONID (((*(volatile u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 24) & 0xff)

extern int mips_revision_sconid;

#ifdef CONFIG_PCI
extern void mips_pcibios_init(void);
#else
#define mips_pcibios_init() do { } while (0)
#endif

#ifdef CONFIG_KGDB
extern void kgdb_config(void);
#endif

#endif  /* __ASM_MIPS_BOARDS_GENERIC_H */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Carsten Langgaard, carstenl@mips.com
	3	* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
	4	*
	5	* This program is free software; you can distribute it and/or modify it
	6	* under the terms of the GNU General Public License (Version 2) as
	7	* published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	12	* for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License along
	15	* with this program; if not, write to the Free Software Foundation, Inc.,
	16	* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
	17	*
	18	* Defines of the MIPS boards specific address-MAP, registers, etc.
	19	*/
	20	#ifndef __ASM_MIPS_BOARDS_GENERIC_H
	21	#define __ASM_MIPS_BOARDS_GENERIC_H
	22
1da177e4 LT	23	#include <asm/addrspace.h>
	24	#include <asm/byteorder.h>
	25	#include <asm/mips-boards/bonito64.h>
	26
	27	/*
	28	* Display register base.
	29	*/
1da177e4 LT	30	#define ASCII_DISPLAY_WORD_BASE 0x1f000410
1da177e4 LT	31	#define ASCII_DISPLAY_POS_BASE 0x1f000418
1da177e4 LT	32
	33
	34	/*
	35	* Yamon Prom print address.
	36	*/
	37	#define YAMON_PROM_PRINT_ADDR 0x1fc00504
	38
	39
	40	/*
	41	* Reset register.
	42	*/
1da177e4 LT	43	#define SOFTRES_REG 0x1f000500
1da177e4 LT	44	#define GORESET 0x42
1da177e4 LT	45
	46	/*
	47	* Revision register.
	48	*/
	49	#define MIPS_REVISION_REG 0x1fc00010
	50	#define MIPS_REVISION_CORID_QED_RM5261 0
	51	#define MIPS_REVISION_CORID_CORE_LV 1
	52	#define MIPS_REVISION_CORID_BONITO64 2
	53	#define MIPS_REVISION_CORID_CORE_20K 3
	54	#define MIPS_REVISION_CORID_CORE_FPGA 4
	55	#define MIPS_REVISION_CORID_CORE_MSC 5
	56	#define MIPS_REVISION_CORID_CORE_EMUL 6
	57	#define MIPS_REVISION_CORID_CORE_FPGA2 7
	58	#define MIPS_REVISION_CORID_CORE_FPGAR2 8
479a0e3e	59	#define MIPS_REVISION_CORID_CORE_FPGA3 9
7a834196	60	#define MIPS_REVISION_CORID_CORE_24K 10
a11b18ef	61	#define MIPS_REVISION_CORID_CORE_FPGA4 11
30840244	62	#define MIPS_REVISION_CORID_CORE_FPGA5 12
1da177e4 LT	63
	64	/** Artificial corid defines **/
	65	/*
	66	* CoreEMUL with Bonito System Controller is treated like a Core20K
	67	* CoreEMUL with SOC-it 101 System Controller is treated like a CoreMSC
	68	*/
b72c0526 CD	69	#define MIPS_REVISION_CORID_CORE_EMUL_BON -1
b72c0526 CD	70	#define MIPS_REVISION_CORID_CORE_EMUL_MSC -2
1da177e4 LT	71
	72	#define MIPS_REVISION_CORID ((((volatile u32 )ioremap(MIPS_REVISION_REG, 4)) >> 10) & 0x3f)
	73
b72c0526 CD	74	#define MIPS_REVISION_SCON_OTHER 0
	75	#define MIPS_REVISION_SCON_SOCITSC 1
	76	#define MIPS_REVISION_SCON_SOCITSCP 2
	77
	78	/* Artificial SCON defines for MIPS_REVISION_SCON_OTHER */
	79	#define MIPS_REVISION_SCON_UNKNOWN -1
	80	#define MIPS_REVISION_SCON_GT64120 -2
	81	#define MIPS_REVISION_SCON_BONITO -3
	82	#define MIPS_REVISION_SCON_BRTL -4
	83	#define MIPS_REVISION_SCON_SOCIT -5
	84	#define MIPS_REVISION_SCON_ROCIT -6
	85
	86	#define MIPS_REVISION_SCONID ((((volatile u32 )ioremap(MIPS_REVISION_REG, 4)) >> 24) & 0xff)
	87
	88	extern int mips_revision_sconid;
1da177e4	89
c83cfc9c RB	90	#ifdef CONFIG_PCI
	91	extern void mips_pcibios_init(void);
	92	#else
	93	#define mips_pcibios_init() do { } while (0)
	94	#endif
	95
bbdda5e1 DV	96	#ifdef CONFIG_KGDB
	97	extern void kgdb_config(void);
	98	#endif
	99
1da177e4	100	#endif /* __ASM_MIPS_BOARDS_GENERIC_H */