[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / mips / include / asm / inst.h

/*
 * Format of an instruction in memory.
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1996, 2000 by Ralf Baechle
 * Copyright (C) 2006 by Thiemo Seufer
 */
#ifndef _ASM_INST_H
#define _ASM_INST_H

/*
 * Major opcodes; before MIPS IV cop1x was called cop3.
 */
enum major_op {
	spec_op, bcond_op, j_op, jal_op,
	beq_op, bne_op, blez_op, bgtz_op,
	addi_op, addiu_op, slti_op, sltiu_op,
	andi_op, ori_op, xori_op, lui_op,
	cop0_op, cop1_op, cop2_op, cop1x_op,
	beql_op, bnel_op, blezl_op, bgtzl_op,
	daddi_op, daddiu_op, ldl_op, ldr_op,
	spec2_op, jalx_op, mdmx_op, spec3_op,
	lb_op, lh_op, lwl_op, lw_op,
	lbu_op, lhu_op, lwr_op, lwu_op,
	sb_op, sh_op, swl_op, sw_op,
	sdl_op, sdr_op, swr_op, cache_op,
	ll_op, lwc1_op, lwc2_op, pref_op,
	lld_op, ldc1_op, ldc2_op, ld_op,
	sc_op, swc1_op, swc2_op, major_3b_op,
	scd_op, sdc1_op, sdc2_op, sd_op
};

/*
 * func field of spec opcode.
 */
enum spec_op {
	sll_op, movc_op, srl_op, sra_op,
	sllv_op, pmon_op, srlv_op, srav_op,
	jr_op, jalr_op, movz_op, movn_op,
	syscall_op, break_op, spim_op, sync_op,
	mfhi_op, mthi_op, mflo_op, mtlo_op,
	dsllv_op, spec2_unused_op, dsrlv_op, dsrav_op,
	mult_op, multu_op, div_op, divu_op,
	dmult_op, dmultu_op, ddiv_op, ddivu_op,
	add_op, addu_op, sub_op, subu_op,
	and_op, or_op, xor_op, nor_op,
	spec3_unused_op, spec4_unused_op, slt_op, sltu_op,
	dadd_op, daddu_op, dsub_op, dsubu_op,
	tge_op, tgeu_op, tlt_op, tltu_op,
	teq_op, spec5_unused_op, tne_op, spec6_unused_op,
	dsll_op, spec7_unused_op, dsrl_op, dsra_op,
	dsll32_op, spec8_unused_op, dsrl32_op, dsra32_op
};

/*
 * func field of spec2 opcode.
 */
enum spec2_op {
	madd_op, maddu_op, mul_op, spec2_3_unused_op,
	msub_op, msubu_op, /* more unused ops */
	clz_op = 0x20, clo_op,
	dclz_op = 0x24, dclo_op,
	sdbpp_op = 0x3f
};

/*
 * func field of spec3 opcode.
 */
enum spec3_op {
	ext_op, dextm_op, dextu_op, dext_op,
	ins_op, dinsm_op, dinsu_op, dins_op,
	lx_op = 0x0a,
	bshfl_op = 0x20,
	dbshfl_op = 0x24,
	rdhwr_op = 0x3b
};

/*
 * rt field of bcond opcodes.
 */
enum rt_op {
	bltz_op, bgez_op, bltzl_op, bgezl_op,
	spimi_op, unused_rt_op_0x05, unused_rt_op_0x06, unused_rt_op_0x07,
	tgei_op, tgeiu_op, tlti_op, tltiu_op,
	teqi_op, unused_0x0d_rt_op, tnei_op, unused_0x0f_rt_op,
	bltzal_op, bgezal_op, bltzall_op, bgezall_op,
	rt_op_0x14, rt_op_0x15, rt_op_0x16, rt_op_0x17,
	rt_op_0x18, rt_op_0x19, rt_op_0x1a, rt_op_0x1b,
	bposge32_op, rt_op_0x1d, rt_op_0x1e, rt_op_0x1f
};

/*
 * rs field of cop opcodes.
 */
enum cop_op {
	mfc_op        = 0x00, dmfc_op       = 0x01,
	cfc_op        = 0x02, mtc_op        = 0x04,
	dmtc_op       = 0x05, ctc_op        = 0x06,
	bc_op         = 0x08, cop_op        = 0x10,
	copm_op       = 0x18
};

/*
 * rt field of cop.bc_op opcodes
 */
enum bcop_op {
	bcf_op, bct_op, bcfl_op, bctl_op
};

/*
 * func field of cop0 coi opcodes.
 */
enum cop0_coi_func {
	tlbr_op       = 0x01, tlbwi_op      = 0x02,
	tlbwr_op      = 0x06, tlbp_op       = 0x08,
	rfe_op        = 0x10, eret_op       = 0x18
};

/*
 * func field of cop0 com opcodes.
 */
enum cop0_com_func {
	tlbr1_op      = 0x01, tlbw_op       = 0x02,
	tlbp1_op      = 0x08, dctr_op       = 0x09,
	dctw_op       = 0x0a
};

/*
 * fmt field of cop1 opcodes.
 */
enum cop1_fmt {
	s_fmt, d_fmt, e_fmt, q_fmt,
	w_fmt, l_fmt
};

/*
 * func field of cop1 instructions using d, s or w format.
 */
enum cop1_sdw_func {
	fadd_op      =  0x00, fsub_op      =  0x01,
	fmul_op      =  0x02, fdiv_op      =  0x03,
	fsqrt_op     =  0x04, fabs_op      =  0x05,
	fmov_op      =  0x06, fneg_op      =  0x07,
	froundl_op   =  0x08, ftruncl_op   =  0x09,
	fceill_op    =  0x0a, ffloorl_op   =  0x0b,
	fround_op    =  0x0c, ftrunc_op    =  0x0d,
	fceil_op     =  0x0e, ffloor_op    =  0x0f,
	fmovc_op     =  0x11, fmovz_op     =  0x12,
	fmovn_op     =  0x13, frecip_op    =  0x15,
	frsqrt_op    =  0x16, fcvts_op     =  0x20,
	fcvtd_op     =  0x21, fcvte_op     =  0x22,
	fcvtw_op     =  0x24, fcvtl_op     =  0x25,
	fcmp_op      =  0x30
};

/*
 * func field of cop1x opcodes (MIPS IV).
 */
enum cop1x_func {
	lwxc1_op     =  0x00, ldxc1_op     =  0x01,
	pfetch_op    =  0x07, swxc1_op     =  0x08,
	sdxc1_op     =  0x09, madd_s_op    =  0x20,
	madd_d_op    =  0x21, madd_e_op    =  0x22,
	msub_s_op    =  0x28, msub_d_op    =  0x29,
	msub_e_op    =  0x2a, nmadd_s_op   =  0x30,
	nmadd_d_op   =  0x31, nmadd_e_op   =  0x32,
	nmsub_s_op   =  0x38, nmsub_d_op   =  0x39,
	nmsub_e_op   =  0x3a
};

/*
 * func field for mad opcodes (MIPS IV).
 */
enum mad_func {
	madd_fp_op      = 0x08, msub_fp_op      = 0x0a,
	nmadd_fp_op     = 0x0c, nmsub_fp_op     = 0x0e
};

/*
 * func field for special3 lx opcodes (Cavium Octeon).
 */
enum lx_func {
	lwx_op	= 0x00,
	lhx_op	= 0x04,
	lbux_op	= 0x06,
	ldx_op	= 0x08,
	lwux_op	= 0x10,
	lhux_op	= 0x14,
	lbx_op	= 0x16,
};

/*
 * Damn ...  bitfields depend from byteorder :-(
 */
#ifdef __MIPSEB__
struct j_format {	/* Jump format */
	unsigned int opcode : 6;
	unsigned int target : 26;
};

struct i_format {	/* Immediate format (addi, lw, ...) */
	unsigned int opcode : 6;
	unsigned int rs : 5;
	unsigned int rt : 5;
	signed int simmediate : 16;
};

struct u_format {	/* Unsigned immediate format (ori, xori, ...) */
	unsigned int opcode : 6;
	unsigned int rs : 5;
	unsigned int rt : 5;
	unsigned int uimmediate : 16;
};

struct c_format {	/* Cache (>= R6000) format */
	unsigned int opcode : 6;
	unsigned int rs : 5;
	unsigned int c_op : 3;
	unsigned int cache : 2;
	unsigned int simmediate : 16;
};

struct r_format {	/* Register format */
	unsigned int opcode : 6;
	unsigned int rs : 5;
	unsigned int rt : 5;
	unsigned int rd : 5;
	unsigned int re : 5;
	unsigned int func : 6;
};

struct p_format {	/* Performance counter format (R10000) */
	unsigned int opcode : 6;
	unsigned int rs : 5;
	unsigned int rt : 5;
	unsigned int rd : 5;
	unsigned int re : 5;
	unsigned int func : 6;
};

struct f_format {	/* FPU register format */
	unsigned int opcode : 6;
	unsigned int : 1;
	unsigned int fmt : 4;
	unsigned int rt : 5;
	unsigned int rd : 5;
	unsigned int re : 5;
	unsigned int func : 6;
};

struct ma_format {	/* FPU multiply and add format (MIPS IV) */
	unsigned int opcode : 6;
	unsigned int fr : 5;
	unsigned int ft : 5;
	unsigned int fs : 5;
	unsigned int fd : 5;
	unsigned int func : 4;
	unsigned int fmt : 2;
};

struct b_format { /* BREAK and SYSCALL */
	unsigned int opcode:6;
	unsigned int code:20;
	unsigned int func:6;
};

#elif defined(__MIPSEL__)

struct j_format {	/* Jump format */
	unsigned int target : 26;
	unsigned int opcode : 6;
};

struct i_format {	/* Immediate format */
	signed int simmediate : 16;
	unsigned int rt : 5;
	unsigned int rs : 5;
	unsigned int opcode : 6;
};

struct u_format {	/* Unsigned immediate format */
	unsigned int uimmediate : 16;
	unsigned int rt : 5;
	unsigned int rs : 5;
	unsigned int opcode : 6;
};

struct c_format {	/* Cache (>= R6000) format */
	unsigned int simmediate : 16;
	unsigned int cache : 2;
	unsigned int c_op : 3;
	unsigned int rs : 5;
	unsigned int opcode : 6;
};

struct r_format {	/* Register format */
	unsigned int func : 6;
	unsigned int re : 5;
	unsigned int rd : 5;
	unsigned int rt : 5;
	unsigned int rs : 5;
	unsigned int opcode : 6;
};

struct p_format {	/* Performance counter format (R10000) */
	unsigned int func : 6;
	unsigned int re : 5;
	unsigned int rd : 5;
	unsigned int rt : 5;
	unsigned int rs : 5;
	unsigned int opcode : 6;
};

struct f_format {	/* FPU register format */
	unsigned int func : 6;
	unsigned int re : 5;
	unsigned int rd : 5;
	unsigned int rt : 5;
	unsigned int fmt : 4;
	unsigned int : 1;
	unsigned int opcode : 6;
};

struct ma_format {	/* FPU multiply and add format (MIPS IV) */
	unsigned int fmt : 2;
	unsigned int func : 4;
	unsigned int fd : 5;
	unsigned int fs : 5;
	unsigned int ft : 5;
	unsigned int fr : 5;
	unsigned int opcode : 6;
};

struct b_format { /* BREAK and SYSCALL */
	unsigned int func:6;
	unsigned int code:20;
	unsigned int opcode:6;
};

#else /* !defined (__MIPSEB__) && !defined (__MIPSEL__) */
#error "MIPS but neither __MIPSEL__ nor __MIPSEB__?"
#endif

union mips_instruction {
	unsigned int word;
	unsigned short halfword[2];
	unsigned char byte[4];
	struct j_format j_format;
	struct i_format i_format;
	struct u_format u_format;
	struct c_format c_format;
	struct r_format r_format;
	struct p_format p_format;
	struct f_format f_format;
	struct ma_format ma_format;
	struct b_format b_format;
};

/* HACHACHAHCAHC ...  */

/* In case some other massaging is needed, keep MIPSInst as wrapper */

#define MIPSInst(x) x

#define I_OPCODE_SFT	26
#define MIPSInst_OPCODE(x) (MIPSInst(x) >> I_OPCODE_SFT)

#define I_JTARGET_SFT	0
#define MIPSInst_JTARGET(x) (MIPSInst(x) & 0x03ffffff)

#define I_RS_SFT	21
#define MIPSInst_RS(x) ((MIPSInst(x) & 0x03e00000) >> I_RS_SFT)

#define I_RT_SFT	16
#define MIPSInst_RT(x) ((MIPSInst(x) & 0x001f0000) >> I_RT_SFT)

#define I_IMM_SFT	0
#define MIPSInst_SIMM(x) ((int)((short)(MIPSInst(x) & 0xffff)))
#define MIPSInst_UIMM(x) (MIPSInst(x) & 0xffff)

#define I_CACHEOP_SFT	18
#define MIPSInst_CACHEOP(x) ((MIPSInst(x) & 0x001c0000) >> I_CACHEOP_SFT)

#define I_CACHESEL_SFT	16
#define MIPSInst_CACHESEL(x) ((MIPSInst(x) & 0x00030000) >> I_CACHESEL_SFT)

#define I_RD_SFT	11
#define MIPSInst_RD(x) ((MIPSInst(x) & 0x0000f800) >> I_RD_SFT)

#define I_RE_SFT	6
#define MIPSInst_RE(x) ((MIPSInst(x) & 0x000007c0) >> I_RE_SFT)

#define I_FUNC_SFT	0
#define MIPSInst_FUNC(x) (MIPSInst(x) & 0x0000003f)

#define I_FFMT_SFT	21
#define MIPSInst_FFMT(x) ((MIPSInst(x) & 0x01e00000) >> I_FFMT_SFT)

#define I_FT_SFT	16
#define MIPSInst_FT(x) ((MIPSInst(x) & 0x001f0000) >> I_FT_SFT)

#define I_FS_SFT	11
#define MIPSInst_FS(x) ((MIPSInst(x) & 0x0000f800) >> I_FS_SFT)

#define I_FD_SFT	6
#define MIPSInst_FD(x) ((MIPSInst(x) & 0x000007c0) >> I_FD_SFT)

#define I_FR_SFT	21
#define MIPSInst_FR(x) ((MIPSInst(x) & 0x03e00000) >> I_FR_SFT)

#define I_FMA_FUNC_SFT	2
#define MIPSInst_FMA_FUNC(x) ((MIPSInst(x) & 0x0000003c) >> I_FMA_FUNC_SFT)

#define I_FMA_FFMT_SFT	0
#define MIPSInst_FMA_FFMT(x) (MIPSInst(x) & 0x00000003)

typedef unsigned int mips_instruction;

#endif /* _ASM_INST_H */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Format of an instruction in memory.
	3	*
	4	* This file is subject to the terms and conditions of the GNU General Public
	5	* License. See the file "COPYING" in the main directory of this archive
	6	* for more details.
	7	*
	8	* Copyright (C) 1996, 2000 by Ralf Baechle
ca30225e	9	* Copyright (C) 2006 by Thiemo Seufer
1da177e4 LT	10	*/
	11	#ifndef _ASM_INST_H
	12	#define _ASM_INST_H
	13
	14	/*
	15	* Major opcodes; before MIPS IV cop1x was called cop3.
	16	*/
	17	enum major_op {
	18	spec_op, bcond_op, j_op, jal_op,
	19	beq_op, bne_op, blez_op, bgtz_op,
	20	addi_op, addiu_op, slti_op, sltiu_op,
	21	andi_op, ori_op, xori_op, lui_op,
	22	cop0_op, cop1_op, cop2_op, cop1x_op,
	23	beql_op, bnel_op, blezl_op, bgtzl_op,
	24	daddi_op, daddiu_op, ldl_op, ldr_op,
ca30225e	25	spec2_op, jalx_op, mdmx_op, spec3_op,
1da177e4 LT	26	lb_op, lh_op, lwl_op, lw_op,
	27	lbu_op, lhu_op, lwr_op, lwu_op,
	28	sb_op, sh_op, swl_op, sw_op,
	29	sdl_op, sdr_op, swr_op, cache_op,
	30	ll_op, lwc1_op, lwc2_op, pref_op,
	31	lld_op, ldc1_op, ldc2_op, ld_op,
ca30225e	32	sc_op, swc1_op, swc2_op, major_3b_op,
1da177e4 LT	33	scd_op, sdc1_op, sdc2_op, sd_op
	34	};
	35
	36	/*
	37	* func field of spec opcode.
	38	*/
	39	enum spec_op {
	40	sll_op, movc_op, srl_op, sra_op,
ca30225e	41	sllv_op, pmon_op, srlv_op, srav_op,
1da177e4 LT	42	jr_op, jalr_op, movz_op, movn_op,
	43	syscall_op, break_op, spim_op, sync_op,
	44	mfhi_op, mthi_op, mflo_op, mtlo_op,
	45	dsllv_op, spec2_unused_op, dsrlv_op, dsrav_op,
	46	mult_op, multu_op, div_op, divu_op,
	47	dmult_op, dmultu_op, ddiv_op, ddivu_op,
	48	add_op, addu_op, sub_op, subu_op,
	49	and_op, or_op, xor_op, nor_op,
	50	spec3_unused_op, spec4_unused_op, slt_op, sltu_op,
	51	dadd_op, daddu_op, dsub_op, dsubu_op,
	52	tge_op, tgeu_op, tlt_op, tltu_op,
	53	teq_op, spec5_unused_op, tne_op, spec6_unused_op,
	54	dsll_op, spec7_unused_op, dsrl_op, dsra_op,
	55	dsll32_op, spec8_unused_op, dsrl32_op, dsra32_op
	56	};
	57
ca30225e TS	58	/*
	59	* func field of spec2 opcode.
	60	*/
	61	enum spec2_op {
	62	madd_op, maddu_op, mul_op, spec2_3_unused_op,
	63	msub_op, msubu_op, /* more unused ops */
	64	clz_op = 0x20, clo_op,
	65	dclz_op = 0x24, dclo_op,
	66	sdbpp_op = 0x3f
	67	};
	68
	69	/*
	70	* func field of spec3 opcode.
	71	*/
	72	enum spec3_op {
	73	ext_op, dextm_op, dextu_op, dext_op,
	74	ins_op, dinsm_op, dinsu_op, dins_op,
bb3d68c3	75	lx_op = 0x0a,
ca30225e TS	76	bshfl_op = 0x20,
ca30225e TS	77	dbshfl_op = 0x24,
8d197f3d	78	rdhwr_op = 0x3b
ca30225e TS	79	};
ca30225e TS	80
1da177e4 LT	81	/*
	82	* rt field of bcond opcodes.
	83	*/
	84	enum rt_op {
	85	bltz_op, bgez_op, bltzl_op, bgezl_op,
	86	spimi_op, unused_rt_op_0x05, unused_rt_op_0x06, unused_rt_op_0x07,
	87	tgei_op, tgeiu_op, tlti_op, tltiu_op,
	88	teqi_op, unused_0x0d_rt_op, tnei_op, unused_0x0f_rt_op,
e50c0a8f RB	89	bltzal_op, bgezal_op, bltzall_op, bgezall_op,
	90	rt_op_0x14, rt_op_0x15, rt_op_0x16, rt_op_0x17,
	91	rt_op_0x18, rt_op_0x19, rt_op_0x1a, rt_op_0x1b,
	92	bposge32_op, rt_op_0x1d, rt_op_0x1e, rt_op_0x1f
1da177e4 LT	93	};
	94
	95	/*
	96	* rs field of cop opcodes.
	97	*/
	98	enum cop_op {
	99	mfc_op = 0x00, dmfc_op = 0x01,
	100	cfc_op = 0x02, mtc_op = 0x04,
	101	dmtc_op = 0x05, ctc_op = 0x06,
	102	bc_op = 0x08, cop_op = 0x10,
	103	copm_op = 0x18
	104	};
	105
	106	/*
	107	* rt field of cop.bc_op opcodes
	108	*/
	109	enum bcop_op {
	110	bcf_op, bct_op, bcfl_op, bctl_op
	111	};
	112
	113	/*
	114	* func field of cop0 coi opcodes.
	115	*/
	116	enum cop0_coi_func {
	117	tlbr_op = 0x01, tlbwi_op = 0x02,
	118	tlbwr_op = 0x06, tlbp_op = 0x08,
	119	rfe_op = 0x10, eret_op = 0x18
	120	};
	121
	122	/*
	123	* func field of cop0 com opcodes.
	124	*/
	125	enum cop0_com_func {
	126	tlbr1_op = 0x01, tlbw_op = 0x02,
	127	tlbp1_op = 0x08, dctr_op = 0x09,
	128	dctw_op = 0x0a
	129	};
	130
	131	/*
	132	* fmt field of cop1 opcodes.
	133	*/
	134	enum cop1_fmt {
	135	s_fmt, d_fmt, e_fmt, q_fmt,
	136	w_fmt, l_fmt
	137	};
	138
	139	/*
	140	* func field of cop1 instructions using d, s or w format.
	141	*/
	142	enum cop1_sdw_func {
	143	fadd_op = 0x00, fsub_op = 0x01,
	144	fmul_op = 0x02, fdiv_op = 0x03,
	145	fsqrt_op = 0x04, fabs_op = 0x05,
	146	fmov_op = 0x06, fneg_op = 0x07,
	147	froundl_op = 0x08, ftruncl_op = 0x09,
	148	fceill_op = 0x0a, ffloorl_op = 0x0b,
	149	fround_op = 0x0c, ftrunc_op = 0x0d,
	150	fceil_op = 0x0e, ffloor_op = 0x0f,
	151	fmovc_op = 0x11, fmovz_op = 0x12,
	152	fmovn_op = 0x13, frecip_op = 0x15,
	153	frsqrt_op = 0x16, fcvts_op = 0x20,
	154	fcvtd_op = 0x21, fcvte_op = 0x22,
	155	fcvtw_op = 0x24, fcvtl_op = 0x25,
	156	fcmp_op = 0x30
157	};
158
159	/*
160	* func field of cop1x opcodes (MIPS IV).
161	*/
162	enum cop1x_func {
163	lwxc1_op = 0x00, ldxc1_op = 0x01,
164	pfetch_op = 0x07, swxc1_op = 0x08,
165	sdxc1_op = 0x09, madd_s_op = 0x20,
166	madd_d_op = 0x21, madd_e_op = 0x22,
167	msub_s_op = 0x28, msub_d_op = 0x29,
168	msub_e_op = 0x2a, nmadd_s_op = 0x30,
169	nmadd_d_op = 0x31, nmadd_e_op = 0x32,
170	nmsub_s_op = 0x38, nmsub_d_op = 0x39,
171	nmsub_e_op = 0x3a
172	};
173
174	/*
175	* func field for mad opcodes (MIPS IV).
176	*/
177	enum mad_func {
ca30225e TS	178	madd_fp_op = 0x08, msub_fp_op = 0x0a,
ca30225e TS	179	nmadd_fp_op = 0x0c, nmsub_fp_op = 0x0e
1da177e4 LT	180	};
1da177e4 LT	181
bb3d68c3 DD	182	/*
	183	* func field for special3 lx opcodes (Cavium Octeon).
	184	*/
	185	enum lx_func {
	186	lwx_op = 0x00,
	187	lhx_op = 0x04,
	188	lbux_op = 0x06,
	189	ldx_op = 0x08,
	190	lwux_op = 0x10,
	191	lhux_op = 0x14,
	192	lbx_op = 0x16,
	193	};
	194
1da177e4 LT	195	/*
	196	* Damn ... bitfields depend from byteorder :-(
	197	*/
	198	#ifdef __MIPSEB__
	199	struct j_format { /* Jump format */
	200	unsigned int opcode : 6;
	201	unsigned int target : 26;
	202	};
	203
	204	struct i_format { /* Immediate format (addi, lw, ...) */
	205	unsigned int opcode : 6;
	206	unsigned int rs : 5;
	207	unsigned int rt : 5;
	208	signed int simmediate : 16;
	209	};
	210
	211	struct u_format { /* Unsigned immediate format (ori, xori, ...) */
	212	unsigned int opcode : 6;
	213	unsigned int rs : 5;
	214	unsigned int rt : 5;
	215	unsigned int uimmediate : 16;
	216	};
	217
	218	struct c_format { /* Cache (>= R6000) format */
	219	unsigned int opcode : 6;
	220	unsigned int rs : 5;
	221	unsigned int c_op : 3;
	222	unsigned int cache : 2;
	223	unsigned int simmediate : 16;
	224	};
	225
	226	struct r_format { /* Register format */
	227	unsigned int opcode : 6;
	228	unsigned int rs : 5;
	229	unsigned int rt : 5;
	230	unsigned int rd : 5;
	231	unsigned int re : 5;
	232	unsigned int func : 6;
	233	};
	234
	235	struct p_format { /* Performance counter format (R10000) */
	236	unsigned int opcode : 6;
	237	unsigned int rs : 5;
	238	unsigned int rt : 5;
	239	unsigned int rd : 5;
	240	unsigned int re : 5;
	241	unsigned int func : 6;
	242	};
	243
	244	struct f_format { /* FPU register format */
	245	unsigned int opcode : 6;
	246	unsigned int : 1;
	247	unsigned int fmt : 4;
	248	unsigned int rt : 5;
	249	unsigned int rd : 5;
	250	unsigned int re : 5;
	251	unsigned int func : 6;
	252	};
	253
a586e14f	254	struct ma_format { /* FPU multiply and add format (MIPS IV) */
1da177e4 LT	255	unsigned int opcode : 6;
	256	unsigned int fr : 5;
	257	unsigned int ft : 5;
	258	unsigned int fs : 5;
	259	unsigned int fd : 5;
	260	unsigned int func : 4;
	261	unsigned int fmt : 2;
	262	};
	263
2ea6399f DD	264	struct b_format { /* BREAK and SYSCALL */
	265	unsigned int opcode:6;
	266	unsigned int code:20;
	267	unsigned int func:6;
	268	};
	269
1da177e4 LT	270	#elif defined(__MIPSEL__)
	271
	272	struct j_format { /* Jump format */
	273	unsigned int target : 26;
	274	unsigned int opcode : 6;
	275	};
	276
	277	struct i_format { /* Immediate format */
	278	signed int simmediate : 16;
	279	unsigned int rt : 5;
	280	unsigned int rs : 5;
	281	unsigned int opcode : 6;
	282	};
	283
	284	struct u_format { /* Unsigned immediate format */
	285	unsigned int uimmediate : 16;
	286	unsigned int rt : 5;
	287	unsigned int rs : 5;
	288	unsigned int opcode : 6;
	289	};
	290
	291	struct c_format { /* Cache (>= R6000) format */
	292	unsigned int simmediate : 16;
	293	unsigned int cache : 2;
	294	unsigned int c_op : 3;
	295	unsigned int rs : 5;
	296	unsigned int opcode : 6;
	297	};
	298
	299	struct r_format { /* Register format */
	300	unsigned int func : 6;
	301	unsigned int re : 5;
	302	unsigned int rd : 5;
	303	unsigned int rt : 5;
	304	unsigned int rs : 5;
	305	unsigned int opcode : 6;
	306	};
	307
	308	struct p_format { /* Performance counter format (R10000) */
	309	unsigned int func : 6;
	310	unsigned int re : 5;
	311	unsigned int rd : 5;
	312	unsigned int rt : 5;
	313	unsigned int rs : 5;
	314	unsigned int opcode : 6;
	315	};
	316
	317	struct f_format { /* FPU register format */
	318	unsigned int func : 6;
	319	unsigned int re : 5;
	320	unsigned int rd : 5;
	321	unsigned int rt : 5;
	322	unsigned int fmt : 4;
	323	unsigned int : 1;
	324	unsigned int opcode : 6;
	325	};
	326
a586e14f	327	struct ma_format { /* FPU multiply and add format (MIPS IV) */
1da177e4 LT	328	unsigned int fmt : 2;
	329	unsigned int func : 4;
	330	unsigned int fd : 5;
	331	unsigned int fs : 5;
	332	unsigned int ft : 5;
	333	unsigned int fr : 5;
	334	unsigned int opcode : 6;
	335	};
	336
2ea6399f DD	337	struct b_format { /* BREAK and SYSCALL */
	338	unsigned int func:6;
	339	unsigned int code:20;
	340	unsigned int opcode:6;
	341	};
	342
1da177e4 LT	343	#else /* !defined (__MIPSEB__) && !defined (__MIPSEL__) */
	344	#error "MIPS but neither __MIPSEL__ nor __MIPSEB__?"
	345	#endif
	346
	347	union mips_instruction {
	348	unsigned int word;
	349	unsigned short halfword[2];
	350	unsigned char byte[4];
	351	struct j_format j_format;
	352	struct i_format i_format;
	353	struct u_format u_format;
	354	struct c_format c_format;
	355	struct r_format r_format;
9561fefc	356	struct p_format p_format;
1da177e4	357	struct f_format f_format;
2ea6399f DD	358	struct ma_format ma_format;
2ea6399f DD	359	struct b_format b_format;
1da177e4 LT	360	};
	361
	362	/* HACHACHAHCAHC ... */
	363
	364	/* In case some other massaging is needed, keep MIPSInst as wrapper */
	365
	366	#define MIPSInst(x) x
	367
	368	#define I_OPCODE_SFT 26
	369	#define MIPSInst_OPCODE(x) (MIPSInst(x) >> I_OPCODE_SFT)
	370
	371	#define I_JTARGET_SFT 0
	372	#define MIPSInst_JTARGET(x) (MIPSInst(x) & 0x03ffffff)
	373
	374	#define I_RS_SFT 21
	375	#define MIPSInst_RS(x) ((MIPSInst(x) & 0x03e00000) >> I_RS_SFT)
	376
	377	#define I_RT_SFT 16
	378	#define MIPSInst_RT(x) ((MIPSInst(x) & 0x001f0000) >> I_RT_SFT)
	379
	380	#define I_IMM_SFT 0
	381	#define MIPSInst_SIMM(x) ((int)((short)(MIPSInst(x) & 0xffff)))
	382	#define MIPSInst_UIMM(x) (MIPSInst(x) & 0xffff)
	383
	384	#define I_CACHEOP_SFT 18
	385	#define MIPSInst_CACHEOP(x) ((MIPSInst(x) & 0x001c0000) >> I_CACHEOP_SFT)
	386
	387	#define I_CACHESEL_SFT 16
	388	#define MIPSInst_CACHESEL(x) ((MIPSInst(x) & 0x00030000) >> I_CACHESEL_SFT)
	389
	390	#define I_RD_SFT 11
	391	#define MIPSInst_RD(x) ((MIPSInst(x) & 0x0000f800) >> I_RD_SFT)
	392
	393	#define I_RE_SFT 6
	394	#define MIPSInst_RE(x) ((MIPSInst(x) & 0x000007c0) >> I_RE_SFT)
	395
	396	#define I_FUNC_SFT 0
	397	#define MIPSInst_FUNC(x) (MIPSInst(x) & 0x0000003f)
	398
	399	#define I_FFMT_SFT 21
	400	#define MIPSInst_FFMT(x) ((MIPSInst(x) & 0x01e00000) >> I_FFMT_SFT)
	401
	402	#define I_FT_SFT 16
	403	#define MIPSInst_FT(x) ((MIPSInst(x) & 0x001f0000) >> I_FT_SFT)
	404
	405	#define I_FS_SFT 11
	406	#define MIPSInst_FS(x) ((MIPSInst(x) & 0x0000f800) >> I_FS_SFT)
	407
	408	#define I_FD_SFT 6
	409	#define MIPSInst_FD(x) ((MIPSInst(x) & 0x000007c0) >> I_FD_SFT)
	410
	411	#define I_FR_SFT 21
	412	#define MIPSInst_FR(x) ((MIPSInst(x) & 0x03e00000) >> I_FR_SFT)
	413
	414	#define I_FMA_FUNC_SFT 2
	415	#define MIPSInst_FMA_FUNC(x) ((MIPSInst(x) & 0x0000003c) >> I_FMA_FUNC_SFT)
	416
	417	#define I_FMA_FFMT_SFT 0
	418	#define MIPSInst_FMA_FFMT(x) (MIPSInst(x) & 0x00000003)
	419
	420	typedef unsigned int mips_instruction;
	421
	422	#endif /* _ASM_INST_H */