projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
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|---|---|---|
| 1da177e4 LT |
1 | /* |
| 2 | * This file is subject to the terms and conditions of the GNU General Public | |
| 3 | * License. See the file "COPYING" in the main directory of this archive | |
| 4 | * for more details. | |
| 5 | * | |
| 6 | * Copyright (C) 2003 Ralf Baechle | |
| 7 | */ | |
| 8 | #ifndef _ASM_ASMMACRO_H | |
| 9 | #define _ASM_ASMMACRO_H | |
| 42a3b4f2 | 10 | |
| 1da177e4 | 11 | #include <asm/hazards.h> |
| 42a3b4f2 | 12 | |
| 875d43e7 | 13 | #ifdef CONFIG_32BIT |
| 1da177e4 LT |
14 | #include <asm/asmmacro-32.h> |
| 15 | #endif | |
| 875d43e7 | 16 | #ifdef CONFIG_64BIT |
| 1da177e4 LT |
17 | #include <asm/asmmacro-64.h> |
| 18 | #endif | |
| 41c594ab RB |
19 | #ifdef CONFIG_MIPS_MT_SMTC |
| 20 | #include <asm/mipsmtregs.h> | |
| 21 | #endif | |
| 1da177e4 | 22 | |
| 41c594ab RB |
23 | #ifdef CONFIG_MIPS_MT_SMTC |
| 24 | .macro local_irq_enable reg=t0 | |
| 25 | mfc0 \reg, CP0_TCSTATUS | |
| 26 | ori \reg, \reg, TCSTATUS_IXMT | |
| 27 | xori \reg, \reg, TCSTATUS_IXMT | |
| 28 | mtc0 \reg, CP0_TCSTATUS | |
| 4277ff5e | 29 | _ehb |
| 41c594ab RB |
30 | .endm |
| 31 | ||
| 32 | .macro local_irq_disable reg=t0 | |
| 33 | mfc0 \reg, CP0_TCSTATUS | |
| 34 | ori \reg, \reg, TCSTATUS_IXMT | |
| 35 | mtc0 \reg, CP0_TCSTATUS | |
| 4277ff5e | 36 | _ehb |
| 41c594ab | 37 | .endm |
| b6354db5 DD |
38 | #elif defined(CONFIG_CPU_MIPSR2) |
| 39 | .macro local_irq_enable reg=t0 | |
| 40 | ei | |
| 41 | irq_enable_hazard | |
| 42 | .endm | |
| 43 | ||
| 44 | .macro local_irq_disable reg=t0 | |
| 45 | di | |
| 46 | irq_disable_hazard | |
| 47 | .endm | |
| 41c594ab | 48 | #else |
| 1da177e4 LT |
49 | .macro local_irq_enable reg=t0 |
| 50 | mfc0 \reg, CP0_STATUS | |
| 51 | ori \reg, \reg, 1 | |
| 52 | mtc0 \reg, CP0_STATUS | |
| 53 | irq_enable_hazard | |
| 54 | .endm | |
| 55 | ||
| 56 | .macro local_irq_disable reg=t0 | |
| 57 | mfc0 \reg, CP0_STATUS | |
| 58 | ori \reg, \reg, 1 | |
| 59 | xori \reg, \reg, 1 | |
| 60 | mtc0 \reg, CP0_STATUS | |
| 61 | irq_disable_hazard | |
| 62 | .endm | |
| 41c594ab | 63 | #endif /* CONFIG_MIPS_MT_SMTC */ |
| 1da177e4 | 64 | |
| 41c594ab RB |
65 | /* |
| 66 | * Temporary until all gas have MT ASE support | |
| 67 | */ | |
| 68 | .macro DMT reg=0 | |
| 49a89efb | 69 | .word 0x41600bc1 | (\reg << 16) |
| 41c594ab RB |
70 | .endm |
| 71 | ||
| 72 | .macro EMT reg=0 | |
| 49a89efb | 73 | .word 0x41600be1 | (\reg << 16) |
| 41c594ab RB |
74 | .endm |
| 75 | ||
| 76 | .macro DVPE reg=0 | |
| 49a89efb | 77 | .word 0x41600001 | (\reg << 16) |
| 41c594ab RB |
78 | .endm |
| 79 | ||
| 80 | .macro EVPE reg=0 | |
| 49a89efb | 81 | .word 0x41600021 | (\reg << 16) |
| 41c594ab RB |
82 | .endm |
| 83 | ||
| 84 | .macro MFTR rt=0, rd=0, u=0, sel=0 | |
| 49a89efb | 85 | .word 0x41000000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel) |
| 41c594ab RB |
86 | .endm |
| 87 | ||
| 88 | .macro MTTR rt=0, rd=0, u=0, sel=0 | |
| 49a89efb | 89 | .word 0x41800000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel) |
| 41c594ab RB |
90 | .endm |
| 91 | ||
| 1da177e4 | 92 | #endif /* _ASM_ASMMACRO_H */ |