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[MIPS] Fix "no space between function name and open parenthesis" warnings.
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / mips / au1000 / common / reset.c
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1da177e4
LT		 1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * Au1000 reset routines.
5 *
6 * Copyright 2001 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc.
8 * ppopov@mvista.com or source@mvista.com
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
1da177e4
LT		 30#include <linux/sched.h>
31#include <linux/mm.h>
32#include <asm/io.h>
33#include <asm/pgtable.h>
34#include <asm/processor.h>
35#include <asm/reboot.h>
36#include <asm/system.h>
37#include <asm/mach-au1x00/au1000.h>
38
39extern int au_sleep(void);
40extern void (*flush_cache_all)(void);
41
42void au1000_restart(char *command)
43{
44 /* Set all integrated peripherals to disabled states */
49a89efb 45 extern void board_reset(void);
1da177e4
LT		 46 u32 prid = read_c0_prid();
47
48 printk(KERN_NOTICE "\n** Resetting Integrated Peripherals\n");
49 switch (prid & 0xFF000000)
50 {
51 case 0x00000000: /* Au1000 */
52 au_writel(0x02, 0xb0000010); /* ac97_enable */
53 au_writel(0x08, 0xb017fffc); /* usbh_enable - early errata */
54 asm("sync");
55 au_writel(0x00, 0xb017fffc); /* usbh_enable */
56 au_writel(0x00, 0xb0200058); /* usbd_enable */
57 au_writel(0x00, 0xb0300040); /* ir_enable */
58 au_writel(0x00, 0xb4004104); /* mac dma */
59 au_writel(0x00, 0xb4004114); /* mac dma */
60 au_writel(0x00, 0xb4004124); /* mac dma */
61 au_writel(0x00, 0xb4004134); /* mac dma */
62 au_writel(0x00, 0xb0520000); /* macen0 */
63 au_writel(0x00, 0xb0520004); /* macen1 */
64 au_writel(0x00, 0xb1000008); /* i2s_enable */
65 au_writel(0x00, 0xb1100100); /* uart0_enable */
66 au_writel(0x00, 0xb1200100); /* uart1_enable */
67 au_writel(0x00, 0xb1300100); /* uart2_enable */
68 au_writel(0x00, 0xb1400100); /* uart3_enable */
69 au_writel(0x02, 0xb1600100); /* ssi0_enable */
70 au_writel(0x02, 0xb1680100); /* ssi1_enable */
71 au_writel(0x00, 0xb1900020); /* sys_freqctrl0 */
72 au_writel(0x00, 0xb1900024); /* sys_freqctrl1 */
73 au_writel(0x00, 0xb1900028); /* sys_clksrc */
74 au_writel(0x10, 0xb1900060); /* sys_cpupll */
75 au_writel(0x00, 0xb1900064); /* sys_auxpll */
76 au_writel(0x00, 0xb1900100); /* sys_pininputen */
77 break;
78 case 0x01000000: /* Au1500 */
79 au_writel(0x02, 0xb0000010); /* ac97_enable */
80 au_writel(0x08, 0xb017fffc); /* usbh_enable - early errata */
81 asm("sync");
82 au_writel(0x00, 0xb017fffc); /* usbh_enable */
83 au_writel(0x00, 0xb0200058); /* usbd_enable */
84 au_writel(0x00, 0xb4004104); /* mac dma */
85 au_writel(0x00, 0xb4004114); /* mac dma */
86 au_writel(0x00, 0xb4004124); /* mac dma */
87 au_writel(0x00, 0xb4004134); /* mac dma */
88 au_writel(0x00, 0xb1520000); /* macen0 */
89 au_writel(0x00, 0xb1520004); /* macen1 */
90 au_writel(0x00, 0xb1100100); /* uart0_enable */
91 au_writel(0x00, 0xb1400100); /* uart3_enable */
92 au_writel(0x00, 0xb1900020); /* sys_freqctrl0 */
93 au_writel(0x00, 0xb1900024); /* sys_freqctrl1 */
94 au_writel(0x00, 0xb1900028); /* sys_clksrc */
95 au_writel(0x10, 0xb1900060); /* sys_cpupll */
96 au_writel(0x00, 0xb1900064); /* sys_auxpll */
97 au_writel(0x00, 0xb1900100); /* sys_pininputen */
98 break;
99 case 0x02000000: /* Au1100 */
100 au_writel(0x02, 0xb0000010); /* ac97_enable */
101 au_writel(0x08, 0xb017fffc); /* usbh_enable - early errata */
102 asm("sync");
103 au_writel(0x00, 0xb017fffc); /* usbh_enable */
104 au_writel(0x00, 0xb0200058); /* usbd_enable */
105 au_writel(0x00, 0xb0300040); /* ir_enable */
106 au_writel(0x00, 0xb4004104); /* mac dma */
107 au_writel(0x00, 0xb4004114); /* mac dma */
108 au_writel(0x00, 0xb4004124); /* mac dma */
109 au_writel(0x00, 0xb4004134); /* mac dma */
110 au_writel(0x00, 0xb0520000); /* macen0 */
111 au_writel(0x00, 0xb1000008); /* i2s_enable */
112 au_writel(0x00, 0xb1100100); /* uart0_enable */
113 au_writel(0x00, 0xb1200100); /* uart1_enable */
114 au_writel(0x00, 0xb1400100); /* uart3_enable */
115 au_writel(0x02, 0xb1600100); /* ssi0_enable */
116 au_writel(0x02, 0xb1680100); /* ssi1_enable */
117 au_writel(0x00, 0xb1900020); /* sys_freqctrl0 */
118 au_writel(0x00, 0xb1900024); /* sys_freqctrl1 */
119 au_writel(0x00, 0xb1900028); /* sys_clksrc */
120 au_writel(0x10, 0xb1900060); /* sys_cpupll */
121 au_writel(0x00, 0xb1900064); /* sys_auxpll */
122 au_writel(0x00, 0xb1900100); /* sys_pininputen */
123 break;
124 case 0x03000000: /* Au1550 */
125 au_writel(0x00, 0xb1a00004); /* psc 0 */
126 au_writel(0x00, 0xb1b00004); /* psc 1 */
127 au_writel(0x00, 0xb0a00004); /* psc 2 */
128 au_writel(0x00, 0xb0b00004); /* psc 3 */
129 au_writel(0x00, 0xb017fffc); /* usbh_enable */
130 au_writel(0x00, 0xb0200058); /* usbd_enable */
131 au_writel(0x00, 0xb4004104); /* mac dma */
132 au_writel(0x00, 0xb4004114); /* mac dma */
133 au_writel(0x00, 0xb4004124); /* mac dma */
134 au_writel(0x00, 0xb4004134); /* mac dma */
135 au_writel(0x00, 0xb1520000); /* macen0 */
136 au_writel(0x00, 0xb1520004); /* macen1 */
137 au_writel(0x00, 0xb1100100); /* uart0_enable */
138 au_writel(0x00, 0xb1200100); /* uart1_enable */
139 au_writel(0x00, 0xb1400100); /* uart3_enable */
140 au_writel(0x00, 0xb1900020); /* sys_freqctrl0 */
141 au_writel(0x00, 0xb1900024); /* sys_freqctrl1 */
142 au_writel(0x00, 0xb1900028); /* sys_clksrc */
143 au_writel(0x10, 0xb1900060); /* sys_cpupll */
144 au_writel(0x00, 0xb1900064); /* sys_auxpll */
145 au_writel(0x00, 0xb1900100); /* sys_pininputen */
146 break;
147
148 default:
149 break;
150 }
151
152 set_c0_status(ST0_BEV | ST0_ERL);
80730555 153 change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
1da177e4
LT		 154 flush_cache_all();
155 write_c0_wired(0);
156
157 /* Give board a chance to do a hardware reset */
158 board_reset();
159
160 /* Jump to the beggining in case board_reset() is empty */
161 __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
162}
163
164void au1000_halt(void)
165{
86dde15b 166#if defined(CONFIG_MIPS_PB1550) || defined(CONFIG_MIPS_DB1550)
1da177e4 167 /* power off system */
86dde15b 168 printk("\n** Powering off...\n");
1da177e4
LT		 169 au_writew(au_readw(0xAF00001C) | (3<<14), 0xAF00001C);
170 au_sync();
171 while(1); /* should not get here */
86dde15b 172#else
1da177e4
LT		 173 printk(KERN_NOTICE "\n** You can safely turn off the power\n");
174#ifdef CONFIG_MIPS_MIRAGE
175 au_writel((1 << 26) | (1 << 10), GPIO2_OUTPUT);
176#endif
66a9a4ff
MK		 177#ifdef CONFIG_MIPS_DB1200
178 au_writew(au_readw(0xB980001C) | (1<<14), 0xB980001C);
179#endif
1da177e4
LT		 180#ifdef CONFIG_PM
181 au_sleep();
182
183 /* should not get here */
184 printk(KERN_ERR "Unable to put cpu in sleep mode\n");
185 while(1);
186#else
187 while (1)
188 __asm__(".set\tmips3\n\t"
189 "wait\n\t"
190 ".set\tmips0");
191#endif
86dde15b 192#endif /* defined(CONFIG_MIPS_PB1550) || defined(CONFIG_MIPS_DB1550) */
1da177e4
LT		 193}
194
195void au1000_power_off(void)
196{
197 au1000_halt();
198}
kernel source for telekom puls (alcatel/mediatek)