[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / mips / ath79 / setup.c

/*
 *  Atheros AR71XX/AR724X/AR913X specific setup
 *
 *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
 *  Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
 *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
 *
 *  Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms of the GNU General Public License version 2 as published
 *  by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/bootmem.h>
#include <linux/err.h>
#include <linux/clk.h>

#include <asm/bootinfo.h>
#include <asm/idle.h>
#include <asm/time.h>		/* for mips_hpt_frequency */
#include <asm/reboot.h>		/* for _machine_{restart,halt} */
#include <asm/mips_machine.h>

#include <asm/mach-ath79/ath79.h>
#include <asm/mach-ath79/ar71xx_regs.h>
#include "common.h"
#include "dev-common.h"
#include "machtypes.h"

#define ATH79_SYS_TYPE_LEN	64

#define AR71XX_BASE_FREQ	40000000
#define AR724X_BASE_FREQ	5000000
#define AR913X_BASE_FREQ	5000000

static char ath79_sys_type[ATH79_SYS_TYPE_LEN];

static void ath79_restart(char *command)
{
	ath79_device_reset_set(AR71XX_RESET_FULL_CHIP);
	for (;;)
		if (cpu_wait)
			cpu_wait();
}

static void ath79_halt(void)
{
	while (1)
		cpu_wait();
}

static void __init ath79_detect_sys_type(void)
{
	char *chip = "????";
	u32 id;
	u32 major;
	u32 minor;
	u32 rev = 0;

	id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID);
	major = id & REV_ID_MAJOR_MASK;

	switch (major) {
	case REV_ID_MAJOR_AR71XX:
		minor = id & AR71XX_REV_ID_MINOR_MASK;
		rev = id >> AR71XX_REV_ID_REVISION_SHIFT;
		rev &= AR71XX_REV_ID_REVISION_MASK;
		switch (minor) {
		case AR71XX_REV_ID_MINOR_AR7130:
			ath79_soc = ATH79_SOC_AR7130;
			chip = "7130";
			break;

		case AR71XX_REV_ID_MINOR_AR7141:
			ath79_soc = ATH79_SOC_AR7141;
			chip = "7141";
			break;

		case AR71XX_REV_ID_MINOR_AR7161:
			ath79_soc = ATH79_SOC_AR7161;
			chip = "7161";
			break;
		}
		break;

	case REV_ID_MAJOR_AR7240:
		ath79_soc = ATH79_SOC_AR7240;
		chip = "7240";
		rev = id & AR724X_REV_ID_REVISION_MASK;
		break;

	case REV_ID_MAJOR_AR7241:
		ath79_soc = ATH79_SOC_AR7241;
		chip = "7241";
		rev = id & AR724X_REV_ID_REVISION_MASK;
		break;

	case REV_ID_MAJOR_AR7242:
		ath79_soc = ATH79_SOC_AR7242;
		chip = "7242";
		rev = id & AR724X_REV_ID_REVISION_MASK;
		break;

	case REV_ID_MAJOR_AR913X:
		minor = id & AR913X_REV_ID_MINOR_MASK;
		rev = id >> AR913X_REV_ID_REVISION_SHIFT;
		rev &= AR913X_REV_ID_REVISION_MASK;
		switch (minor) {
		case AR913X_REV_ID_MINOR_AR9130:
			ath79_soc = ATH79_SOC_AR9130;
			chip = "9130";
			break;

		case AR913X_REV_ID_MINOR_AR9132:
			ath79_soc = ATH79_SOC_AR9132;
			chip = "9132";
			break;
		}
		break;

	case REV_ID_MAJOR_AR9330:
		ath79_soc = ATH79_SOC_AR9330;
		chip = "9330";
		rev = id & AR933X_REV_ID_REVISION_MASK;
		break;

	case REV_ID_MAJOR_AR9331:
		ath79_soc = ATH79_SOC_AR9331;
		chip = "9331";
		rev = id & AR933X_REV_ID_REVISION_MASK;
		break;

	case REV_ID_MAJOR_AR9341:
		ath79_soc = ATH79_SOC_AR9341;
		chip = "9341";
		rev = id & AR934X_REV_ID_REVISION_MASK;
		break;

	case REV_ID_MAJOR_AR9342:
		ath79_soc = ATH79_SOC_AR9342;
		chip = "9342";
		rev = id & AR934X_REV_ID_REVISION_MASK;
		break;

	case REV_ID_MAJOR_AR9344:
		ath79_soc = ATH79_SOC_AR9344;
		chip = "9344";
		rev = id & AR934X_REV_ID_REVISION_MASK;
		break;

	case REV_ID_MAJOR_QCA9556:
		ath79_soc = ATH79_SOC_QCA9556;
		chip = "9556";
		rev = id & QCA955X_REV_ID_REVISION_MASK;
		break;

	case REV_ID_MAJOR_QCA9558:
		ath79_soc = ATH79_SOC_QCA9558;
		chip = "9558";
		rev = id & QCA955X_REV_ID_REVISION_MASK;
		break;

	default:
		panic("ath79: unknown SoC, id:0x%08x", id);
	}

	ath79_soc_rev = rev;

	if (soc_is_qca955x())
		sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u",
			chip, rev);
	else
		sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
	pr_info("SoC: %s\n", ath79_sys_type);
}

const char *get_system_type(void)
{
	return ath79_sys_type;
}

unsigned int __cpuinit get_c0_compare_int(void)
{
	return CP0_LEGACY_COMPARE_IRQ;
}

void __init plat_mem_setup(void)
{
	set_io_port_base(KSEG1);

	ath79_reset_base = ioremap_nocache(AR71XX_RESET_BASE,
					   AR71XX_RESET_SIZE);
	ath79_pll_base = ioremap_nocache(AR71XX_PLL_BASE,
					 AR71XX_PLL_SIZE);
	ath79_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE,
					 AR71XX_DDR_CTRL_SIZE);

	ath79_detect_sys_type();
	detect_memory_region(0, ATH79_MEM_SIZE_MIN, ATH79_MEM_SIZE_MAX);
	ath79_clocks_init();

	_machine_restart = ath79_restart;
	_machine_halt = ath79_halt;
	pm_power_off = ath79_halt;
}

void __init plat_time_init(void)
{
	struct clk *clk;

	clk = clk_get(NULL, "cpu");
	if (IS_ERR(clk))
		panic("unable to get CPU clock, err=%ld", PTR_ERR(clk));

	mips_hpt_frequency = clk_get_rate(clk) / 2;
}

static int __init ath79_setup(void)
{
	ath79_gpio_init();
	ath79_register_uart();
	ath79_register_wdt();

	mips_machine_setup();

	return 0;
}

arch_initcall(ath79_setup);

static void __init ath79_generic_init(void)
{
	/* Nothing to do */
}

MIPS_MACHINE(ATH79_MACH_GENERIC,
	     "Generic",
	     "Generic AR71XX/AR724X/AR913X based board",
	     ath79_generic_init);
Commit	Line	Data
d4a67d9d GJ	1	/*
	2	* Atheros AR71XX/AR724X/AR913X specific setup
	3	*
d8411466	4	* Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
d4a67d9d GJ	5	* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
	6	* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
	7	*
d8411466	8	* Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
d4a67d9d GJ	9	*
	10	* This program is free software; you can redistribute it and/or modify it
	11	* under the terms of the GNU General Public License version 2 as published
	12	* by the Free Software Foundation.
	13	*/
	14
	15	#include <linux/kernel.h>
	16	#include <linux/init.h>
	17	#include <linux/bootmem.h>
	18	#include <linux/err.h>
	19	#include <linux/clk.h>
	20
	21	#include <asm/bootinfo.h>
bdc92d74	22	#include <asm/idle.h>
d4a67d9d GJ	23	#include <asm/time.h> /* for mips_hpt_frequency */
d4a67d9d GJ	24	#include <asm/reboot.h> /* for _machine_{restart,halt} */
0aabf1a4	25	#include <asm/mips_machine.h>
d4a67d9d GJ	26
	27	#include <asm/mach-ath79/ath79.h>
	28	#include <asm/mach-ath79/ar71xx_regs.h>
	29	#include "common.h"
	30	#include "dev-common.h"
0aabf1a4	31	#include "machtypes.h"
d4a67d9d GJ	32
	33	#define ATH79_SYS_TYPE_LEN 64
	34
	35	#define AR71XX_BASE_FREQ 40000000
	36	#define AR724X_BASE_FREQ 5000000
	37	#define AR913X_BASE_FREQ 5000000
	38
	39	static char ath79_sys_type[ATH79_SYS_TYPE_LEN];
	40
	41	static void ath79_restart(char *command)
	42	{
	43	ath79_device_reset_set(AR71XX_RESET_FULL_CHIP);
	44	for (;;)
	45	if (cpu_wait)
	46	cpu_wait();
	47	}
	48
	49	static void ath79_halt(void)
	50	{
	51	while (1)
	52	cpu_wait();
	53	}
	54
d4a67d9d GJ	55	static void __init ath79_detect_sys_type(void)
	56	{
	57	char *chip = "????";
	58	u32 id;
	59	u32 major;
	60	u32 minor;
	61	u32 rev = 0;
	62
	63	id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID);
	64	major = id & REV_ID_MAJOR_MASK;
	65
	66	switch (major) {
	67	case REV_ID_MAJOR_AR71XX:
	68	minor = id & AR71XX_REV_ID_MINOR_MASK;
	69	rev = id >> AR71XX_REV_ID_REVISION_SHIFT;
	70	rev &= AR71XX_REV_ID_REVISION_MASK;
	71	switch (minor) {
	72	case AR71XX_REV_ID_MINOR_AR7130:
	73	ath79_soc = ATH79_SOC_AR7130;
	74	chip = "7130";
	75	break;
	76
	77	case AR71XX_REV_ID_MINOR_AR7141:
	78	ath79_soc = ATH79_SOC_AR7141;
	79	chip = "7141";
	80	break;
	81
	82	case AR71XX_REV_ID_MINOR_AR7161:
	83	ath79_soc = ATH79_SOC_AR7161;
	84	chip = "7161";
	85	break;
	86	}
	87	break;
	88
	89	case REV_ID_MAJOR_AR7240:
	90	ath79_soc = ATH79_SOC_AR7240;
	91	chip = "7240";
8bed1288	92	rev = id & AR724X_REV_ID_REVISION_MASK;
d4a67d9d GJ	93	break;
	94
	95	case REV_ID_MAJOR_AR7241:
	96	ath79_soc = ATH79_SOC_AR7241;
	97	chip = "7241";
8bed1288	98	rev = id & AR724X_REV_ID_REVISION_MASK;
d4a67d9d GJ	99	break;
	100
	101	case REV_ID_MAJOR_AR7242:
	102	ath79_soc = ATH79_SOC_AR7242;
	103	chip = "7242";
8bed1288	104	rev = id & AR724X_REV_ID_REVISION_MASK;
d4a67d9d GJ	105	break;
	106
	107	case REV_ID_MAJOR_AR913X:
	108	minor = id & AR913X_REV_ID_MINOR_MASK;
	109	rev = id >> AR913X_REV_ID_REVISION_SHIFT;
	110	rev &= AR913X_REV_ID_REVISION_MASK;
	111	switch (minor) {
	112	case AR913X_REV_ID_MINOR_AR9130:
	113	ath79_soc = ATH79_SOC_AR9130;
	114	chip = "9130";
	115	break;
	116
	117	case AR913X_REV_ID_MINOR_AR9132:
	118	ath79_soc = ATH79_SOC_AR9132;
	119	chip = "9132";
	120	break;
	121	}
	122	break;
	123
80a7ed81 GJ	124	case REV_ID_MAJOR_AR9330:
	125	ath79_soc = ATH79_SOC_AR9330;
	126	chip = "9330";
	127	rev = id & AR933X_REV_ID_REVISION_MASK;
	128	break;
	129
	130	case REV_ID_MAJOR_AR9331:
	131	ath79_soc = ATH79_SOC_AR9331;
	132	chip = "9331";
	133	rev = id & AR933X_REV_ID_REVISION_MASK;
	134	break;
	135
d8411466 GJ	136	case REV_ID_MAJOR_AR9341:
	137	ath79_soc = ATH79_SOC_AR9341;
	138	chip = "9341";
	139	rev = id & AR934X_REV_ID_REVISION_MASK;
	140	break;
	141
	142	case REV_ID_MAJOR_AR9342:
	143	ath79_soc = ATH79_SOC_AR9342;
	144	chip = "9342";
	145	rev = id & AR934X_REV_ID_REVISION_MASK;
	146	break;
	147
	148	case REV_ID_MAJOR_AR9344:
	149	ath79_soc = ATH79_SOC_AR9344;
	150	chip = "9344";
	151	rev = id & AR934X_REV_ID_REVISION_MASK;
	152	break;
	153
2e6c91e3 GJ	154	case REV_ID_MAJOR_QCA9556:
	155	ath79_soc = ATH79_SOC_QCA9556;
	156	chip = "9556";
	157	rev = id & QCA955X_REV_ID_REVISION_MASK;
	158	break;
	159
	160	case REV_ID_MAJOR_QCA9558:
	161	ath79_soc = ATH79_SOC_QCA9558;
	162	chip = "9558";
	163	rev = id & QCA955X_REV_ID_REVISION_MASK;
	164	break;
	165
d4a67d9d	166	default:
ab75dc02	167	panic("ath79: unknown SoC, id:0x%08x", id);
d4a67d9d GJ	168	}
d4a67d9d GJ	169
be5f3623 GJ	170	ath79_soc_rev = rev;
be5f3623 GJ	171
2e6c91e3 GJ	172	if (soc_is_qca955x())
	173	sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u",
	174	chip, rev);
	175	else
	176	sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
d4a67d9d GJ	177	pr_info("SoC: %s\n", ath79_sys_type);
	178	}
	179
	180	const char *get_system_type(void)
	181	{
	182	return ath79_sys_type;
	183	}
	184
	185	unsigned int __cpuinit get_c0_compare_int(void)
	186	{
	187	return CP0_LEGACY_COMPARE_IRQ;
	188	}
	189
	190	void __init plat_mem_setup(void)
	191	{
	192	set_io_port_base(KSEG1);
	193
	194	ath79_reset_base = ioremap_nocache(AR71XX_RESET_BASE,
	195	AR71XX_RESET_SIZE);
	196	ath79_pll_base = ioremap_nocache(AR71XX_PLL_BASE,
	197	AR71XX_PLL_SIZE);
d4a67d9d GJ	198	ath79_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE,
	199	AR71XX_DDR_CTRL_SIZE);
	200
	201	ath79_detect_sys_type();
9b75733b	202	detect_memory_region(0, ATH79_MEM_SIZE_MIN, ATH79_MEM_SIZE_MAX);
d4a67d9d GJ	203	ath79_clocks_init();
	204
	205	_machine_restart = ath79_restart;
	206	_machine_halt = ath79_halt;
	207	pm_power_off = ath79_halt;
	208	}
	209
	210	void __init plat_time_init(void)
	211	{
	212	struct clk *clk;
	213
	214	clk = clk_get(NULL, "cpu");
	215	if (IS_ERR(clk))
	216	panic("unable to get CPU clock, err=%ld", PTR_ERR(clk));
	217
	218	mips_hpt_frequency = clk_get_rate(clk) / 2;
	219	}
	220
	221	static int __init ath79_setup(void)
	222	{
6eae43c5	223	ath79_gpio_init();
d4a67d9d	224	ath79_register_uart();
858f763c	225	ath79_register_wdt();
0aabf1a4 GJ	226
	227	mips_machine_setup();
	228
d4a67d9d GJ	229	return 0;
	230	}
	231
	232	arch_initcall(ath79_setup);
0aabf1a4 GJ	233
	234	static void __init ath79_generic_init(void)
	235	{
	236	/* Nothing to do */
	237	}
	238
	239	MIPS_MACHINE(ATH79_MACH_GENERIC,
	240	"Generic",
	241	"Generic AR71XX/AR724X/AR913X based board",
	242	ath79_generic_init);