projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
| Commit | Line | Data |
|---|---|---|
| d4a67d9d GJ |
1 | /* |
| 2 | * Atheros AR71XX/AR724X/AR913X common routines | |
| 3 | * | |
| 42184768 GJ |
4 | * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com> |
| 5 | * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> | |
| d4a67d9d GJ |
6 | * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> |
| 7 | * | |
| 42184768 GJ |
8 | * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP |
| 9 | * | |
| d4a67d9d GJ |
10 | * This program is free software; you can redistribute it and/or modify it |
| 11 | * under the terms of the GNU General Public License version 2 as published | |
| 12 | * by the Free Software Foundation. | |
| 13 | */ | |
| 14 | ||
| 15 | #include <linux/kernel.h> | |
| 16 | #include <linux/module.h> | |
| 17 | #include <linux/types.h> | |
| 18 | #include <linux/spinlock.h> | |
| 19 | ||
| 20 | #include <asm/mach-ath79/ath79.h> | |
| 21 | #include <asm/mach-ath79/ar71xx_regs.h> | |
| 22 | #include "common.h" | |
| 23 | ||
| 24 | static DEFINE_SPINLOCK(ath79_device_reset_lock); | |
| 25 | ||
| 26 | u32 ath79_cpu_freq; | |
| 27 | EXPORT_SYMBOL_GPL(ath79_cpu_freq); | |
| 28 | ||
| 29 | u32 ath79_ahb_freq; | |
| 30 | EXPORT_SYMBOL_GPL(ath79_ahb_freq); | |
| 31 | ||
| 32 | u32 ath79_ddr_freq; | |
| 33 | EXPORT_SYMBOL_GPL(ath79_ddr_freq); | |
| 34 | ||
| 35 | enum ath79_soc_type ath79_soc; | |
| be5f3623 | 36 | unsigned int ath79_soc_rev; |
| d4a67d9d GJ |
37 | |
| 38 | void __iomem *ath79_pll_base; | |
| 39 | void __iomem *ath79_reset_base; | |
| 40 | EXPORT_SYMBOL_GPL(ath79_reset_base); | |
| 41 | void __iomem *ath79_ddr_base; | |
| 42 | ||
| 43 | void ath79_ddr_wb_flush(u32 reg) | |
| 44 | { | |
| 45 | void __iomem *flush_reg = ath79_ddr_base + reg; | |
| 46 | ||
| 47 | /* Flush the DDR write buffer. */ | |
| 48 | __raw_writel(0x1, flush_reg); | |
| 49 | while (__raw_readl(flush_reg) & 0x1) | |
| 50 | ; | |
| 51 | ||
| 52 | /* It must be run twice. */ | |
| 53 | __raw_writel(0x1, flush_reg); | |
| 54 | while (__raw_readl(flush_reg) & 0x1) | |
| 55 | ; | |
| 56 | } | |
| 57 | EXPORT_SYMBOL_GPL(ath79_ddr_wb_flush); | |
| 58 | ||
| 59 | void ath79_device_reset_set(u32 mask) | |
| 60 | { | |
| 61 | unsigned long flags; | |
| 62 | u32 reg; | |
| 63 | u32 t; | |
| 64 | ||
| 65 | if (soc_is_ar71xx()) | |
| 66 | reg = AR71XX_RESET_REG_RESET_MODULE; | |
| 67 | else if (soc_is_ar724x()) | |
| 68 | reg = AR724X_RESET_REG_RESET_MODULE; | |
| 69 | else if (soc_is_ar913x()) | |
| 70 | reg = AR913X_RESET_REG_RESET_MODULE; | |
| 7ee15d8a GJ |
71 | else if (soc_is_ar933x()) |
| 72 | reg = AR933X_RESET_REG_RESET_MODULE; | |
| 42184768 GJ |
73 | else if (soc_is_ar934x()) |
| 74 | reg = AR934X_RESET_REG_RESET_MODULE; | |
| 7d4c2af9 GJ |
75 | else if (soc_is_qca955x()) |
| 76 | reg = QCA955X_RESET_REG_RESET_MODULE; | |
| d4a67d9d GJ |
77 | else |
| 78 | BUG(); | |
| 79 | ||
| 80 | spin_lock_irqsave(&ath79_device_reset_lock, flags); | |
| 81 | t = ath79_reset_rr(reg); | |
| 82 | ath79_reset_wr(reg, t | mask); | |
| 83 | spin_unlock_irqrestore(&ath79_device_reset_lock, flags); | |
| 84 | } | |
| 85 | EXPORT_SYMBOL_GPL(ath79_device_reset_set); | |
| 86 | ||
| 87 | void ath79_device_reset_clear(u32 mask) | |
| 88 | { | |
| 89 | unsigned long flags; | |
| 90 | u32 reg; | |
| 91 | u32 t; | |
| 92 | ||
| 93 | if (soc_is_ar71xx()) | |
| 94 | reg = AR71XX_RESET_REG_RESET_MODULE; | |
| 95 | else if (soc_is_ar724x()) | |
| 96 | reg = AR724X_RESET_REG_RESET_MODULE; | |
| 97 | else if (soc_is_ar913x()) | |
| 98 | reg = AR913X_RESET_REG_RESET_MODULE; | |
| 7ee15d8a GJ |
99 | else if (soc_is_ar933x()) |
| 100 | reg = AR933X_RESET_REG_RESET_MODULE; | |
| 42184768 GJ |
101 | else if (soc_is_ar934x()) |
| 102 | reg = AR934X_RESET_REG_RESET_MODULE; | |
| 7d4c2af9 GJ |
103 | else if (soc_is_qca955x()) |
| 104 | reg = QCA955X_RESET_REG_RESET_MODULE; | |
| d4a67d9d GJ |
105 | else |
| 106 | BUG(); | |
| 107 | ||
| 108 | spin_lock_irqsave(&ath79_device_reset_lock, flags); | |
| 109 | t = ath79_reset_rr(reg); | |
| 110 | ath79_reset_wr(reg, t & ~mask); | |
| 111 | spin_unlock_irqrestore(&ath79_device_reset_lock, flags); | |
| 112 | } | |
| 113 | EXPORT_SYMBOL_GPL(ath79_device_reset_clear); |