[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / mips / alchemy / devboards / db1x00 / board_setup.c

/*
 *
 * BRIEF MODULE DESCRIPTION
 *	Alchemy Db1x00 board setup.
 *
 * Copyright 2000, 2008 MontaVista Software Inc.
 * Author: MontaVista Software, Inc. <source@mvista.com>
 *
 *  This program is free software; you can redistribute  it and/or modify it
 *  under  the terms of  the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the  License, or (at your
 *  option) any later version.
 *
 *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *  You should have received a copy of the  GNU General Public License along
 *  with this program; if not, write  to the Free Software Foundation, Inc.,
 *  675 Mass Ave, Cambridge, MA 02139, USA.
 */

#include <linux/gpio.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/pm.h>

#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-au1x00/au1xxx_eth.h>
#include <asm/mach-db1x00/db1x00.h>
#include <asm/mach-db1x00/bcsr.h>
#include <asm/reboot.h>

#include <prom.h>

#ifdef CONFIG_MIPS_DB1500
char irq_tab_alchemy[][5] __initdata = {
	[12] = { -1, AU1500_PCI_INTA, 0xff, 0xff, 0xff }, /* IDSEL 12 - HPT371   */
	[13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, AU1500_PCI_INTC, AU1500_PCI_INTD }, /* IDSEL 13 - PCI slot */
};

#endif


#ifdef CONFIG_MIPS_DB1550
char irq_tab_alchemy[][5] __initdata = {
	[11] = { -1, AU1550_PCI_INTC, 0xff, 0xff, 0xff }, /* IDSEL 11 - on-board HPT371 */
	[12] = { -1, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD, AU1550_PCI_INTA }, /* IDSEL 12 - PCI slot 2 (left) */
	[13] = { -1, AU1550_PCI_INTA, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD }, /* IDSEL 13 - PCI slot 1 (right) */
};
#endif


#ifdef CONFIG_MIPS_BOSPORUS
char irq_tab_alchemy[][5] __initdata = {
	[11] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 11 - miniPCI  */
	[12] = { -1, AU1500_PCI_INTA, 0xff, 0xff, 0xff }, /* IDSEL 12 - SN1741   */
	[13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, AU1500_PCI_INTC, AU1500_PCI_INTD }, /* IDSEL 13 - PCI slot */
};

/*
 * Micrel/Kendin 5 port switch attached to MAC0,
 * MAC0 is associated with PHY address 5 (== WAN port)
 * MAC1 is not associated with any PHY, since it's connected directly
 * to the switch.
 * no interrupts are used
 */
static struct au1000_eth_platform_data eth0_pdata = {
	.phy_static_config	= 1,
	.phy_addr		= 5,
};

static void bosporus_power_off(void)
{
	while (1)
		asm volatile (".set mips3 ; wait ; .set mips0");
}

const char *get_system_type(void)
{
	return "Alchemy Bosporus Gateway Reference";
}
#endif


#ifdef CONFIG_MIPS_MIRAGE
char irq_tab_alchemy[][5] __initdata = {
	[11] = { -1, AU1500_PCI_INTD, 0xff, 0xff, 0xff }, /* IDSEL 11 - SMI VGX */
	[12] = { -1, 0xff, 0xff, AU1500_PCI_INTC, 0xff }, /* IDSEL 12 - PNX1300 */
	[13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 13 - miniPCI */
};

static void mirage_power_off(void)
{
	alchemy_gpio_direction_output(210, 1);
}

const char *get_system_type(void)
{
	return "Alchemy Mirage";
}
#endif


#if defined(CONFIG_MIPS_BOSPORUS) || defined(CONFIG_MIPS_MIRAGE)
static void mips_softreset(void)
{
	asm volatile ("jr\t%0" : : "r"(0xbfc00000));
}

#else

const char *get_system_type(void)
{
	return "Alchemy Db1x00";
}
#endif


void __init board_setup(void)
{
	unsigned long bcsr1, bcsr2;

	bcsr1 = DB1000_BCSR_PHYS_ADDR;
	bcsr2 = DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS;

#ifdef CONFIG_MIPS_DB1000
	printk(KERN_INFO "AMD Alchemy Au1000/Db1000 Board\n");
#endif
#ifdef CONFIG_MIPS_DB1500
	printk(KERN_INFO "AMD Alchemy Au1500/Db1500 Board\n");
#endif
#ifdef CONFIG_MIPS_DB1100
	printk(KERN_INFO "AMD Alchemy Au1100/Db1100 Board\n");
#endif
#ifdef CONFIG_MIPS_BOSPORUS
	au1xxx_override_eth_cfg(0, &eth0_pdata);

	printk(KERN_INFO "AMD Alchemy Bosporus Board\n");
#endif
#ifdef CONFIG_MIPS_MIRAGE
	printk(KERN_INFO "AMD Alchemy Mirage Board\n");
#endif
#ifdef CONFIG_MIPS_DB1550
	printk(KERN_INFO "AMD Alchemy Au1550/Db1550 Board\n");

	bcsr1 = DB1550_BCSR_PHYS_ADDR;
	bcsr2 = DB1550_BCSR_PHYS_ADDR + DB1550_BCSR_HEXLED_OFS;
#endif

	/* initialize board register space */
	bcsr_init(bcsr1, bcsr2);

	/* Not valid for Au1550 */
#if defined(CONFIG_IRDA) && \
   (defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1100))
	{
		u32 pin_func;

		/* Set IRFIRSEL instead of GPIO15 */
		pin_func = au_readl(SYS_PINFUNC) | SYS_PF_IRF;
		au_writel(pin_func, SYS_PINFUNC);
		/* Power off until the driver is in use */
		bcsr_mod(BCSR_RESETS, BCSR_RESETS_IRDA_MODE_MASK,
			 BCSR_RESETS_IRDA_MODE_OFF);
	}
#endif
	bcsr_write(BCSR_PCMCIA, 0);	/* turn off PCMCIA power */

	/* Enable GPIO[31:0] inputs */
	alchemy_gpio1_input_enable();

#ifdef CONFIG_MIPS_MIRAGE
	{
		u32 pin_func;

		/* GPIO[20] is output */
		alchemy_gpio_direction_output(20, 0);

		/* Set GPIO[210:208] instead of SSI_0 */
		pin_func = au_readl(SYS_PINFUNC) | SYS_PF_S0;

		/* Set GPIO[215:211] for LEDs */
		pin_func |= 5 << 2;

		/* Set GPIO[214:213] for more LEDs */
		pin_func |= 5 << 12;

		/* Set GPIO[207:200] instead of PCMCIA/LCD */
		pin_func |= SYS_PF_LCD | SYS_PF_PC;
		au_writel(pin_func, SYS_PINFUNC);

		/*
		 * Enable speaker amplifier.  This should
		 * be part of the audio driver.
		 */
		alchemy_gpio_direction_output(209, 1);

		pm_power_off = mirage_power_off;
		_machine_halt = mirage_power_off;
		_machine_restart = (void(*)(char *))mips_softreset;
	}
#endif

#ifdef CONFIG_MIPS_BOSPORUS
	pm_power_off = bosporus_power_off;
	_machine_halt = bosporus_power_off;
	_machine_restart = (void(*)(char *))mips_softreset;
#endif
	au_sync();
}

static int __init db1x00_init_irq(void)
{
#if defined(CONFIG_MIPS_MIRAGE)
	irq_set_irq_type(AU1500_GPIO7_INT, IRQF_TRIGGER_RISING); /* TS pendown */
#elif defined(CONFIG_MIPS_DB1550)
	irq_set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW);  /* CD0# */
	irq_set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW);  /* CD1# */
	irq_set_irq_type(AU1550_GPIO3_INT, IRQF_TRIGGER_LOW);  /* CARD0# */
	irq_set_irq_type(AU1550_GPIO5_INT, IRQF_TRIGGER_LOW);  /* CARD1# */
	irq_set_irq_type(AU1550_GPIO21_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
	irq_set_irq_type(AU1550_GPIO22_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
#elif defined(CONFIG_MIPS_DB1500)
	irq_set_irq_type(AU1500_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
	irq_set_irq_type(AU1500_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
	irq_set_irq_type(AU1500_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
	irq_set_irq_type(AU1500_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
	irq_set_irq_type(AU1500_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
	irq_set_irq_type(AU1500_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
#elif defined(CONFIG_MIPS_DB1100)
	irq_set_irq_type(AU1100_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
	irq_set_irq_type(AU1100_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
	irq_set_irq_type(AU1100_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
	irq_set_irq_type(AU1100_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
	irq_set_irq_type(AU1100_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
	irq_set_irq_type(AU1100_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
#elif defined(CONFIG_MIPS_DB1000)
	irq_set_irq_type(AU1000_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
	irq_set_irq_type(AU1000_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
	irq_set_irq_type(AU1000_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
	irq_set_irq_type(AU1000_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
	irq_set_irq_type(AU1000_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
	irq_set_irq_type(AU1000_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
#endif
	return 0;
}
arch_initcall(db1x00_init_irq);
Commit	Line	Data
1da177e4 LT	1	/*
	2	*
	3	* BRIEF MODULE DESCRIPTION
	4	* Alchemy Db1x00 board setup.
	5	*
abd14cc0 SS	6	* Copyright 2000, 2008 MontaVista Software Inc.
abd14cc0 SS	7	* Author: MontaVista Software, Inc. <source@mvista.com>
1da177e4 LT	8	*
	9	* This program is free software; you can redistribute it and/or modify it
	10	* under the terms of the GNU General Public License as published by the
	11	* Free Software Foundation; either version 2 of the License, or (at your
	12	* option) any later version.
	13	*
	14	* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
	15	* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
	16	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
	17	* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
	18	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
	19	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
	20	* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
	21	* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	22	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
	23	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	24	*
	25	* You should have received a copy of the GNU General Public License along
	26	* with this program; if not, write to the Free Software Foundation, Inc.,
	27	* 675 Mass Ave, Cambridge, MA 02139, USA.
	28	*/
ce28f94c	29
ce65cc8f	30	#include <linux/gpio.h>
1da177e4	31	#include <linux/init.h>
7e50b2b7	32	#include <linux/interrupt.h>
32fd6901	33	#include <linux/pm.h>
1da177e4	34
1da177e4	35	#include <asm/mach-au1x00/au1000.h>
66f75ccb	36	#include <asm/mach-au1x00/au1xxx_eth.h>
1da177e4	37	#include <asm/mach-db1x00/db1x00.h>
9bdcf336	38	#include <asm/mach-db1x00/bcsr.h>
32fd6901	39	#include <asm/reboot.h>
1da177e4	40
7179380e ML	41	#include <prom.h>
7179380e ML	42
7e50b2b7 ML	43	#ifdef CONFIG_MIPS_DB1500
7e50b2b7 ML	44	char irq_tab_alchemy[][5] __initdata = {
78814465 ML	45	[12] = { -1, AU1500_PCI_INTA, 0xff, 0xff, 0xff }, /* IDSEL 12 - HPT371 */
78814465 ML	46	[13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, AU1500_PCI_INTC, AU1500_PCI_INTD }, /* IDSEL 13 - PCI slot */
7e50b2b7	47	};
32fd6901	48
570cb456	49	#endif
32fd6901	50
570cb456 ML	51
	52	#ifdef CONFIG_MIPS_DB1550
	53	char irq_tab_alchemy[][5] __initdata = {
	54	[11] = { -1, AU1550_PCI_INTC, 0xff, 0xff, 0xff }, /* IDSEL 11 - on-board HPT371 */
	55	[12] = { -1, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD, AU1550_PCI_INTA }, /* IDSEL 12 - PCI slot 2 (left) */
	56	[13] = { -1, AU1550_PCI_INTA, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD }, /* IDSEL 13 - PCI slot 1 (right) */
	57	};
7e50b2b7 ML	58	#endif
7e50b2b7 ML	59
570cb456 ML	60
	61	#ifdef CONFIG_MIPS_BOSPORUS
	62	char irq_tab_alchemy[][5] __initdata = {
	63	[11] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 11 - miniPCI */
	64	[12] = { -1, AU1500_PCI_INTA, 0xff, 0xff, 0xff }, /* IDSEL 12 - SN1741 */
	65	[13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, AU1500_PCI_INTC, AU1500_PCI_INTD }, /* IDSEL 13 - PCI slot */
	66	};
	67
66f75ccb FF	68	/*
	69	* Micrel/Kendin 5 port switch attached to MAC0,
	70	* MAC0 is associated with PHY address 5 (== WAN port)
	71	* MAC1 is not associated with any PHY, since it's connected directly
	72	* to the switch.
	73	* no interrupts are used
	74	*/
	75	static struct au1000_eth_platform_data eth0_pdata = {
	76	.phy_static_config = 1,
	77	.phy_addr = 5,
	78	};
	79
570cb456 ML	80	static void bosporus_power_off(void)
570cb456 ML	81	{
570cb456 ML	82	while (1)
	83	asm volatile (".set mips3 ; wait ; .set mips0");
	84	}
66f75ccb	85
570cb456 ML	86	const char *get_system_type(void)
	87	{
	88	return "Alchemy Bosporus Gateway Reference";
	89	}
7e50b2b7 ML	90	#endif
7e50b2b7 ML	91
570cb456	92
7e50b2b7 ML	93	#ifdef CONFIG_MIPS_MIRAGE
7e50b2b7 ML	94	char irq_tab_alchemy[][5] __initdata = {
78814465 ML	95	[11] = { -1, AU1500_PCI_INTD, 0xff, 0xff, 0xff }, /* IDSEL 11 - SMI VGX */
	96	[12] = { -1, 0xff, 0xff, AU1500_PCI_INTC, 0xff }, /* IDSEL 12 - PNX1300 */
	97	[13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 13 - miniPCI */
7e50b2b7	98	};
32fd6901 ML	99
	100	static void mirage_power_off(void)
	101	{
	102	alchemy_gpio_direction_output(210, 1);
	103	}
	104
	105	const char *get_system_type(void)
	106	{
	107	return "Alchemy Mirage";
	108	}
7e50b2b7 ML	109	#endif
7e50b2b7 ML	110
7e50b2b7	111
32fd6901 ML	112	#if defined(CONFIG_MIPS_BOSPORUS) \|\| defined(CONFIG_MIPS_MIRAGE)
32fd6901 ML	113	static void mips_softreset(void)
23ba25d5	114	{
32fd6901	115	asm volatile ("jr\t%0" : : "r"(0xbfc00000));
23ba25d5 ML	116	}
23ba25d5 ML	117
32fd6901 ML	118	#else
	119
	120	const char *get_system_type(void)
1da177e4	121	{
32fd6901	122	return "Alchemy Db1x00";
1da177e4	123	}
32fd6901	124	#endif
1da177e4	125
570cb456	126
1da177e4 LT	127	void __init board_setup(void)
1da177e4 LT	128	{
9bdcf336	129	unsigned long bcsr1, bcsr2;
7179380e	130
9bdcf336 ML	131	bcsr1 = DB1000_BCSR_PHYS_ADDR;
	132	bcsr2 = DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS;
	133
	134	#ifdef CONFIG_MIPS_DB1000
	135	printk(KERN_INFO "AMD Alchemy Au1000/Db1000 Board\n");
	136	#endif
	137	#ifdef CONFIG_MIPS_DB1500
	138	printk(KERN_INFO "AMD Alchemy Au1500/Db1500 Board\n");
	139	#endif
	140	#ifdef CONFIG_MIPS_DB1100
	141	printk(KERN_INFO "AMD Alchemy Au1100/Db1100 Board\n");
	142	#endif
	143	#ifdef CONFIG_MIPS_BOSPORUS
66f75ccb FF	144	au1xxx_override_eth_cfg(0, &eth0_pdata);
66f75ccb FF	145
9bdcf336 ML	146	printk(KERN_INFO "AMD Alchemy Bosporus Board\n");
	147	#endif
	148	#ifdef CONFIG_MIPS_MIRAGE
	149	printk(KERN_INFO "AMD Alchemy Mirage Board\n");
	150	#endif
	151	#ifdef CONFIG_MIPS_DB1550
	152	printk(KERN_INFO "AMD Alchemy Au1550/Db1550 Board\n");
	153
	154	bcsr1 = DB1550_BCSR_PHYS_ADDR;
	155	bcsr2 = DB1550_BCSR_PHYS_ADDR + DB1550_BCSR_HEXLED_OFS;
	156	#endif
	157
	158	/* initialize board register space */
	159	bcsr_init(bcsr1, bcsr2);
	160
abd14cc0 SS	161	/* Not valid for Au1550 */
	162	#if defined(CONFIG_IRDA) && \
	163	(defined(CONFIG_SOC_AU1000) \|\| defined(CONFIG_SOC_AU1100))
403fbdff RB	164	{
	165	u32 pin_func;
	166
	167	/* Set IRFIRSEL instead of GPIO15 */
	168	pin_func = au_readl(SYS_PINFUNC) \| SYS_PF_IRF;
	169	au_writel(pin_func, SYS_PINFUNC);
	170	/* Power off until the driver is in use */
	171	bcsr_mod(BCSR_RESETS, BCSR_RESETS_IRDA_MODE_MASK,
	172	BCSR_RESETS_IRDA_MODE_OFF);
	173	}
1da177e4	174	#endif
9bdcf336	175	bcsr_write(BCSR_PCMCIA, 0); /* turn off PCMCIA power */
1da177e4	176
abd14cc0	177	/* Enable GPIO[31:0] inputs */
ce65cc8f	178	alchemy_gpio1_input_enable();
1da177e4	179
ce65cc8f	180	#ifdef CONFIG_MIPS_MIRAGE
403fbdff RB	181	{
403fbdff RB	182	u32 pin_func;
1da177e4	183
403fbdff RB	184	/* GPIO[20] is output */
403fbdff RB	185	alchemy_gpio_direction_output(20, 0);
1da177e4	186
403fbdff RB	187	/* Set GPIO[210:208] instead of SSI_0 */
403fbdff RB	188	pin_func = au_readl(SYS_PINFUNC) \| SYS_PF_S0;
1da177e4	189
403fbdff RB	190	/* Set GPIO[215:211] for LEDs */
403fbdff RB	191	pin_func \|= 5 << 2;
1da177e4	192
403fbdff RB	193	/* Set GPIO[214:213] for more LEDs */
403fbdff RB	194	pin_func \|= 5 << 12;
1da177e4	195
403fbdff RB	196	/* Set GPIO[207:200] instead of PCMCIA/LCD */
	197	pin_func \|= SYS_PF_LCD \| SYS_PF_PC;
	198	au_writel(pin_func, SYS_PINFUNC);
32fd6901	199
403fbdff RB	200	/*
	201	* Enable speaker amplifier. This should
	202	* be part of the audio driver.
	203	*/
	204	alchemy_gpio_direction_output(209, 1);
	205
	206	pm_power_off = mirage_power_off;
	207	_machine_halt = mirage_power_off;
	208	_machine_restart = (void()(char ))mips_softreset;
	209	}
1da177e4 LT	210	#endif
1da177e4 LT	211
32fd6901 ML	212	#ifdef CONFIG_MIPS_BOSPORUS
	213	pm_power_off = bosporus_power_off;
	214	_machine_halt = bosporus_power_off;
	215	_machine_restart = (void()(char ))mips_softreset;
	216	#endif
1da177e4	217	au_sync();
1da177e4	218	}
7e50b2b7 ML	219
	220	static int __init db1x00_init_irq(void)
	221	{
	222	#if defined(CONFIG_MIPS_MIRAGE)
e4ec7989	223	irq_set_irq_type(AU1500_GPIO7_INT, IRQF_TRIGGER_RISING); /* TS pendown */
7e50b2b7	224	#elif defined(CONFIG_MIPS_DB1550)
e4ec7989 TG	225	irq_set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
	226	irq_set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW); /* CD1# */
	227	irq_set_irq_type(AU1550_GPIO3_INT, IRQF_TRIGGER_LOW); /* CARD0# */
	228	irq_set_irq_type(AU1550_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
	229	irq_set_irq_type(AU1550_GPIO21_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
	230	irq_set_irq_type(AU1550_GPIO22_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
78814465	231	#elif defined(CONFIG_MIPS_DB1500)
e4ec7989 TG	232	irq_set_irq_type(AU1500_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
	233	irq_set_irq_type(AU1500_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
	234	irq_set_irq_type(AU1500_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
	235	irq_set_irq_type(AU1500_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
	236	irq_set_irq_type(AU1500_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
	237	irq_set_irq_type(AU1500_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
78814465	238	#elif defined(CONFIG_MIPS_DB1100)
e4ec7989 TG	239	irq_set_irq_type(AU1100_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
	240	irq_set_irq_type(AU1100_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
	241	irq_set_irq_type(AU1100_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
	242	irq_set_irq_type(AU1100_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
	243	irq_set_irq_type(AU1100_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
	244	irq_set_irq_type(AU1100_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
78814465	245	#elif defined(CONFIG_MIPS_DB1000)
e4ec7989 TG	246	irq_set_irq_type(AU1000_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
	247	irq_set_irq_type(AU1000_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
	248	irq_set_irq_type(AU1000_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
	249	irq_set_irq_type(AU1000_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
	250	irq_set_irq_type(AU1000_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
	251	irq_set_irq_type(AU1000_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
7e50b2b7 ML	252	#endif
	253	return 0;
	254	}
	255	arch_initcall(db1x00_init_irq);