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2c572c28 | 1 | /* |
dc95be1f MS |
2 | * Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu> |
3 | * Copyright (C) 2007-2009 PetaLogix | |
2c572c28 MS |
4 | * Copyright (C) 2006 Atmark Techno, Inc. |
5 | * | |
6 | * This file is subject to the terms and conditions of the GNU General Public | |
7 | * License. See the file "COPYING" in the main directory of this archive | |
8 | * for more details. | |
9 | */ | |
10 | ||
11 | #ifndef _ASM_MICROBLAZE_IO_H | |
12 | #define _ASM_MICROBLAZE_IO_H | |
13 | ||
14 | #include <asm/byteorder.h> | |
15 | #include <asm/page.h> | |
16 | #include <linux/types.h> | |
dc95be1f MS |
17 | #include <linux/mm.h> /* Get struct page {...} */ |
18 | ||
2c572c28 MS |
19 | |
20 | #define IO_SPACE_LIMIT (0xFFFFFFFF) | |
21 | ||
22 | static inline unsigned char __raw_readb(const volatile void __iomem *addr) | |
23 | { | |
24 | return *(volatile unsigned char __force *)addr; | |
25 | } | |
26 | static inline unsigned short __raw_readw(const volatile void __iomem *addr) | |
27 | { | |
28 | return *(volatile unsigned short __force *)addr; | |
29 | } | |
30 | static inline unsigned int __raw_readl(const volatile void __iomem *addr) | |
31 | { | |
32 | return *(volatile unsigned int __force *)addr; | |
33 | } | |
34 | static inline unsigned long __raw_readq(const volatile void __iomem *addr) | |
35 | { | |
36 | return *(volatile unsigned long __force *)addr; | |
37 | } | |
38 | static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr) | |
39 | { | |
40 | *(volatile unsigned char __force *)addr = v; | |
41 | } | |
42 | static inline void __raw_writew(unsigned short v, volatile void __iomem *addr) | |
43 | { | |
44 | *(volatile unsigned short __force *)addr = v; | |
45 | } | |
46 | static inline void __raw_writel(unsigned int v, volatile void __iomem *addr) | |
47 | { | |
48 | *(volatile unsigned int __force *)addr = v; | |
49 | } | |
50 | static inline void __raw_writeq(unsigned long v, volatile void __iomem *addr) | |
51 | { | |
52 | *(volatile unsigned long __force *)addr = v; | |
53 | } | |
54 | ||
55 | /* | |
56 | * read (readb, readw, readl, readq) and write (writeb, writew, | |
57 | * writel, writeq) accessors are for PCI and thus littel endian. | |
58 | * Linux 2.4 for Microblaze had this wrong. | |
59 | */ | |
60 | static inline unsigned char readb(const volatile void __iomem *addr) | |
61 | { | |
62 | return *(volatile unsigned char __force *)addr; | |
63 | } | |
64 | static inline unsigned short readw(const volatile void __iomem *addr) | |
65 | { | |
66 | return le16_to_cpu(*(volatile unsigned short __force *)addr); | |
67 | } | |
68 | static inline unsigned int readl(const volatile void __iomem *addr) | |
69 | { | |
70 | return le32_to_cpu(*(volatile unsigned int __force *)addr); | |
71 | } | |
72 | static inline void writeb(unsigned char v, volatile void __iomem *addr) | |
73 | { | |
74 | *(volatile unsigned char __force *)addr = v; | |
75 | } | |
76 | static inline void writew(unsigned short v, volatile void __iomem *addr) | |
77 | { | |
78 | *(volatile unsigned short __force *)addr = cpu_to_le16(v); | |
79 | } | |
80 | static inline void writel(unsigned int v, volatile void __iomem *addr) | |
81 | { | |
82 | *(volatile unsigned int __force *)addr = cpu_to_le32(v); | |
83 | } | |
84 | ||
85 | /* ioread and iowrite variants. thease are for now same as __raw_ | |
86 | * variants of accessors. we might check for endianess in the feature | |
87 | */ | |
88 | #define ioread8(addr) __raw_readb((u8 *)(addr)) | |
89 | #define ioread16(addr) __raw_readw((u16 *)(addr)) | |
90 | #define ioread32(addr) __raw_readl((u32 *)(addr)) | |
91 | #define iowrite8(v, addr) __raw_writeb((u8)(v), (u8 *)(addr)) | |
92 | #define iowrite16(v, addr) __raw_writew((u16)(v), (u16 *)(addr)) | |
93 | #define iowrite32(v, addr) __raw_writel((u32)(v), (u32 *)(addr)) | |
94 | ||
95 | /* These are the definitions for the x86 IO instructions | |
96 | * inb/inw/inl/outb/outw/outl, the "string" versions | |
97 | * insb/insw/insl/outsb/outsw/outsl, and the "pausing" versions | |
98 | * inb_p/inw_p/... | |
99 | * The macros don't do byte-swapping. | |
100 | */ | |
101 | #define inb(port) readb((u8 *)((port))) | |
102 | #define outb(val, port) writeb((val), (u8 *)((unsigned long)(port))) | |
103 | #define inw(port) readw((u16 *)((port))) | |
104 | #define outw(val, port) writew((val), (u16 *)((unsigned long)(port))) | |
105 | #define inl(port) readl((u32 *)((port))) | |
106 | #define outl(val, port) writel((val), (u32 *)((unsigned long)(port))) | |
107 | ||
108 | #define inb_p(port) inb((port)) | |
109 | #define outb_p(val, port) outb((val), (port)) | |
110 | #define inw_p(port) inw((port)) | |
111 | #define outw_p(val, port) outw((val), (port)) | |
112 | #define inl_p(port) inl((port)) | |
113 | #define outl_p(val, port) outl((val), (port)) | |
114 | ||
115 | #define memset_io(a, b, c) memset((void *)(a), (b), (c)) | |
116 | #define memcpy_fromio(a, b, c) memcpy((a), (void *)(b), (c)) | |
117 | #define memcpy_toio(a, b, c) memcpy((void *)(a), (b), (c)) | |
118 | ||
dc95be1f MS |
119 | #ifdef CONFIG_MMU |
120 | ||
121 | #define mm_ptov(addr) ((void *)__phys_to_virt(addr)) | |
122 | #define mm_vtop(addr) ((unsigned long)__virt_to_phys(addr)) | |
123 | #define phys_to_virt(addr) ((void *)__phys_to_virt(addr)) | |
124 | #define virt_to_phys(addr) ((unsigned long)__virt_to_phys(addr)) | |
125 | #define virt_to_bus(addr) ((unsigned long)__virt_to_phys(addr)) | |
126 | ||
127 | #define __page_address(page) \ | |
128 | (PAGE_OFFSET + (((page) - mem_map) << PAGE_SHIFT)) | |
129 | #define page_to_phys(page) virt_to_phys((void *)__page_address(page)) | |
130 | #define page_to_bus(page) (page_to_phys(page)) | |
131 | #define bus_to_virt(addr) (phys_to_virt(addr)) | |
132 | ||
133 | extern void iounmap(void *addr); | |
134 | /*extern void *__ioremap(phys_addr_t address, unsigned long size, | |
135 | unsigned long flags);*/ | |
136 | extern void __iomem *ioremap(phys_addr_t address, unsigned long size); | |
137 | #define ioremap_writethrough(addr, size) ioremap((addr), (size)) | |
138 | #define ioremap_nocache(addr, size) ioremap((addr), (size)) | |
139 | #define ioremap_fullcache(addr, size) ioremap((addr), (size)) | |
140 | ||
141 | #else /* CONFIG_MMU */ | |
142 | ||
2c572c28 MS |
143 | /** |
144 | * virt_to_phys - map virtual addresses to physical | |
145 | * @address: address to remap | |
146 | * | |
147 | * The returned physical address is the physical (CPU) mapping for | |
148 | * the memory address given. It is only valid to use this function on | |
149 | * addresses directly mapped or allocated via kmalloc. | |
150 | * | |
151 | * This function does not give bus mappings for DMA transfers. In | |
152 | * almost all conceivable cases a device driver should not be using | |
153 | * this function | |
154 | */ | |
155 | static inline unsigned long __iomem virt_to_phys(volatile void *address) | |
156 | { | |
157 | return __pa((unsigned long)address); | |
158 | } | |
159 | ||
160 | #define virt_to_bus virt_to_phys | |
161 | ||
162 | /** | |
163 | * phys_to_virt - map physical address to virtual | |
164 | * @address: address to remap | |
165 | * | |
166 | * The returned virtual address is a current CPU mapping for | |
167 | * the memory address given. It is only valid to use this function on | |
168 | * addresses that have a kernel mapping | |
169 | * | |
170 | * This function does not handle bus mappings for DMA transfers. In | |
171 | * almost all conceivable cases a device driver should not be using | |
172 | * this function | |
173 | */ | |
174 | static inline void *phys_to_virt(unsigned long address) | |
175 | { | |
176 | return (void *)__va(address); | |
177 | } | |
178 | ||
179 | #define bus_to_virt(a) phys_to_virt(a) | |
180 | ||
181 | static inline void __iomem *__ioremap(phys_addr_t address, unsigned long size, | |
182 | unsigned long flags) | |
183 | { | |
184 | return (void *)address; | |
185 | } | |
186 | ||
187 | #define ioremap(physaddr, size) ((void __iomem *)(unsigned long)(physaddr)) | |
188 | #define iounmap(addr) ((void)0) | |
189 | #define ioremap_nocache(physaddr, size) ioremap(physaddr, size) | |
190 | ||
dc95be1f MS |
191 | #endif /* CONFIG_MMU */ |
192 | ||
2c572c28 MS |
193 | /* |
194 | * Convert a physical pointer to a virtual kernel pointer for /dev/mem | |
195 | * access | |
196 | */ | |
197 | #define xlate_dev_mem_ptr(p) __va(p) | |
198 | ||
199 | /* | |
200 | * Convert a virtual cached pointer to an uncached pointer | |
201 | */ | |
202 | #define xlate_dev_kmem_ptr(p) p | |
203 | ||
204 | /* | |
205 | * Big Endian | |
206 | */ | |
207 | #define out_be32(a, v) __raw_writel((v), (void __iomem __force *)(a)) | |
208 | #define out_be16(a, v) __raw_writew((v), (a)) | |
209 | ||
210 | #define in_be32(a) __raw_readl((const void __iomem __force *)(a)) | |
211 | #define in_be16(a) __raw_readw(a) | |
212 | ||
afc26cb3 JZ |
213 | #define writel_be(v, a) out_be32((__force unsigned *)a, v) |
214 | #define readl_be(a) in_be32((__force unsigned *)a) | |
215 | ||
2c572c28 MS |
216 | /* |
217 | * Little endian | |
218 | */ | |
219 | ||
220 | #define out_le32(a, v) __raw_writel(__cpu_to_le32(v), (a)); | |
221 | #define out_le16(a, v) __raw_writew(__cpu_to_le16(v), (a)) | |
222 | ||
223 | #define in_le32(a) __le32_to_cpu(__raw_readl(a)) | |
224 | #define in_le16(a) __le16_to_cpu(__raw_readw(a)) | |
225 | ||
226 | /* Byte ops */ | |
227 | #define out_8(a, v) __raw_writeb((v), (a)) | |
228 | #define in_8(a) __raw_readb(a) | |
229 | ||
230 | /* FIXME */ | |
231 | static inline void __iomem *ioport_map(unsigned long port, unsigned int len) | |
232 | { | |
233 | return (void __iomem *) (port); | |
234 | } | |
235 | ||
236 | static inline void ioport_unmap(void __iomem *addr) | |
237 | { | |
238 | /* Nothing to do */ | |
239 | } | |
240 | ||
241 | #endif /* _ASM_MICROBLAZE_IO_H */ |