[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / m68k / include / asm / system.h

#ifndef _M68K_SYSTEM_H
#define _M68K_SYSTEM_H

#include <linux/linkage.h>
#include <linux/kernel.h>
#include <linux/bug.h>
#include <linux/irqflags.h>
#include <asm/segment.h>
#include <asm/entry.h>

#ifdef __KERNEL__

/*
 * switch_to(n) should switch tasks to task ptr, first checking that
 * ptr isn't the current task, in which case it does nothing.  This
 * also clears the TS-flag if the task we switched to has used the
 * math co-processor latest.
 */
/*
 * switch_to() saves the extra registers, that are not saved
 * automatically by SAVE_SWITCH_STACK in resume(), ie. d0-d5 and
 * a0-a1. Some of these are used by schedule() and its predecessors
 * and so we might get see unexpected behaviors when a task returns
 * with unexpected register values.
 *
 * syscall stores these registers itself and none of them are used
 * by syscall after the function in the syscall has been called.
 *
 * Beware that resume now expects *next to be in d1 and the offset of
 * tss to be in a1. This saves a few instructions as we no longer have
 * to push them onto the stack and read them back right after.
 *
 * 02/17/96 - Jes Sorensen (jds@kom.auc.dk)
 *
 * Changed 96/09/19 by Andreas Schwab
 * pass prev in a0, next in a1
 */
asmlinkage void resume(void);
#define switch_to(prev,next,last) do { \
  register void *_prev __asm__ ("a0") = (prev); \
  register void *_next __asm__ ("a1") = (next); \
  register void *_last __asm__ ("d1"); \
  __asm__ __volatile__("jbsr resume" \
		       : "=a" (_prev), "=a" (_next), "=d" (_last) \
		       : "0" (_prev), "1" (_next) \
		       : "d0", "d2", "d3", "d4", "d5"); \
  (last) = _last; \
} while (0)


/*
 * Force strict CPU ordering.
 * Not really required on m68k...
 */
#define nop()		do { asm volatile ("nop"); barrier(); } while (0)
#define mb()		barrier()
#define rmb()		barrier()
#define wmb()		barrier()
#define read_barrier_depends()	((void)0)
#define set_mb(var, value)	({ (var) = (value); wmb(); })

#define smp_mb()	barrier()
#define smp_rmb()	barrier()
#define smp_wmb()	barrier()
#define smp_read_barrier_depends()	((void)0)

#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))

struct __xchg_dummy { unsigned long a[100]; };
#define __xg(x) ((volatile struct __xchg_dummy *)(x))

#ifndef CONFIG_RMW_INSNS
static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
{
	unsigned long flags, tmp;

	local_irq_save(flags);

	switch (size) {
	case 1:
		tmp = *(u8 *)ptr;
		*(u8 *)ptr = x;
		x = tmp;
		break;
	case 2:
		tmp = *(u16 *)ptr;
		*(u16 *)ptr = x;
		x = tmp;
		break;
	case 4:
		tmp = *(u32 *)ptr;
		*(u32 *)ptr = x;
		x = tmp;
		break;
	default:
		BUG();
	}

	local_irq_restore(flags);
	return x;
}
#else
static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
{
	switch (size) {
	    case 1:
		__asm__ __volatile__
			("moveb %2,%0\n\t"
			 "1:\n\t"
			 "casb %0,%1,%2\n\t"
			 "jne 1b"
			 : "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory");
		break;
	    case 2:
		__asm__ __volatile__
			("movew %2,%0\n\t"
			 "1:\n\t"
			 "casw %0,%1,%2\n\t"
			 "jne 1b"
			 : "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory");
		break;
	    case 4:
		__asm__ __volatile__
			("movel %2,%0\n\t"
			 "1:\n\t"
			 "casl %0,%1,%2\n\t"
			 "jne 1b"
			 : "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory");
		break;
	}
	return x;
}
#endif

#include <asm-generic/cmpxchg-local.h>

#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))

/*
 * Atomic compare and exchange.  Compare OLD with MEM, if identical,
 * store NEW in MEM.  Return the initial value in MEM.  Success is
 * indicated by comparing RETURN with OLD.
 */
#ifdef CONFIG_RMW_INSNS
#define __HAVE_ARCH_CMPXCHG	1

static inline unsigned long __cmpxchg(volatile void *p, unsigned long old,
				      unsigned long new, int size)
{
	switch (size) {
	case 1:
		__asm__ __volatile__ ("casb %0,%2,%1"
				      : "=d" (old), "=m" (*(char *)p)
				      : "d" (new), "0" (old), "m" (*(char *)p));
		break;
	case 2:
		__asm__ __volatile__ ("casw %0,%2,%1"
				      : "=d" (old), "=m" (*(short *)p)
				      : "d" (new), "0" (old), "m" (*(short *)p));
		break;
	case 4:
		__asm__ __volatile__ ("casl %0,%2,%1"
				      : "=d" (old), "=m" (*(int *)p)
				      : "d" (new), "0" (old), "m" (*(int *)p));
		break;
	}
	return old;
}

#define cmpxchg(ptr, o, n)						    \
	((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(o),	    \
			(unsigned long)(n), sizeof(*(ptr))))
#define cmpxchg_local(ptr, o, n)					    \
	((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(o),	    \
			(unsigned long)(n), sizeof(*(ptr))))
#else

/*
 * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
 * them available.
 */
#define cmpxchg_local(ptr, o, n)				  	       \
	((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\
			(unsigned long)(n), sizeof(*(ptr))))

#include <asm-generic/cmpxchg.h>

#endif

#define arch_align_stack(x) (x)

#endif /* __KERNEL__ */

#endif /* _M68K_SYSTEM_H */
Commit	Line	Data
f941f5ca GU	1	#ifndef _M68K_SYSTEM_H
	2	#define _M68K_SYSTEM_H
	3
	4	#include <linux/linkage.h>
	5	#include <linux/kernel.h>
187f1882	6	#include <linux/bug.h>
f941f5ca GU	7	#include <linux/irqflags.h>
	8	#include <asm/segment.h>
	9	#include <asm/entry.h>
	10
	11	#ifdef __KERNEL__
	12
	13	/*
	14	* switch_to(n) should switch tasks to task ptr, first checking that
	15	* ptr isn't the current task, in which case it does nothing. This
	16	* also clears the TS-flag if the task we switched to has used the
	17	* math co-processor latest.
	18	*/
	19	/*
	20	* switch_to() saves the extra registers, that are not saved
	21	* automatically by SAVE_SWITCH_STACK in resume(), ie. d0-d5 and
	22	* a0-a1. Some of these are used by schedule() and its predecessors
	23	* and so we might get see unexpected behaviors when a task returns
	24	* with unexpected register values.
	25	*
	26	* syscall stores these registers itself and none of them are used
	27	* by syscall after the function in the syscall has been called.
	28	*
	29	* Beware that resume now expects *next to be in d1 and the offset of
	30	* tss to be in a1. This saves a few instructions as we no longer have
	31	* to push them onto the stack and read them back right after.
	32	*
	33	* 02/17/96 - Jes Sorensen (jds@kom.auc.dk)
	34	*
	35	* Changed 96/09/19 by Andreas Schwab
	36	* pass prev in a0, next in a1
	37	*/
	38	asmlinkage void resume(void);
	39	#define switch_to(prev,next,last) do { \
	40	register void *_prev __asm__ ("a0") = (prev); \
	41	register void *_next __asm__ ("a1") = (next); \
	42	register void *_last __asm__ ("d1"); \
	43	__asm__ __volatile__("jbsr resume" \
	44	: "=a" (_prev), "=a" (_next), "=d" (_last) \
	45	: "0" (_prev), "1" (_next) \
	46	: "d0", "d2", "d3", "d4", "d5"); \
	47	(last) = _last; \
	48	} while (0)
	49
	50
	51	/*
	52	* Force strict CPU ordering.
	53	* Not really required on m68k...
	54	*/
	55	#define nop() do { asm volatile ("nop"); barrier(); } while (0)
	56	#define mb() barrier()
	57	#define rmb() barrier()
	58	#define wmb() barrier()
	59	#define read_barrier_depends() ((void)0)
	60	#define set_mb(var, value) ({ (var) = (value); wmb(); })
	61
	62	#define smp_mb() barrier()
	63	#define smp_rmb() barrier()
	64	#define smp_wmb() barrier()
	65	#define smp_read_barrier_depends() ((void)0)
	66
	67	#define xchg(ptr,x) ((__typeof__((ptr)))__xchg((unsigned long)(x),(ptr),sizeof((ptr))))
	68
	69	struct __xchg_dummy { unsigned long a[100]; };
	70	#define __xg(x) ((volatile struct __xchg_dummy *)(x))
71
72	#ifndef CONFIG_RMW_INSNS
73	static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
74	{
75	unsigned long flags, tmp;
76
77	local_irq_save(flags);
78
79	switch (size) {
80	case 1:
81	tmp = (u8 )ptr;
82	(u8 )ptr = x;
83	x = tmp;
84	break;
85	case 2:
86	tmp = (u16 )ptr;
87	(u16 )ptr = x;
88	x = tmp;
89	break;
90	case 4:
91	tmp = (u32 )ptr;
92	(u32 )ptr = x;
93	x = tmp;
94	break;
95	default:
96	BUG();
97	}
98
99	local_irq_restore(flags);
100	return x;
101	}
49148020	102	#else
f941f5ca GU	103	static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
	104	{
	105	switch (size) {
	106	case 1:
	107	__asm__ __volatile__
	108	("moveb %2,%0\n\t"
	109	"1:\n\t"
	110	"casb %0,%1,%2\n\t"
	111	"jne 1b"
	112	: "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory");
	113	break;
	114	case 2:
	115	__asm__ __volatile__
	116	("movew %2,%0\n\t"
	117	"1:\n\t"
	118	"casw %0,%1,%2\n\t"
	119	"jne 1b"
	120	: "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory");
	121	break;
	122	case 4:
	123	__asm__ __volatile__
	124	("movel %2,%0\n\t"
	125	"1:\n\t"
	126	"casl %0,%1,%2\n\t"
	127	"jne 1b"
	128	: "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory");
	129	break;
	130	}
	131	return x;
	132	}
49148020	133	#endif
f941f5ca GU	134
	135	#include <asm-generic/cmpxchg-local.h>
	136
	137	#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
	138
	139	/*
	140	* Atomic compare and exchange. Compare OLD with MEM, if identical,
	141	* store NEW in MEM. Return the initial value in MEM. Success is
	142	* indicated by comparing RETURN with OLD.
	143	*/
	144	#ifdef CONFIG_RMW_INSNS
	145	#define __HAVE_ARCH_CMPXCHG 1
	146
	147	static inline unsigned long __cmpxchg(volatile void *p, unsigned long old,
	148	unsigned long new, int size)
	149	{
	150	switch (size) {
	151	case 1:
	152	__asm__ __volatile__ ("casb %0,%2,%1"
	153	: "=d" (old), "=m" ((char )p)
	154	: "d" (new), "0" (old), "m" ((char )p));
	155	break;
	156	case 2:
	157	__asm__ __volatile__ ("casw %0,%2,%1"
	158	: "=d" (old), "=m" ((short )p)
	159	: "d" (new), "0" (old), "m" ((short )p));
	160	break;
	161	case 4:
	162	__asm__ __volatile__ ("casl %0,%2,%1"
	163	: "=d" (old), "=m" ((int )p)
	164	: "d" (new), "0" (old), "m" ((int )p));
	165	break;
	166	}
	167	return old;
	168	}
	169
	170	#define cmpxchg(ptr, o, n) \
	171	((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(o), \
	172	(unsigned long)(n), sizeof(*(ptr))))
	173	#define cmpxchg_local(ptr, o, n) \
	174	((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(o), \
	175	(unsigned long)(n), sizeof(*(ptr))))
	176	#else
	177
	178	/*
	179	* cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
	180	* them available.
	181	*/
	182	#define cmpxchg_local(ptr, o, n) \
	183	((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\
	184	(unsigned long)(n), sizeof(*(ptr))))
	185
	186	#include <asm-generic/cmpxchg.h>
	187
	188	#endif
	189
	190	#define arch_align_stack(x) (x)
	191
	192	#endif /* __KERNEL__ */
	193
	194	#endif /* _M68K_SYSTEM_H */