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1da177e4 LT |
1 | /****************************************************************************/ |
2 | ||
3 | /* | |
4 | * m527xsim.h -- ColdFire 5270/5271 System Integration Module support. | |
5 | * | |
6 | * (C) Copyright 2004, Greg Ungerer (gerg@snapgear.com) | |
7 | */ | |
8 | ||
9 | /****************************************************************************/ | |
10 | #ifndef m527xsim_h | |
11 | #define m527xsim_h | |
12 | /****************************************************************************/ | |
13 | ||
733f31b7 GU |
14 | #define CPU_NAME "COLDFIRE(m527x)" |
15 | #define CPU_INSTR_PER_JIFFY 3 | |
7fc82b65 | 16 | |
a12cf0a8 | 17 | #include <asm/m52xxacr.h> |
1da177e4 LT |
18 | |
19 | /* | |
20 | * Define the 5270/5271 SIM register set addresses. | |
21 | */ | |
22 | #define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */ | |
23 | #define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 1 */ | |
24 | #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ | |
25 | #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ | |
26 | #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ | |
27 | #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ | |
28 | #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ | |
29 | #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ | |
30 | #define MCFINTC_IRLR 0x18 /* */ | |
31 | #define MCFINTC_IACKL 0x19 /* */ | |
32 | #define MCFINTC_ICR0 0x40 /* Base ICR register */ | |
33 | ||
34 | #define MCFINT_VECBASE 64 /* Vector base number */ | |
35 | #define MCFINT_UART0 13 /* Interrupt number for UART0 */ | |
36 | #define MCFINT_UART1 14 /* Interrupt number for UART1 */ | |
37 | #define MCFINT_UART2 15 /* Interrupt number for UART2 */ | |
91d60417 | 38 | #define MCFINT_QSPI 18 /* Interrupt number for QSPI */ |
1da177e4 LT |
39 | #define MCFINT_PIT1 36 /* Interrupt number for PIT1 */ |
40 | ||
41 | /* | |
42 | * SDRAM configuration registers. | |
43 | */ | |
d871629b | 44 | #ifdef CONFIG_M5271 |
1da177e4 LT |
45 | #define MCFSIM_DCR 0x40 /* SDRAM control */ |
46 | #define MCFSIM_DACR0 0x48 /* SDRAM base address 0 */ | |
47 | #define MCFSIM_DMR0 0x4c /* SDRAM address mask 0 */ | |
48 | #define MCFSIM_DACR1 0x50 /* SDRAM base address 1 */ | |
49 | #define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */ | |
d871629b GU |
50 | #endif |
51 | #ifdef CONFIG_M5275 | |
1da177e4 LT |
52 | #define MCFSIM_DMR 0x40 /* SDRAM mode */ |
53 | #define MCFSIM_DCR 0x44 /* SDRAM control */ | |
54 | #define MCFSIM_DCFG1 0x48 /* SDRAM configuration 1 */ | |
55 | #define MCFSIM_DCFG2 0x4c /* SDRAM configuration 2 */ | |
56 | #define MCFSIM_DBAR0 0x50 /* SDRAM base address 0 */ | |
57 | #define MCFSIM_DMR0 0x54 /* SDRAM address mask 0 */ | |
58 | #define MCFSIM_DBAR1 0x58 /* SDRAM base address 1 */ | |
59 | #define MCFSIM_DMR1 0x5c /* SDRAM address mask 1 */ | |
60 | #endif | |
61 | ||
57015421 GU |
62 | /* |
63 | * UART module. | |
64 | */ | |
65 | #define MCFUART_BASE1 0x200 /* Base address of UART1 */ | |
66 | #define MCFUART_BASE2 0x240 /* Base address of UART2 */ | |
67 | #define MCFUART_BASE3 0x280 /* Base address of UART3 */ | |
f1554da3 | 68 | |
69 | #ifdef CONFIG_M5271 | |
70 | #define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000) | |
71 | #define MCFGPIO_PODR_DATAH (MCF_IPSBAR + 0x100001) | |
72 | #define MCFGPIO_PODR_DATAL (MCF_IPSBAR + 0x100002) | |
73 | #define MCFGPIO_PODR_BUSCTL (MCF_IPSBAR + 0x100003) | |
74 | #define MCFGPIO_PODR_BS (MCF_IPSBAR + 0x100004) | |
75 | #define MCFGPIO_PODR_CS (MCF_IPSBAR + 0x100005) | |
76 | #define MCFGPIO_PODR_SDRAM (MCF_IPSBAR + 0x100006) | |
77 | #define MCFGPIO_PODR_FECI2C (MCF_IPSBAR + 0x100007) | |
78 | #define MCFGPIO_PODR_UARTH (MCF_IPSBAR + 0x100008) | |
79 | #define MCFGPIO_PODR_UARTL (MCF_IPSBAR + 0x100009) | |
80 | #define MCFGPIO_PODR_QSPI (MCF_IPSBAR + 0x10000A) | |
81 | #define MCFGPIO_PODR_TIMER (MCF_IPSBAR + 0x10000B) | |
82 | ||
83 | #define MCFGPIO_PDDR_ADDR (MCF_IPSBAR + 0x100010) | |
84 | #define MCFGPIO_PDDR_DATAH (MCF_IPSBAR + 0x100011) | |
85 | #define MCFGPIO_PDDR_DATAL (MCF_IPSBAR + 0x100012) | |
86 | #define MCFGPIO_PDDR_BUSCTL (MCF_IPSBAR + 0x100013) | |
87 | #define MCFGPIO_PDDR_BS (MCF_IPSBAR + 0x100014) | |
88 | #define MCFGPIO_PDDR_CS (MCF_IPSBAR + 0x100015) | |
89 | #define MCFGPIO_PDDR_SDRAM (MCF_IPSBAR + 0x100016) | |
90 | #define MCFGPIO_PDDR_FECI2C (MCF_IPSBAR + 0x100017) | |
91 | #define MCFGPIO_PDDR_UARTH (MCF_IPSBAR + 0x100018) | |
92 | #define MCFGPIO_PDDR_UARTL (MCF_IPSBAR + 0x100019) | |
93 | #define MCFGPIO_PDDR_QSPI (MCF_IPSBAR + 0x10001A) | |
94 | #define MCFGPIO_PDDR_TIMER (MCF_IPSBAR + 0x10001B) | |
95 | ||
96 | #define MCFGPIO_PPDSDR_ADDR (MCF_IPSBAR + 0x100020) | |
97 | #define MCFGPIO_PPDSDR_DATAH (MCF_IPSBAR + 0x100021) | |
98 | #define MCFGPIO_PPDSDR_DATAL (MCF_IPSBAR + 0x100022) | |
99 | #define MCFGPIO_PPDSDR_BUSCTL (MCF_IPSBAR + 0x100023) | |
100 | #define MCFGPIO_PPDSDR_BS (MCF_IPSBAR + 0x100024) | |
101 | #define MCFGPIO_PPDSDR_CS (MCF_IPSBAR + 0x100025) | |
102 | #define MCFGPIO_PPDSDR_SDRAM (MCF_IPSBAR + 0x100026) | |
103 | #define MCFGPIO_PPDSDR_FECI2C (MCF_IPSBAR + 0x100027) | |
104 | #define MCFGPIO_PPDSDR_UARTH (MCF_IPSBAR + 0x100028) | |
105 | #define MCFGPIO_PPDSDR_UARTL (MCF_IPSBAR + 0x100029) | |
106 | #define MCFGPIO_PPDSDR_QSPI (MCF_IPSBAR + 0x10002A) | |
107 | #define MCFGPIO_PPDSDR_TIMER (MCF_IPSBAR + 0x10002B) | |
108 | ||
109 | #define MCFGPIO_PCLRR_ADDR (MCF_IPSBAR + 0x100030) | |
110 | #define MCFGPIO_PCLRR_DATAH (MCF_IPSBAR + 0x100031) | |
111 | #define MCFGPIO_PCLRR_DATAL (MCF_IPSBAR + 0x100032) | |
112 | #define MCFGPIO_PCLRR_BUSCTL (MCF_IPSBAR + 0x100033) | |
113 | #define MCFGPIO_PCLRR_BS (MCF_IPSBAR + 0x100034) | |
114 | #define MCFGPIO_PCLRR_CS (MCF_IPSBAR + 0x100035) | |
115 | #define MCFGPIO_PCLRR_SDRAM (MCF_IPSBAR + 0x100036) | |
116 | #define MCFGPIO_PCLRR_FECI2C (MCF_IPSBAR + 0x100037) | |
117 | #define MCFGPIO_PCLRR_UARTH (MCF_IPSBAR + 0x100038) | |
118 | #define MCFGPIO_PCLRR_UARTL (MCF_IPSBAR + 0x100039) | |
119 | #define MCFGPIO_PCLRR_QSPI (MCF_IPSBAR + 0x10003A) | |
120 | #define MCFGPIO_PCLRR_TIMER (MCF_IPSBAR + 0x10003B) | |
121 | ||
122 | /* | |
123 | * Generic GPIO support | |
124 | */ | |
125 | #define MCFGPIO_PODR MCFGPIO_PODR_ADDR | |
126 | #define MCFGPIO_PDDR MCFGPIO_PDDR_ADDR | |
127 | #define MCFGPIO_PPDR MCFGPIO_PPDSDR_ADDR | |
128 | #define MCFGPIO_SETR MCFGPIO_PPDSDR_ADDR | |
129 | #define MCFGPIO_CLRR MCFGPIO_PCLRR_ADDR | |
130 | ||
131 | #define MCFGPIO_PIN_MAX 100 | |
132 | #define MCFGPIO_IRQ_MAX 8 | |
133 | #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE | |
91d60417 SK |
134 | |
135 | #define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10004A) | |
136 | #define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10004C) | |
f1554da3 | 137 | #endif |
138 | ||
139 | #ifdef CONFIG_M5275 | |
140 | #define MCFGPIO_PODR_BUSCTL (MCF_IPSBAR + 0x100004) | |
141 | #define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100005) | |
142 | #define MCFGPIO_PODR_CS (MCF_IPSBAR + 0x100008) | |
143 | #define MCFGPIO_PODR_FEC0H (MCF_IPSBAR + 0x10000A) | |
144 | #define MCFGPIO_PODR_FEC0L (MCF_IPSBAR + 0x10000B) | |
145 | #define MCFGPIO_PODR_FECI2C (MCF_IPSBAR + 0x10000C) | |
146 | #define MCFGPIO_PODR_QSPI (MCF_IPSBAR + 0x10000D) | |
147 | #define MCFGPIO_PODR_SDRAM (MCF_IPSBAR + 0x10000E) | |
148 | #define MCFGPIO_PODR_TIMERH (MCF_IPSBAR + 0x10000F) | |
149 | #define MCFGPIO_PODR_TIMERL (MCF_IPSBAR + 0x100010) | |
150 | #define MCFGPIO_PODR_UARTL (MCF_IPSBAR + 0x100011) | |
151 | #define MCFGPIO_PODR_FEC1H (MCF_IPSBAR + 0x100012) | |
152 | #define MCFGPIO_PODR_FEC1L (MCF_IPSBAR + 0x100013) | |
153 | #define MCFGPIO_PODR_BS (MCF_IPSBAR + 0x100014) | |
154 | #define MCFGPIO_PODR_IRQ (MCF_IPSBAR + 0x100015) | |
155 | #define MCFGPIO_PODR_USBH (MCF_IPSBAR + 0x100016) | |
156 | #define MCFGPIO_PODR_USBL (MCF_IPSBAR + 0x100017) | |
157 | #define MCFGPIO_PODR_UARTH (MCF_IPSBAR + 0x100018) | |
158 | ||
159 | #define MCFGPIO_PDDR_BUSCTL (MCF_IPSBAR + 0x100020) | |
160 | #define MCFGPIO_PDDR_ADDR (MCF_IPSBAR + 0x100021) | |
161 | #define MCFGPIO_PDDR_CS (MCF_IPSBAR + 0x100024) | |
162 | #define MCFGPIO_PDDR_FEC0H (MCF_IPSBAR + 0x100026) | |
163 | #define MCFGPIO_PDDR_FEC0L (MCF_IPSBAR + 0x100027) | |
164 | #define MCFGPIO_PDDR_FECI2C (MCF_IPSBAR + 0x100028) | |
165 | #define MCFGPIO_PDDR_QSPI (MCF_IPSBAR + 0x100029) | |
166 | #define MCFGPIO_PDDR_SDRAM (MCF_IPSBAR + 0x10002A) | |
167 | #define MCFGPIO_PDDR_TIMERH (MCF_IPSBAR + 0x10002B) | |
168 | #define MCFGPIO_PDDR_TIMERL (MCF_IPSBAR + 0x10002C) | |
169 | #define MCFGPIO_PDDR_UARTL (MCF_IPSBAR + 0x10002D) | |
170 | #define MCFGPIO_PDDR_FEC1H (MCF_IPSBAR + 0x10002E) | |
171 | #define MCFGPIO_PDDR_FEC1L (MCF_IPSBAR + 0x10002F) | |
172 | #define MCFGPIO_PDDR_BS (MCF_IPSBAR + 0x100030) | |
173 | #define MCFGPIO_PDDR_IRQ (MCF_IPSBAR + 0x100031) | |
174 | #define MCFGPIO_PDDR_USBH (MCF_IPSBAR + 0x100032) | |
175 | #define MCFGPIO_PDDR_USBL (MCF_IPSBAR + 0x100033) | |
176 | #define MCFGPIO_PDDR_UARTH (MCF_IPSBAR + 0x100034) | |
177 | ||
178 | #define MCFGPIO_PPDSDR_BUSCTL (MCF_IPSBAR + 0x10003C) | |
179 | #define MCFGPIO_PPDSDR_ADDR (MCF_IPSBAR + 0x10003D) | |
180 | #define MCFGPIO_PPDSDR_CS (MCF_IPSBAR + 0x100040) | |
181 | #define MCFGPIO_PPDSDR_FEC0H (MCF_IPSBAR + 0x100042) | |
182 | #define MCFGPIO_PPDSDR_FEC0L (MCF_IPSBAR + 0x100043) | |
183 | #define MCFGPIO_PPDSDR_FECI2C (MCF_IPSBAR + 0x100044) | |
184 | #define MCFGPIO_PPDSDR_QSPI (MCF_IPSBAR + 0x100045) | |
185 | #define MCFGPIO_PPDSDR_SDRAM (MCF_IPSBAR + 0x100046) | |
186 | #define MCFGPIO_PPDSDR_TIMERH (MCF_IPSBAR + 0x100047) | |
187 | #define MCFGPIO_PPDSDR_TIMERL (MCF_IPSBAR + 0x100048) | |
188 | #define MCFGPIO_PPDSDR_UARTL (MCF_IPSBAR + 0x100049) | |
189 | #define MCFGPIO_PPDSDR_FEC1H (MCF_IPSBAR + 0x10004A) | |
190 | #define MCFGPIO_PPDSDR_FEC1L (MCF_IPSBAR + 0x10004B) | |
191 | #define MCFGPIO_PPDSDR_BS (MCF_IPSBAR + 0x10004C) | |
192 | #define MCFGPIO_PPDSDR_IRQ (MCF_IPSBAR + 0x10004D) | |
193 | #define MCFGPIO_PPDSDR_USBH (MCF_IPSBAR + 0x10004E) | |
194 | #define MCFGPIO_PPDSDR_USBL (MCF_IPSBAR + 0x10004F) | |
195 | #define MCFGPIO_PPDSDR_UARTH (MCF_IPSBAR + 0x100050) | |
196 | ||
197 | #define MCFGPIO_PCLRR_BUSCTL (MCF_IPSBAR + 0x100058) | |
198 | #define MCFGPIO_PCLRR_ADDR (MCF_IPSBAR + 0x100059) | |
199 | #define MCFGPIO_PCLRR_CS (MCF_IPSBAR + 0x10005C) | |
200 | #define MCFGPIO_PCLRR_FEC0H (MCF_IPSBAR + 0x10005E) | |
201 | #define MCFGPIO_PCLRR_FEC0L (MCF_IPSBAR + 0x10005F) | |
202 | #define MCFGPIO_PCLRR_FECI2C (MCF_IPSBAR + 0x100060) | |
203 | #define MCFGPIO_PCLRR_QSPI (MCF_IPSBAR + 0x100061) | |
204 | #define MCFGPIO_PCLRR_SDRAM (MCF_IPSBAR + 0x100062) | |
205 | #define MCFGPIO_PCLRR_TIMERH (MCF_IPSBAR + 0x100063) | |
206 | #define MCFGPIO_PCLRR_TIMERL (MCF_IPSBAR + 0x100064) | |
207 | #define MCFGPIO_PCLRR_UARTL (MCF_IPSBAR + 0x100065) | |
208 | #define MCFGPIO_PCLRR_FEC1H (MCF_IPSBAR + 0x100066) | |
209 | #define MCFGPIO_PCLRR_FEC1L (MCF_IPSBAR + 0x100067) | |
210 | #define MCFGPIO_PCLRR_BS (MCF_IPSBAR + 0x100068) | |
211 | #define MCFGPIO_PCLRR_IRQ (MCF_IPSBAR + 0x100069) | |
212 | #define MCFGPIO_PCLRR_USBH (MCF_IPSBAR + 0x10006A) | |
213 | #define MCFGPIO_PCLRR_USBL (MCF_IPSBAR + 0x10006B) | |
214 | #define MCFGPIO_PCLRR_UARTH (MCF_IPSBAR + 0x10006C) | |
215 | ||
216 | ||
217 | /* | |
218 | * Generic GPIO support | |
219 | */ | |
220 | #define MCFGPIO_PODR MCFGPIO_PODR_BUSCTL | |
221 | #define MCFGPIO_PDDR MCFGPIO_PDDR_BUSCTL | |
222 | #define MCFGPIO_PPDR MCFGPIO_PPDSDR_BUSCTL | |
223 | #define MCFGPIO_SETR MCFGPIO_PPDSDR_BUSCTL | |
224 | #define MCFGPIO_CLRR MCFGPIO_PCLRR_BUSCTL | |
225 | ||
226 | #define MCFGPIO_PIN_MAX 148 | |
227 | #define MCFGPIO_IRQ_MAX 8 | |
228 | #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE | |
91d60417 SK |
229 | |
230 | #define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10007E) | |
f1554da3 | 231 | #endif |
232 | ||
233 | /* | |
234 | * EPort | |
235 | */ | |
236 | ||
237 | #define MCFEPORT_EPDDR (MCF_IPSBAR + 0x130002) | |
238 | #define MCFEPORT_EPDR (MCF_IPSBAR + 0x130004) | |
239 | #define MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005) | |
240 | ||
241 | ||
91d60417 | 242 | |
d871629b GU |
243 | /* |
244 | * GPIO pins setups to enable the UARTs. | |
245 | */ | |
246 | #ifdef CONFIG_M5271 | |
247 | #define MCF_GPIO_PAR_UART 0x100048 /* PAR UART address */ | |
248 | #define UART0_ENABLE_MASK 0x000f | |
249 | #define UART1_ENABLE_MASK 0x0ff0 | |
250 | #define UART2_ENABLE_MASK 0x3000 | |
251 | #endif | |
252 | #ifdef CONFIG_M5275 | |
253 | #define MCF_GPIO_PAR_UART 0x10007c /* PAR UART address */ | |
254 | #define UART0_ENABLE_MASK 0x000f | |
255 | #define UART1_ENABLE_MASK 0x00f0 | |
256 | #define UART2_ENABLE_MASK 0x3f00 | |
257 | #endif | |
258 | ||
4c0b008d GU |
259 | /* |
260 | * Reset Controll Unit (relative to IPSBAR). | |
261 | */ | |
262 | #define MCF_RCR 0x110000 | |
263 | #define MCF_RSR 0x110001 | |
264 | ||
265 | #define MCF_RCR_SWRESET 0x80 /* Software reset bit */ | |
266 | #define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ | |
267 | ||
1da177e4 LT |
268 | /****************************************************************************/ |
269 | #endif /* m527xsim_h */ |