[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / ia64 / sn / kernel / io_init.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1992 - 1997, 2000-2006 Silicon Graphics, Inc. All rights reserved.
 */

#include <asm/sn/types.h>
#include <asm/sn/addrs.h>
#include <asm/sn/io.h>
#include <asm/sn/module.h>
#include <asm/sn/intr.h>
#include <asm/sn/pcibus_provider_defs.h>
#include <asm/sn/pcidev.h>
#include <asm/sn/sn_sal.h>
#include "xtalk/hubdev.h"

/*
 * The code in this file will only be executed when running with
 * a PROM that does _not_ have base ACPI IO support.
 * (i.e., SN_ACPI_BASE_SUPPORT() == 0)
 */

static int max_segment_number;		 /* Default highest segment number */
static int max_pcibus_number = 255;	/* Default highest pci bus number */


/*
 * Retrieve the hub device info structure for the given nasid.
 */
static inline u64 sal_get_hubdev_info(u64 handle, u64 address)
{
	struct ia64_sal_retval ret_stuff;
	ret_stuff.status = 0;
	ret_stuff.v0 = 0;

	SAL_CALL_NOLOCK(ret_stuff,
			(u64) SN_SAL_IOIF_GET_HUBDEV_INFO,
			(u64) handle, (u64) address, 0, 0, 0, 0, 0);
	return ret_stuff.v0;
}

/*
 * Retrieve the pci bus information given the bus number.
 */
static inline u64 sal_get_pcibus_info(u64 segment, u64 busnum, u64 address)
{
	struct ia64_sal_retval ret_stuff;
	ret_stuff.status = 0;
	ret_stuff.v0 = 0;

	SAL_CALL_NOLOCK(ret_stuff,
			(u64) SN_SAL_IOIF_GET_PCIBUS_INFO,
			(u64) segment, (u64) busnum, (u64) address, 0, 0, 0, 0);
	return ret_stuff.v0;
}

/*
 * Retrieve the pci device information given the bus and device|function number.
 */
static inline u64
sal_get_pcidev_info(u64 segment, u64 bus_number, u64 devfn, u64 pci_dev,
		    u64 sn_irq_info)
{
	struct ia64_sal_retval ret_stuff;
	ret_stuff.status = 0;
	ret_stuff.v0 = 0;

	SAL_CALL_NOLOCK(ret_stuff,
			(u64) SN_SAL_IOIF_GET_PCIDEV_INFO,
			(u64) segment, (u64) bus_number, (u64) devfn,
			(u64) pci_dev,
			sn_irq_info, 0, 0);
	return ret_stuff.v0;
}


/*
 * sn_fixup_ionodes() - This routine initializes the HUB data structure for
 *			each node in the system. This function is only
 *			executed when running with a non-ACPI capable PROM.
 */
static void __init sn_fixup_ionodes(void)
{

	struct hubdev_info *hubdev;
	u64 status;
	u64 nasid;
	int i;
	extern void sn_common_hubdev_init(struct hubdev_info *);

	/*
	 * Get SGI Specific HUB chipset information.
	 * Inform Prom that this kernel can support domain bus numbering.
	 */
	for (i = 0; i < num_cnodes; i++) {
		hubdev = (struct hubdev_info *)(NODEPDA(i)->pdinfo);
		nasid = cnodeid_to_nasid(i);
		hubdev->max_segment_number = 0xffffffff;
		hubdev->max_pcibus_number = 0xff;
		status = sal_get_hubdev_info(nasid, (u64) __pa(hubdev));
		if (status)
			continue;

		/* Save the largest Domain and pcibus numbers found. */
		if (hubdev->max_segment_number) {
			/*
			 * Dealing with a Prom that supports segments.
			 */
			max_segment_number = hubdev->max_segment_number;
			max_pcibus_number = hubdev->max_pcibus_number;
		}
		sn_common_hubdev_init(hubdev);
	}
}

/*
 * sn_pci_legacy_window_fixup - Create PCI controller windows for
 *				legacy IO and MEM space. This needs to
 *				be done here, as the PROM does not have
 *				ACPI support defining the root buses
 *				and their resources (_CRS),
 */
static void
sn_legacy_pci_window_fixup(struct pci_controller *controller,
			   u64 legacy_io, u64 legacy_mem)
{
		controller->window = kcalloc(2, sizeof(struct pci_window),
					     GFP_KERNEL);
		if (controller->window == NULL)
			BUG();
		controller->window[0].offset = legacy_io;
		controller->window[0].resource.name = "legacy_io";
		controller->window[0].resource.flags = IORESOURCE_IO;
		controller->window[0].resource.start = legacy_io;
		controller->window[0].resource.end =
	    			controller->window[0].resource.start + 0xffff;
		controller->window[0].resource.parent = &ioport_resource;
		controller->window[1].offset = legacy_mem;
		controller->window[1].resource.name = "legacy_mem";
		controller->window[1].resource.flags = IORESOURCE_MEM;
		controller->window[1].resource.start = legacy_mem;
		controller->window[1].resource.end =
	    	       controller->window[1].resource.start + (1024 * 1024) - 1;
		controller->window[1].resource.parent = &iomem_resource;
		controller->windows = 2;
}

/*
 * sn_pci_window_fixup() - Create a pci_window for each device resource.
 *			   It will setup pci_windows for use by
 *			   pcibios_bus_to_resource(), pcibios_resource_to_bus(),
 *			   etc.
 */
static void
sn_pci_window_fixup(struct pci_dev *dev, unsigned int count,
		    s64 * pci_addrs)
{
	struct pci_controller *controller = PCI_CONTROLLER(dev->bus);
	unsigned int i;
	unsigned int idx;
	unsigned int new_count;
	struct pci_window *new_window;

	if (count == 0)
		return;
	idx = controller->windows;
	new_count = controller->windows + count;
	new_window = kcalloc(new_count, sizeof(struct pci_window), GFP_KERNEL);
	if (new_window == NULL)
		BUG();
	if (controller->window) {
		memcpy(new_window, controller->window,
		       sizeof(struct pci_window) * controller->windows);
		kfree(controller->window);
	}

	/* Setup a pci_window for each device resource. */
	for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
		if (pci_addrs[i] == -1)
			continue;

		new_window[idx].offset = dev->resource[i].start - pci_addrs[i];
		new_window[idx].resource = dev->resource[i];
		idx++;
	}

	controller->windows = new_count;
	controller->window = new_window;
}

/*
 * sn_io_slot_fixup() -   We are not running with an ACPI capable PROM,
 *			  and need to convert the pci_dev->resource
 *			  'start' and 'end' addresses to mapped addresses,
 *			  and setup the pci_controller->window array entries.
 */
void
sn_io_slot_fixup(struct pci_dev *dev)
{
	unsigned int count = 0;
	int idx;
	s64 pci_addrs[PCI_ROM_RESOURCE + 1];
	unsigned long addr, end, size, start;
	struct pcidev_info *pcidev_info;
	struct sn_irq_info *sn_irq_info;
	int status;

	pcidev_info = kzalloc(sizeof(struct pcidev_info), GFP_KERNEL);
	if (!pcidev_info)
		panic("%s: Unable to alloc memory for pcidev_info", __func__);

	sn_irq_info = kzalloc(sizeof(struct sn_irq_info), GFP_KERNEL);
	if (!sn_irq_info)
		panic("%s: Unable to alloc memory for sn_irq_info", __func__);

	/* Call to retrieve pci device information needed by kernel. */
	status = sal_get_pcidev_info((u64) pci_domain_nr(dev),
		(u64) dev->bus->number,
		dev->devfn,
		(u64) __pa(pcidev_info),
		(u64) __pa(sn_irq_info));

	if (status)
		BUG(); /* Cannot get platform pci device information */


	/* Copy over PIO Mapped Addresses */
	for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {

		if (!pcidev_info->pdi_pio_mapped_addr[idx]) {
			pci_addrs[idx] = -1;
			continue;
		}

		start = dev->resource[idx].start;
		end = dev->resource[idx].end;
		size = end - start;
		if (size == 0) {
			pci_addrs[idx] = -1;
			continue;
		}
		pci_addrs[idx] = start;
		count++;
		addr = pcidev_info->pdi_pio_mapped_addr[idx];
		addr = ((addr << 4) >> 4) | __IA64_UNCACHED_OFFSET;
		dev->resource[idx].start = addr;
		dev->resource[idx].end = addr + size;

		/*
		 * if it's already in the device structure, remove it before
		 * inserting
		 */
		if (dev->resource[idx].parent && dev->resource[idx].parent->child)
			release_resource(&dev->resource[idx]);

		if (dev->resource[idx].flags & IORESOURCE_IO)
			insert_resource(&ioport_resource, &dev->resource[idx]);
		else
			insert_resource(&iomem_resource, &dev->resource[idx]);
		/*
		 * If ROM, set the actual ROM image size, and mark as
		 * shadowed in PROM.
		 */
		if (idx == PCI_ROM_RESOURCE) {
			size_t image_size;
			void __iomem *rom;

			rom = ioremap(pci_resource_start(dev, PCI_ROM_RESOURCE),
				      size + 1);
			image_size = pci_get_rom_size(rom, size + 1);
			dev->resource[PCI_ROM_RESOURCE].end =
				dev->resource[PCI_ROM_RESOURCE].start +
				image_size - 1;
			dev->resource[PCI_ROM_RESOURCE].flags |=
						 IORESOURCE_ROM_BIOS_COPY;
		}
	}
	/* Create a pci_window in the pci_controller struct for
	 * each device resource.
	 */
	if (count > 0)
		sn_pci_window_fixup(dev, count, pci_addrs);

	sn_pci_fixup_slot(dev, pcidev_info, sn_irq_info);
}

EXPORT_SYMBOL(sn_io_slot_fixup);

/*
 * sn_pci_controller_fixup() - This routine sets up a bus's resources
 *			       consistent with the Linux PCI abstraction layer.
 */
static void __init
sn_pci_controller_fixup(int segment, int busnum, struct pci_bus *bus)
{
	s64 status = 0;
	struct pci_controller *controller;
	struct pcibus_bussoft *prom_bussoft_ptr;


 	status = sal_get_pcibus_info((u64) segment, (u64) busnum,
 				     (u64) ia64_tpa(&prom_bussoft_ptr));
 	if (status > 0)
		return;		/*bus # does not exist */
	prom_bussoft_ptr = __va(prom_bussoft_ptr);

	controller = kzalloc(sizeof(*controller), GFP_KERNEL);
	if (!controller)
		BUG();
	controller->segment = segment;

	/*
	 * Temporarily save the prom_bussoft_ptr for use by sn_bus_fixup().
	 * (platform_data will be overwritten later in sn_common_bus_fixup())
	 */
	controller->platform_data = prom_bussoft_ptr;

	bus = pci_scan_bus(busnum, &pci_root_ops, controller);
 	if (bus == NULL)
 		goto error_return; /* error, or bus already scanned */

	bus->sysdata = controller;

	return;

error_return:

	kfree(controller);
	return;
}

/*
 * sn_bus_fixup
 */
void
sn_bus_fixup(struct pci_bus *bus)
{
	struct pci_dev *pci_dev = NULL;
	struct pcibus_bussoft *prom_bussoft_ptr;

	if (!bus->parent) {  /* If root bus */
		prom_bussoft_ptr = PCI_CONTROLLER(bus)->platform_data;
		if (prom_bussoft_ptr == NULL) {
			printk(KERN_ERR
			       "sn_bus_fixup: 0x%04x:0x%02x Unable to "
			       "obtain prom_bussoft_ptr\n",
			       pci_domain_nr(bus), bus->number);
			return;
		}
		sn_common_bus_fixup(bus, prom_bussoft_ptr);
		sn_legacy_pci_window_fixup(PCI_CONTROLLER(bus),
					   prom_bussoft_ptr->bs_legacy_io,
					   prom_bussoft_ptr->bs_legacy_mem);
        }
        list_for_each_entry(pci_dev, &bus->devices, bus_list) {
                sn_io_slot_fixup(pci_dev);
        }

}

/*
 * sn_io_init - PROM does not have ACPI support to define nodes or root buses,
 *		so we need to do things the hard way, including initiating the
 *		bus scanning ourselves.
 */

void __init sn_io_init(void)
{
	int i, j;

	sn_fixup_ionodes();

	/* busses are not known yet ... */
	for (i = 0; i <= max_segment_number; i++)
		for (j = 0; j <= max_pcibus_number; j++)
			sn_pci_controller_fixup(i, j, NULL);
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
8ea6091f	6	* Copyright (C) 1992 - 1997, 2000-2006 Silicon Graphics, Inc. All rights reserved.
1da177e4 LT	7	*/
1da177e4 LT	8
1da177e4	9	#include <asm/sn/types.h>
1da177e4	10	#include <asm/sn/addrs.h>
1da177e4	11	#include <asm/sn/io.h>
f90aa8c4	12	#include <asm/sn/module.h>
8ea6091f	13	#include <asm/sn/intr.h>
c13cf371 PB	14	#include <asm/sn/pcibus_provider_defs.h>
c13cf371 PB	15	#include <asm/sn/pcidev.h>
c13cf371	16	#include <asm/sn/sn_sal.h>
c13cf371	17	#include "xtalk/hubdev.h"
674c6479	18
e955d825	19	/*
8ea6091f JK	20	* The code in this file will only be executed when running with
	21	* a PROM that does _not_ have base ACPI IO support.
	22	* (i.e., SN_ACPI_BASE_SUPPORT() == 0)
e955d825 MM	23	*/
e955d825 MM	24
8ea6091f JK	25	static int max_segment_number; /* Default highest segment number */
8ea6091f JK	26	static int max_pcibus_number = 255; /* Default highest pci bus number */
1da177e4	27
1da177e4 LT	28
	29	/*
	30	* Retrieve the hub device info structure for the given nasid.
	31	*/
6d6e4200	32	static inline u64 sal_get_hubdev_info(u64 handle, u64 address)
1da177e4	33	{
1da177e4 LT	34	struct ia64_sal_retval ret_stuff;
	35	ret_stuff.status = 0;
	36	ret_stuff.v0 = 0;
	37
	38	SAL_CALL_NOLOCK(ret_stuff,
	39	(u64) SN_SAL_IOIF_GET_HUBDEV_INFO,
	40	(u64) handle, (u64) address, 0, 0, 0, 0, 0);
	41	return ret_stuff.v0;
	42	}
	43
	44	/*
	45	* Retrieve the pci bus information given the bus number.
	46	*/
6d6e4200	47	static inline u64 sal_get_pcibus_info(u64 segment, u64 busnum, u64 address)
1da177e4	48	{
1da177e4 LT	49	struct ia64_sal_retval ret_stuff;
	50	ret_stuff.status = 0;
	51	ret_stuff.v0 = 0;
	52
	53	SAL_CALL_NOLOCK(ret_stuff,
	54	(u64) SN_SAL_IOIF_GET_PCIBUS_INFO,
	55	(u64) segment, (u64) busnum, (u64) address, 0, 0, 0, 0);
	56	return ret_stuff.v0;
	57	}
	58
6f09a925 JK	59	/*
	60	* Retrieve the pci device information given the bus and device\|function number.
	61	*/
	62	static inline u64
	63	sal_get_pcidev_info(u64 segment, u64 bus_number, u64 devfn, u64 pci_dev,
	64	u64 sn_irq_info)
	65	{
	66	struct ia64_sal_retval ret_stuff;
	67	ret_stuff.status = 0;
	68	ret_stuff.v0 = 0;
	69
	70	SAL_CALL_NOLOCK(ret_stuff,
	71	(u64) SN_SAL_IOIF_GET_PCIDEV_INFO,
	72	(u64) segment, (u64) bus_number, (u64) devfn,
	73	(u64) pci_dev,
	74	sn_irq_info, 0, 0);
	75	return ret_stuff.v0;
	76	}
	77
5f7f5b0c	78
1da177e4	79	/*
8ea6091f JK	80	* sn_fixup_ionodes() - This routine initializes the HUB data structure for
	81	* each node in the system. This function is only
	82	* executed when running with a non-ACPI capable PROM.
1da177e4	83	*/
2fcc3db0	84	static void __init sn_fixup_ionodes(void)
1da177e4	85	{
8ea6091f	86
1da177e4	87	struct hubdev_info *hubdev;
6d6e4200 PB	88	u64 status;
6d6e4200 PB	89	u64 nasid;
8ea6091f JK	90	int i;
8ea6091f JK	91	extern void sn_common_hubdev_init(struct hubdev_info *);
1da177e4	92
674c6479 CN	93	/*
	94	* Get SGI Specific HUB chipset information.
	95	* Inform Prom that this kernel can support domain bus numbering.
	96	*/
24ee0a6d	97	for (i = 0; i < num_cnodes; i++) {
1da177e4 LT	98	hubdev = (struct hubdev_info *)(NODEPDA(i)->pdinfo);
1da177e4 LT	99	nasid = cnodeid_to_nasid(i);
674c6479 CN	100	hubdev->max_segment_number = 0xffffffff;
674c6479 CN	101	hubdev->max_pcibus_number = 0xff;
6d6e4200	102	status = sal_get_hubdev_info(nasid, (u64) __pa(hubdev));
1da177e4 LT	103	if (status)
	104	continue;
	105
674c6479 CN	106	/* Save the largest Domain and pcibus numbers found. */
	107	if (hubdev->max_segment_number) {
	108	/*
	109	* Dealing with a Prom that supports segments.
	110	*/
	111	max_segment_number = hubdev->max_segment_number;
	112	max_pcibus_number = hubdev->max_pcibus_number;
	113	}
8ea6091f JK	114	sn_common_hubdev_init(hubdev);
	115	}
	116	}
674c6479	117
8ea6091f JK	118	/*
	119	* sn_pci_legacy_window_fixup - Create PCI controller windows for
	120	* legacy IO and MEM space. This needs to
	121	* be done here, as the PROM does not have
	122	* ACPI support defining the root buses
	123	* and their resources (_CRS),
	124	*/
	125	static void
	126	sn_legacy_pci_window_fixup(struct pci_controller *controller,
	127	u64 legacy_io, u64 legacy_mem)
	128	{
	129	controller->window = kcalloc(2, sizeof(struct pci_window),
	130	GFP_KERNEL);
	131	if (controller->window == NULL)
8ed9b2c7	132	BUG();
8ea6091f JK	133	controller->window[0].offset = legacy_io;
	134	controller->window[0].resource.name = "legacy_io";
	135	controller->window[0].resource.flags = IORESOURCE_IO;
	136	controller->window[0].resource.start = legacy_io;
	137	controller->window[0].resource.end =
	138	controller->window[0].resource.start + 0xffff;
	139	controller->window[0].resource.parent = &ioport_resource;
	140	controller->window[1].offset = legacy_mem;
	141	controller->window[1].resource.name = "legacy_mem";
	142	controller->window[1].resource.flags = IORESOURCE_MEM;
	143	controller->window[1].resource.start = legacy_mem;
	144	controller->window[1].resource.end =
	145	controller->window[1].resource.start + (1024 * 1024) - 1;
	146	controller->window[1].resource.parent = &iomem_resource;
	147	controller->windows = 2;
1da177e4 LT	148	}
1da177e4 LT	149
3ec829b6 JK	150	/*
3ec829b6 JK	151	* sn_pci_window_fixup() - Create a pci_window for each device resource.
8ea6091f JK	152	* It will setup pci_windows for use by
	153	* pcibios_bus_to_resource(), pcibios_resource_to_bus(),
	154	* etc.
3ec829b6 JK	155	*/
	156	static void
	157	sn_pci_window_fixup(struct pci_dev *dev, unsigned int count,
53493dcf	158	s64 * pci_addrs)
3ec829b6 JK	159	{
	160	struct pci_controller *controller = PCI_CONTROLLER(dev->bus);
	161	unsigned int i;
	162	unsigned int idx;
	163	unsigned int new_count;
	164	struct pci_window *new_window;
	165
	166	if (count == 0)
	167	return;
	168	idx = controller->windows;
	169	new_count = controller->windows + count;
	170	new_window = kcalloc(new_count, sizeof(struct pci_window), GFP_KERNEL);
	171	if (new_window == NULL)
	172	BUG();
	173	if (controller->window) {
	174	memcpy(new_window, controller->window,
	175	sizeof(struct pci_window) * controller->windows);
	176	kfree(controller->window);
	177	}
	178
	179	/* Setup a pci_window for each device resource. */
	180	for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
	181	if (pci_addrs[i] == -1)
	182	continue;
	183
	184	new_window[idx].offset = dev->resource[i].start - pci_addrs[i];
	185	new_window[idx].resource = dev->resource[i];
	186	idx++;
	187	}
	188
	189	controller->windows = new_count;
	190	controller->window = new_window;
	191	}
	192
1da177e4	193	/*
6f09a925	194	* sn_io_slot_fixup() - We are not running with an ACPI capable PROM,
8ea6091f JK	195	* and need to convert the pci_dev->resource
	196	* 'start' and 'end' addresses to mapped addresses,
	197	* and setup the pci_controller->window array entries.
1da177e4	198	*/
8ea6091f	199	void
6f09a925	200	sn_io_slot_fixup(struct pci_dev *dev)
1da177e4	201	{
3ec829b6	202	unsigned int count = 0;
1da177e4	203	int idx;
53493dcf	204	s64 pci_addrs[PCI_ROM_RESOURCE + 1];
8ea6091f	205	unsigned long addr, end, size, start;
6f09a925 JK	206	struct pcidev_info *pcidev_info;
	207	struct sn_irq_info *sn_irq_info;
	208	int status;
	209
	210	pcidev_info = kzalloc(sizeof(struct pcidev_info), GFP_KERNEL);
	211	if (!pcidev_info)
d4ed8084	212	panic("%s: Unable to alloc memory for pcidev_info", __func__);
6f09a925 JK	213
	214	sn_irq_info = kzalloc(sizeof(struct sn_irq_info), GFP_KERNEL);
	215	if (!sn_irq_info)
d4ed8084	216	panic("%s: Unable to alloc memory for sn_irq_info", __func__);
6f09a925 JK	217
	218	/* Call to retrieve pci device information needed by kernel. */
	219	status = sal_get_pcidev_info((u64) pci_domain_nr(dev),
	220	(u64) dev->bus->number,
	221	dev->devfn,
	222	(u64) __pa(pcidev_info),
	223	(u64) __pa(sn_irq_info));
	224
	225	if (status)
	226	BUG(); /* Cannot get platform pci device information */
	227
3ec829b6	228
1da177e4 LT	229	/* Copy over PIO Mapped Addresses */
1da177e4 LT	230	for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
1da177e4	231
3ec829b6 JK	232	if (!pcidev_info->pdi_pio_mapped_addr[idx]) {
3ec829b6 JK	233	pci_addrs[idx] = -1;
1da177e4	234	continue;
3ec829b6	235	}
1da177e4 LT	236
	237	start = dev->resource[idx].start;
	238	end = dev->resource[idx].end;
	239	size = end - start;
3ec829b6 JK	240	if (size == 0) {
	241	pci_addrs[idx] = -1;
	242	continue;
	243	}
	244	pci_addrs[idx] = start;
	245	count++;
	246	addr = pcidev_info->pdi_pio_mapped_addr[idx];
1da177e4 LT	247	addr = ((addr << 4) >> 4) \| __IA64_UNCACHED_OFFSET;
	248	dev->resource[idx].start = addr;
	249	dev->resource[idx].end = addr + size;
64715725 BW	250
	251	/*
	252	* if it's already in the device structure, remove it before
	253	* inserting
	254	*/
	255	if (dev->resource[idx].parent && dev->resource[idx].parent->child)
	256	release_resource(&dev->resource[idx]);
	257
1da177e4	258	if (dev->resource[idx].flags & IORESOURCE_IO)
64715725	259	insert_resource(&ioport_resource, &dev->resource[idx]);
1da177e4	260	else
64715725	261	insert_resource(&iomem_resource, &dev->resource[idx]);
d7ad2254 JK	262	/*
	263	* If ROM, set the actual ROM image size, and mark as
	264	* shadowed in PROM.
	265	*/
	266	if (idx == PCI_ROM_RESOURCE) {
	267	size_t image_size;
	268	void __iomem *rom;
	269
	270	rom = ioremap(pci_resource_start(dev, PCI_ROM_RESOURCE),
	271	size + 1);
	272	image_size = pci_get_rom_size(rom, size + 1);
	273	dev->resource[PCI_ROM_RESOURCE].end =
	274	dev->resource[PCI_ROM_RESOURCE].start +
	275	image_size - 1;
	276	dev->resource[PCI_ROM_RESOURCE].flags \|=
	277	IORESOURCE_ROM_BIOS_COPY;
	278	}
1da177e4	279	}
3ec829b6 JK	280	/* Create a pci_window in the pci_controller struct for
	281	* each device resource.
	282	*/
	283	if (count > 0)
	284	sn_pci_window_fixup(dev, count, pci_addrs);
6f09a925 JK	285
6f09a925 JK	286	sn_pci_fixup_slot(dev, pcidev_info, sn_irq_info);
1da177e4 LT	287	}
1da177e4 LT	288
6f09a925 JK	289	EXPORT_SYMBOL(sn_io_slot_fixup);
6f09a925 JK	290
1da177e4 LT	291	/*
1da177e4 LT	292	* sn_pci_controller_fixup() - This routine sets up a bus's resources
8ea6091f	293	* consistent with the Linux PCI abstraction layer.
1da177e4	294	*/
d3a307f3	295	static void __init
8ea6091f	296	sn_pci_controller_fixup(int segment, int busnum, struct pci_bus *bus)
1da177e4	297	{
8ea6091f	298	s64 status = 0;
1da177e4 LT	299	struct pci_controller *controller;
1da177e4 LT	300	struct pcibus_bussoft *prom_bussoft_ptr;
8ea6091f	301
1da177e4	302
6f354b01 PB	303	status = sal_get_pcibus_info((u64) segment, (u64) busnum,
	304	(u64) ia64_tpa(&prom_bussoft_ptr));
	305	if (status > 0)
	306	return; /bus # does not exist /
1da177e4	307	prom_bussoft_ptr = __va(prom_bussoft_ptr);
1da177e4	308
8ea6091f JK	309	controller = kzalloc(sizeof(*controller), GFP_KERNEL);
8ea6091f JK	310	if (!controller)
3ec829b6	311	BUG();
674c6479	312	controller->segment = segment;
6f354b01	313
1da177e4	314	/*
8ea6091f JK	315	* Temporarily save the prom_bussoft_ptr for use by sn_bus_fixup().
8ea6091f JK	316	* (platform_data will be overwritten later in sn_common_bus_fixup())
1da177e4	317	*/
8ea6091f	318	controller->platform_data = prom_bussoft_ptr;
1da177e4	319
8ea6091f JK	320	bus = pci_scan_bus(busnum, &pci_root_ops, controller);
	321	if (bus == NULL)
	322	goto error_return; /* error, or bus already scanned */
e955d825	323
c1ffb910	324	bus->sysdata = controller;
6f354b01 PB	325
	326	return;
	327
	328	error_return:
	329
8ea6091f	330	kfree(controller);
6f354b01 PB	331	return;
	332	}
	333
8ea6091f JK	334	/*
	335	* sn_bus_fixup
	336	*/
	337	void
	338	sn_bus_fixup(struct pci_bus *bus)
6f354b01	339	{
8ea6091f JK	340	struct pci_dev *pci_dev = NULL;
8ea6091f JK	341	struct pcibus_bussoft *prom_bussoft_ptr;
8ea6091f JK	342
	343	if (!bus->parent) { /* If root bus */
	344	prom_bussoft_ptr = PCI_CONTROLLER(bus)->platform_data;
	345	if (prom_bussoft_ptr == NULL) {
	346	printk(KERN_ERR
	347	"sn_bus_fixup: 0x%04x:0x%02x Unable to "
	348	"obtain prom_bussoft_ptr\n",
	349	pci_domain_nr(bus), bus->number);
	350	return;
	351	}
	352	sn_common_bus_fixup(bus, prom_bussoft_ptr);
	353	sn_legacy_pci_window_fixup(PCI_CONTROLLER(bus),
	354	prom_bussoft_ptr->bs_legacy_io,
	355	prom_bussoft_ptr->bs_legacy_mem);
	356	}
	357	list_for_each_entry(pci_dev, &bus->devices, bus_list) {
6f09a925	358	sn_io_slot_fixup(pci_dev);
8ea6091f	359	}
6f354b01	360
1da177e4 LT	361	}
	362
	363	/*
8ea6091f JK	364	* sn_io_init - PROM does not have ACPI support to define nodes or root buses,
	365	* so we need to do things the hard way, including initiating the
	366	* bus scanning ourselves.
1da177e4 LT	367	*/
1da177e4 LT	368
8ea6091f	369	void __init sn_io_init(void)
1da177e4	370	{
8ed9b2c7	371	int i, j;
e955d825	372
1da177e4	373	sn_fixup_ionodes();
1da177e4	374
6f354b01	375	/* busses are not known yet ... */
674c6479 CN	376	for (i = 0; i <= max_segment_number; i++)
	377	for (j = 0; j <= max_pcibus_number; j++)
	378	sn_pci_controller_fixup(i, j, NULL);
1da177e4	379	}