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1da177e4 LT |
1 | /* |
2 | * pci.c - Low-Level PCI Access in IA-64 | |
3 | * | |
4 | * Derived from bios32.c of i386 tree. | |
5 | * | |
6 | * (c) Copyright 2002, 2005 Hewlett-Packard Development Company, L.P. | |
7 | * David Mosberger-Tang <davidm@hpl.hp.com> | |
8 | * Bjorn Helgaas <bjorn.helgaas@hp.com> | |
9 | * Copyright (C) 2004 Silicon Graphics, Inc. | |
10 | * | |
11 | * Note: Above list of copyright holders is incomplete... | |
12 | */ | |
13 | #include <linux/config.h> | |
14 | ||
15 | #include <linux/acpi.h> | |
16 | #include <linux/types.h> | |
17 | #include <linux/kernel.h> | |
18 | #include <linux/pci.h> | |
19 | #include <linux/init.h> | |
20 | #include <linux/ioport.h> | |
21 | #include <linux/slab.h> | |
22 | #include <linux/smp_lock.h> | |
23 | #include <linux/spinlock.h> | |
24 | ||
25 | #include <asm/machvec.h> | |
26 | #include <asm/page.h> | |
1da177e4 LT |
27 | #include <asm/system.h> |
28 | #include <asm/io.h> | |
29 | #include <asm/sal.h> | |
30 | #include <asm/smp.h> | |
31 | #include <asm/irq.h> | |
32 | #include <asm/hw_irq.h> | |
33 | ||
34 | ||
1da177e4 LT |
35 | /* |
36 | * Low-level SAL-based PCI configuration access functions. Note that SAL | |
37 | * calls are already serialized (via sal_lock), so we don't need another | |
38 | * synchronization mechanism here. | |
39 | */ | |
40 | ||
41 | #define PCI_SAL_ADDRESS(seg, bus, devfn, reg) \ | |
42 | (((u64) seg << 24) | (bus << 16) | (devfn << 8) | (reg)) | |
43 | ||
44 | /* SAL 3.2 adds support for extended config space. */ | |
45 | ||
46 | #define PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg) \ | |
47 | (((u64) seg << 28) | (bus << 20) | (devfn << 12) | (reg)) | |
48 | ||
49 | static int | |
50 | pci_sal_read (unsigned int seg, unsigned int bus, unsigned int devfn, | |
51 | int reg, int len, u32 *value) | |
52 | { | |
53 | u64 addr, data = 0; | |
54 | int mode, result; | |
55 | ||
56 | if (!value || (seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095)) | |
57 | return -EINVAL; | |
58 | ||
59 | if ((seg | reg) <= 255) { | |
60 | addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg); | |
61 | mode = 0; | |
62 | } else { | |
63 | addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg); | |
64 | mode = 1; | |
65 | } | |
66 | result = ia64_sal_pci_config_read(addr, mode, len, &data); | |
67 | if (result != 0) | |
68 | return -EINVAL; | |
69 | ||
70 | *value = (u32) data; | |
71 | return 0; | |
72 | } | |
73 | ||
74 | static int | |
75 | pci_sal_write (unsigned int seg, unsigned int bus, unsigned int devfn, | |
76 | int reg, int len, u32 value) | |
77 | { | |
78 | u64 addr; | |
79 | int mode, result; | |
80 | ||
81 | if ((seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095)) | |
82 | return -EINVAL; | |
83 | ||
84 | if ((seg | reg) <= 255) { | |
85 | addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg); | |
86 | mode = 0; | |
87 | } else { | |
88 | addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg); | |
89 | mode = 1; | |
90 | } | |
91 | result = ia64_sal_pci_config_write(addr, mode, len, value); | |
92 | if (result != 0) | |
93 | return -EINVAL; | |
94 | return 0; | |
95 | } | |
96 | ||
97 | static struct pci_raw_ops pci_sal_ops = { | |
98 | .read = pci_sal_read, | |
99 | .write = pci_sal_write | |
100 | }; | |
101 | ||
102 | struct pci_raw_ops *raw_pci_ops = &pci_sal_ops; | |
103 | ||
104 | static int | |
105 | pci_read (struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value) | |
106 | { | |
107 | return raw_pci_ops->read(pci_domain_nr(bus), bus->number, | |
108 | devfn, where, size, value); | |
109 | } | |
110 | ||
111 | static int | |
112 | pci_write (struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value) | |
113 | { | |
114 | return raw_pci_ops->write(pci_domain_nr(bus), bus->number, | |
115 | devfn, where, size, value); | |
116 | } | |
117 | ||
118 | struct pci_ops pci_root_ops = { | |
119 | .read = pci_read, | |
120 | .write = pci_write, | |
121 | }; | |
122 | ||
1da177e4 LT |
123 | /* Called by ACPI when it finds a new root bus. */ |
124 | ||
125 | static struct pci_controller * __devinit | |
126 | alloc_pci_controller (int seg) | |
127 | { | |
128 | struct pci_controller *controller; | |
129 | ||
130 | controller = kmalloc(sizeof(*controller), GFP_KERNEL); | |
131 | if (!controller) | |
132 | return NULL; | |
133 | ||
134 | memset(controller, 0, sizeof(*controller)); | |
135 | controller->segment = seg; | |
514604c6 | 136 | controller->node = -1; |
1da177e4 LT |
137 | return controller; |
138 | } | |
139 | ||
140 | static u64 __devinit | |
141 | add_io_space (struct acpi_resource_address64 *addr) | |
142 | { | |
143 | u64 offset; | |
144 | int sparse = 0; | |
145 | int i; | |
146 | ||
147 | if (addr->address_translation_offset == 0) | |
148 | return IO_SPACE_BASE(0); /* part of legacy IO space */ | |
149 | ||
150 | if (addr->attribute.io.translation_attribute == ACPI_SPARSE_TRANSLATION) | |
151 | sparse = 1; | |
152 | ||
153 | offset = (u64) ioremap(addr->address_translation_offset, 0); | |
154 | for (i = 0; i < num_io_spaces; i++) | |
155 | if (io_space[i].mmio_base == offset && | |
156 | io_space[i].sparse == sparse) | |
157 | return IO_SPACE_BASE(i); | |
158 | ||
159 | if (num_io_spaces == MAX_IO_SPACES) { | |
160 | printk("Too many IO port spaces\n"); | |
161 | return ~0; | |
162 | } | |
163 | ||
164 | i = num_io_spaces++; | |
165 | io_space[i].mmio_base = offset; | |
166 | io_space[i].sparse = sparse; | |
167 | ||
168 | return IO_SPACE_BASE(i); | |
169 | } | |
170 | ||
463eb297 BH |
171 | static acpi_status __devinit resource_to_window(struct acpi_resource *resource, |
172 | struct acpi_resource_address64 *addr) | |
173 | { | |
174 | acpi_status status; | |
175 | ||
176 | /* | |
177 | * We're only interested in _CRS descriptors that are | |
178 | * - address space descriptors for memory or I/O space | |
179 | * - non-zero size | |
180 | * - producers, i.e., the address space is routed downstream, | |
181 | * not consumed by the bridge itself | |
182 | */ | |
183 | status = acpi_resource_to_address64(resource, addr); | |
184 | if (ACPI_SUCCESS(status) && | |
185 | (addr->resource_type == ACPI_MEMORY_RANGE || | |
186 | addr->resource_type == ACPI_IO_RANGE) && | |
187 | addr->address_length && | |
188 | addr->producer_consumer == ACPI_PRODUCER) | |
189 | return AE_OK; | |
190 | ||
191 | return AE_ERROR; | |
192 | } | |
193 | ||
1da177e4 LT |
194 | static acpi_status __devinit |
195 | count_window (struct acpi_resource *resource, void *data) | |
196 | { | |
197 | unsigned int *windows = (unsigned int *) data; | |
198 | struct acpi_resource_address64 addr; | |
199 | acpi_status status; | |
200 | ||
463eb297 | 201 | status = resource_to_window(resource, &addr); |
1da177e4 | 202 | if (ACPI_SUCCESS(status)) |
463eb297 | 203 | (*windows)++; |
1da177e4 LT |
204 | |
205 | return AE_OK; | |
206 | } | |
207 | ||
208 | struct pci_root_info { | |
209 | struct pci_controller *controller; | |
210 | char *name; | |
211 | }; | |
212 | ||
213 | static __devinit acpi_status add_window(struct acpi_resource *res, void *data) | |
214 | { | |
215 | struct pci_root_info *info = data; | |
216 | struct pci_window *window; | |
217 | struct acpi_resource_address64 addr; | |
218 | acpi_status status; | |
219 | unsigned long flags, offset = 0; | |
220 | struct resource *root; | |
221 | ||
463eb297 BH |
222 | /* Return AE_OK for non-window resources to keep scanning for more */ |
223 | status = resource_to_window(res, &addr); | |
1da177e4 LT |
224 | if (!ACPI_SUCCESS(status)) |
225 | return AE_OK; | |
226 | ||
1da177e4 LT |
227 | if (addr.resource_type == ACPI_MEMORY_RANGE) { |
228 | flags = IORESOURCE_MEM; | |
229 | root = &iomem_resource; | |
230 | offset = addr.address_translation_offset; | |
231 | } else if (addr.resource_type == ACPI_IO_RANGE) { | |
232 | flags = IORESOURCE_IO; | |
233 | root = &ioport_resource; | |
234 | offset = add_io_space(&addr); | |
235 | if (offset == ~0) | |
236 | return AE_OK; | |
237 | } else | |
238 | return AE_OK; | |
239 | ||
240 | window = &info->controller->window[info->controller->windows++]; | |
241 | window->resource.name = info->name; | |
242 | window->resource.flags = flags; | |
243 | window->resource.start = addr.min_address_range + offset; | |
244 | window->resource.end = addr.max_address_range + offset; | |
245 | window->resource.child = NULL; | |
246 | window->offset = offset; | |
247 | ||
248 | if (insert_resource(root, &window->resource)) { | |
249 | printk(KERN_ERR "alloc 0x%lx-0x%lx from %s for %s failed\n", | |
250 | window->resource.start, window->resource.end, | |
251 | root->name, info->name); | |
252 | } | |
253 | ||
254 | return AE_OK; | |
255 | } | |
256 | ||
257 | static void __devinit | |
258 | pcibios_setup_root_windows(struct pci_bus *bus, struct pci_controller *ctrl) | |
259 | { | |
260 | int i, j; | |
261 | ||
262 | j = 0; | |
263 | for (i = 0; i < ctrl->windows; i++) { | |
264 | struct resource *res = &ctrl->window[i].resource; | |
265 | /* HP's firmware has a hack to work around a Windows bug. | |
266 | * Ignore these tiny memory ranges */ | |
267 | if ((res->flags & IORESOURCE_MEM) && | |
268 | (res->end - res->start < 16)) | |
269 | continue; | |
270 | if (j >= PCI_BUS_NUM_RESOURCES) { | |
271 | printk("Ignoring range [%lx-%lx] (%lx)\n", res->start, | |
272 | res->end, res->flags); | |
273 | continue; | |
274 | } | |
275 | bus->resource[j++] = res; | |
276 | } | |
277 | } | |
278 | ||
279 | struct pci_bus * __devinit | |
280 | pci_acpi_scan_root(struct acpi_device *device, int domain, int bus) | |
281 | { | |
282 | struct pci_root_info info; | |
283 | struct pci_controller *controller; | |
284 | unsigned int windows = 0; | |
285 | struct pci_bus *pbus; | |
286 | char *name; | |
514604c6 | 287 | int pxm; |
1da177e4 LT |
288 | |
289 | controller = alloc_pci_controller(domain); | |
290 | if (!controller) | |
291 | goto out1; | |
292 | ||
293 | controller->acpi_handle = device->handle; | |
294 | ||
514604c6 CL |
295 | pxm = acpi_get_pxm(controller->acpi_handle); |
296 | #ifdef CONFIG_NUMA | |
297 | if (pxm >= 0) | |
298 | controller->node = pxm_to_nid_map[pxm]; | |
299 | #endif | |
300 | ||
1da177e4 LT |
301 | acpi_walk_resources(device->handle, METHOD_NAME__CRS, count_window, |
302 | &windows); | |
514604c6 CL |
303 | controller->window = kmalloc_node(sizeof(*controller->window) * windows, |
304 | GFP_KERNEL, controller->node); | |
1da177e4 LT |
305 | if (!controller->window) |
306 | goto out2; | |
307 | ||
308 | name = kmalloc(16, GFP_KERNEL); | |
309 | if (!name) | |
310 | goto out3; | |
311 | ||
312 | sprintf(name, "PCI Bus %04x:%02x", domain, bus); | |
313 | info.controller = controller; | |
314 | info.name = name; | |
315 | acpi_walk_resources(device->handle, METHOD_NAME__CRS, add_window, | |
316 | &info); | |
317 | ||
c431ada4 | 318 | pbus = pci_scan_bus_parented(NULL, bus, &pci_root_ops, controller); |
1da177e4 LT |
319 | if (pbus) |
320 | pcibios_setup_root_windows(pbus, controller); | |
321 | ||
322 | return pbus; | |
323 | ||
324 | out3: | |
325 | kfree(controller->window); | |
326 | out2: | |
327 | kfree(controller); | |
328 | out1: | |
329 | return NULL; | |
330 | } | |
331 | ||
332 | void pcibios_resource_to_bus(struct pci_dev *dev, | |
333 | struct pci_bus_region *region, struct resource *res) | |
334 | { | |
335 | struct pci_controller *controller = PCI_CONTROLLER(dev); | |
336 | unsigned long offset = 0; | |
337 | int i; | |
338 | ||
339 | for (i = 0; i < controller->windows; i++) { | |
340 | struct pci_window *window = &controller->window[i]; | |
341 | if (!(window->resource.flags & res->flags)) | |
342 | continue; | |
343 | if (window->resource.start > res->start) | |
344 | continue; | |
345 | if (window->resource.end < res->end) | |
346 | continue; | |
347 | offset = window->offset; | |
348 | break; | |
349 | } | |
350 | ||
351 | region->start = res->start - offset; | |
352 | region->end = res->end - offset; | |
353 | } | |
354 | EXPORT_SYMBOL(pcibios_resource_to_bus); | |
355 | ||
356 | void pcibios_bus_to_resource(struct pci_dev *dev, | |
357 | struct resource *res, struct pci_bus_region *region) | |
358 | { | |
359 | struct pci_controller *controller = PCI_CONTROLLER(dev); | |
360 | unsigned long offset = 0; | |
361 | int i; | |
362 | ||
363 | for (i = 0; i < controller->windows; i++) { | |
364 | struct pci_window *window = &controller->window[i]; | |
365 | if (!(window->resource.flags & res->flags)) | |
366 | continue; | |
367 | if (window->resource.start - window->offset > region->start) | |
368 | continue; | |
369 | if (window->resource.end - window->offset < region->end) | |
370 | continue; | |
371 | offset = window->offset; | |
372 | break; | |
373 | } | |
374 | ||
375 | res->start = region->start + offset; | |
376 | res->end = region->end + offset; | |
377 | } | |
41290c14 | 378 | EXPORT_SYMBOL(pcibios_bus_to_resource); |
1da177e4 | 379 | |
71c3511c RS |
380 | static int __devinit is_valid_resource(struct pci_dev *dev, int idx) |
381 | { | |
382 | unsigned int i, type_mask = IORESOURCE_IO | IORESOURCE_MEM; | |
383 | struct resource *devr = &dev->resource[idx]; | |
384 | ||
385 | if (!dev->bus) | |
386 | return 0; | |
387 | for (i=0; i<PCI_BUS_NUM_RESOURCES; i++) { | |
388 | struct resource *busr = dev->bus->resource[i]; | |
389 | ||
390 | if (!busr || ((busr->flags ^ devr->flags) & type_mask)) | |
391 | continue; | |
392 | if ((devr->start) && (devr->start >= busr->start) && | |
393 | (devr->end <= busr->end)) | |
394 | return 1; | |
395 | } | |
396 | return 0; | |
397 | } | |
398 | ||
1da177e4 LT |
399 | static void __devinit pcibios_fixup_device_resources(struct pci_dev *dev) |
400 | { | |
401 | struct pci_bus_region region; | |
402 | int i; | |
403 | int limit = (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) ? \ | |
404 | PCI_BRIDGE_RESOURCES : PCI_NUM_RESOURCES; | |
405 | ||
406 | for (i = 0; i < limit; i++) { | |
407 | if (!dev->resource[i].flags) | |
408 | continue; | |
409 | region.start = dev->resource[i].start; | |
410 | region.end = dev->resource[i].end; | |
411 | pcibios_bus_to_resource(dev, &dev->resource[i], ®ion); | |
71c3511c RS |
412 | if ((is_valid_resource(dev, i))) |
413 | pci_claim_resource(dev, i); | |
1da177e4 LT |
414 | } |
415 | } | |
416 | ||
417 | /* | |
418 | * Called after each bus is probed, but before its children are examined. | |
419 | */ | |
420 | void __devinit | |
421 | pcibios_fixup_bus (struct pci_bus *b) | |
422 | { | |
423 | struct pci_dev *dev; | |
424 | ||
f7d473d9 RS |
425 | if (b->self) { |
426 | pci_read_bridge_bases(b); | |
427 | pcibios_fixup_device_resources(b->self); | |
428 | } | |
1da177e4 LT |
429 | list_for_each_entry(dev, &b->devices, bus_list) |
430 | pcibios_fixup_device_resources(dev); | |
431 | ||
432 | return; | |
433 | } | |
434 | ||
435 | void __devinit | |
436 | pcibios_update_irq (struct pci_dev *dev, int irq) | |
437 | { | |
438 | pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); | |
439 | ||
440 | /* ??? FIXME -- record old value for shutdown. */ | |
441 | } | |
442 | ||
443 | static inline int | |
444 | pcibios_enable_resources (struct pci_dev *dev, int mask) | |
445 | { | |
446 | u16 cmd, old_cmd; | |
447 | int idx; | |
448 | struct resource *r; | |
fab3fb0a | 449 | unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM; |
1da177e4 LT |
450 | |
451 | if (!dev) | |
452 | return -EINVAL; | |
453 | ||
454 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
455 | old_cmd = cmd; | |
fab3fb0a | 456 | for (idx=0; idx<PCI_NUM_RESOURCES; idx++) { |
1da177e4 LT |
457 | /* Only set up the desired resources. */ |
458 | if (!(mask & (1 << idx))) | |
459 | continue; | |
460 | ||
461 | r = &dev->resource[idx]; | |
fab3fb0a RS |
462 | if (!(r->flags & type_mask)) |
463 | continue; | |
464 | if ((idx == PCI_ROM_RESOURCE) && | |
465 | (!(r->flags & IORESOURCE_ROM_ENABLE))) | |
466 | continue; | |
1da177e4 LT |
467 | if (!r->start && r->end) { |
468 | printk(KERN_ERR | |
469 | "PCI: Device %s not available because of resource collisions\n", | |
470 | pci_name(dev)); | |
471 | return -EINVAL; | |
472 | } | |
473 | if (r->flags & IORESOURCE_IO) | |
474 | cmd |= PCI_COMMAND_IO; | |
475 | if (r->flags & IORESOURCE_MEM) | |
476 | cmd |= PCI_COMMAND_MEMORY; | |
477 | } | |
1da177e4 LT |
478 | if (cmd != old_cmd) { |
479 | printk("PCI: Enabling device %s (%04x -> %04x)\n", pci_name(dev), old_cmd, cmd); | |
480 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
481 | } | |
482 | return 0; | |
483 | } | |
484 | ||
485 | int | |
486 | pcibios_enable_device (struct pci_dev *dev, int mask) | |
487 | { | |
488 | int ret; | |
489 | ||
490 | ret = pcibios_enable_resources(dev, mask); | |
491 | if (ret < 0) | |
492 | return ret; | |
493 | ||
494 | return acpi_pci_irq_enable(dev); | |
495 | } | |
496 | ||
1da177e4 LT |
497 | void |
498 | pcibios_disable_device (struct pci_dev *dev) | |
499 | { | |
500 | acpi_pci_irq_disable(dev); | |
501 | } | |
1da177e4 LT |
502 | |
503 | void | |
504 | pcibios_align_resource (void *data, struct resource *res, | |
505 | unsigned long size, unsigned long align) | |
506 | { | |
507 | } | |
508 | ||
509 | /* | |
510 | * PCI BIOS setup, always defaults to SAL interface | |
511 | */ | |
512 | char * __init | |
513 | pcibios_setup (char *str) | |
514 | { | |
1da177e4 LT |
515 | return NULL; |
516 | } | |
517 | ||
518 | int | |
519 | pci_mmap_page_range (struct pci_dev *dev, struct vm_area_struct *vma, | |
520 | enum pci_mmap_state mmap_state, int write_combine) | |
521 | { | |
522 | /* | |
523 | * I/O space cannot be accessed via normal processor loads and | |
524 | * stores on this platform. | |
525 | */ | |
526 | if (mmap_state == pci_mmap_io) | |
527 | /* | |
528 | * XXX we could relax this for I/O spaces for which ACPI | |
529 | * indicates that the space is 1-to-1 mapped. But at the | |
530 | * moment, we don't support multiple PCI address spaces and | |
531 | * the legacy I/O space is not 1-to-1 mapped, so this is moot. | |
532 | */ | |
533 | return -EINVAL; | |
534 | ||
535 | /* | |
536 | * Leave vm_pgoff as-is, the PCI space address is the physical | |
537 | * address on this platform. | |
538 | */ | |
539 | vma->vm_flags |= (VM_SHM | VM_RESERVED | VM_IO); | |
540 | ||
541 | if (write_combine && efi_range_is_wc(vma->vm_start, | |
542 | vma->vm_end - vma->vm_start)) | |
543 | vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); | |
544 | else | |
545 | vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); | |
546 | ||
547 | if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, | |
548 | vma->vm_end - vma->vm_start, vma->vm_page_prot)) | |
549 | return -EAGAIN; | |
550 | ||
551 | return 0; | |
552 | } | |
553 | ||
554 | /** | |
555 | * ia64_pci_get_legacy_mem - generic legacy mem routine | |
556 | * @bus: bus to get legacy memory base address for | |
557 | * | |
558 | * Find the base of legacy memory for @bus. This is typically the first | |
559 | * megabyte of bus address space for @bus or is simply 0 on platforms whose | |
560 | * chipsets support legacy I/O and memory routing. Returns the base address | |
561 | * or an error pointer if an error occurred. | |
562 | * | |
563 | * This is the ia64 generic version of this routine. Other platforms | |
564 | * are free to override it with a machine vector. | |
565 | */ | |
566 | char *ia64_pci_get_legacy_mem(struct pci_bus *bus) | |
567 | { | |
568 | return (char *)__IA64_UNCACHED_OFFSET; | |
569 | } | |
570 | ||
571 | /** | |
572 | * pci_mmap_legacy_page_range - map legacy memory space to userland | |
573 | * @bus: bus whose legacy space we're mapping | |
574 | * @vma: vma passed in by mmap | |
575 | * | |
576 | * Map legacy memory space for this device back to userspace using a machine | |
577 | * vector to get the base address. | |
578 | */ | |
579 | int | |
580 | pci_mmap_legacy_page_range(struct pci_bus *bus, struct vm_area_struct *vma) | |
581 | { | |
582 | char *addr; | |
583 | ||
584 | addr = pci_get_legacy_mem(bus); | |
585 | if (IS_ERR(addr)) | |
586 | return PTR_ERR(addr); | |
587 | ||
588 | vma->vm_pgoff += (unsigned long)addr >> PAGE_SHIFT; | |
589 | vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); | |
590 | vma->vm_flags |= (VM_SHM | VM_RESERVED | VM_IO); | |
591 | ||
592 | if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, | |
593 | vma->vm_end - vma->vm_start, vma->vm_page_prot)) | |
594 | return -EAGAIN; | |
595 | ||
596 | return 0; | |
597 | } | |
598 | ||
599 | /** | |
600 | * ia64_pci_legacy_read - read from legacy I/O space | |
601 | * @bus: bus to read | |
602 | * @port: legacy port value | |
603 | * @val: caller allocated storage for returned value | |
604 | * @size: number of bytes to read | |
605 | * | |
606 | * Simply reads @size bytes from @port and puts the result in @val. | |
607 | * | |
608 | * Again, this (and the write routine) are generic versions that can be | |
609 | * overridden by the platform. This is necessary on platforms that don't | |
610 | * support legacy I/O routing or that hard fail on legacy I/O timeouts. | |
611 | */ | |
612 | int ia64_pci_legacy_read(struct pci_bus *bus, u16 port, u32 *val, u8 size) | |
613 | { | |
614 | int ret = size; | |
615 | ||
616 | switch (size) { | |
617 | case 1: | |
618 | *val = inb(port); | |
619 | break; | |
620 | case 2: | |
621 | *val = inw(port); | |
622 | break; | |
623 | case 4: | |
624 | *val = inl(port); | |
625 | break; | |
626 | default: | |
627 | ret = -EINVAL; | |
628 | break; | |
629 | } | |
630 | ||
631 | return ret; | |
632 | } | |
633 | ||
634 | /** | |
635 | * ia64_pci_legacy_write - perform a legacy I/O write | |
636 | * @bus: bus pointer | |
637 | * @port: port to write | |
638 | * @val: value to write | |
639 | * @size: number of bytes to write from @val | |
640 | * | |
641 | * Simply writes @size bytes of @val to @port. | |
642 | */ | |
643 | int ia64_pci_legacy_write(struct pci_dev *bus, u16 port, u32 val, u8 size) | |
644 | { | |
645 | int ret = 0; | |
646 | ||
647 | switch (size) { | |
648 | case 1: | |
649 | outb(val, port); | |
650 | break; | |
651 | case 2: | |
652 | outw(val, port); | |
653 | break; | |
654 | case 4: | |
655 | outl(val, port); | |
656 | break; | |
657 | default: | |
658 | ret = -EINVAL; | |
659 | break; | |
660 | } | |
661 | ||
662 | return ret; | |
663 | } | |
664 | ||
665 | /** | |
666 | * pci_cacheline_size - determine cacheline size for PCI devices | |
667 | * @dev: void | |
668 | * | |
669 | * We want to use the line-size of the outer-most cache. We assume | |
670 | * that this line-size is the same for all CPUs. | |
671 | * | |
672 | * Code mostly taken from arch/ia64/kernel/palinfo.c:cache_info(). | |
673 | * | |
674 | * RETURNS: An appropriate -ERRNO error value on eror, or zero for success. | |
675 | */ | |
676 | static unsigned long | |
677 | pci_cacheline_size (void) | |
678 | { | |
679 | u64 levels, unique_caches; | |
680 | s64 status; | |
681 | pal_cache_config_info_t cci; | |
682 | static u8 cacheline_size; | |
683 | ||
684 | if (cacheline_size) | |
685 | return cacheline_size; | |
686 | ||
687 | status = ia64_pal_cache_summary(&levels, &unique_caches); | |
688 | if (status != 0) { | |
689 | printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n", | |
690 | __FUNCTION__, status); | |
691 | return SMP_CACHE_BYTES; | |
692 | } | |
693 | ||
694 | status = ia64_pal_cache_config_info(levels - 1, /* cache_type (data_or_unified)= */ 2, | |
695 | &cci); | |
696 | if (status != 0) { | |
697 | printk(KERN_ERR "%s: ia64_pal_cache_config_info() failed (status=%ld)\n", | |
698 | __FUNCTION__, status); | |
699 | return SMP_CACHE_BYTES; | |
700 | } | |
701 | cacheline_size = 1 << cci.pcci_line_size; | |
702 | return cacheline_size; | |
703 | } | |
704 | ||
705 | /** | |
706 | * pcibios_prep_mwi - helper function for drivers/pci/pci.c:pci_set_mwi() | |
707 | * @dev: the PCI device for which MWI is enabled | |
708 | * | |
709 | * For ia64, we can get the cacheline sizes from PAL. | |
710 | * | |
711 | * RETURNS: An appropriate -ERRNO error value on eror, or zero for success. | |
712 | */ | |
713 | int | |
714 | pcibios_prep_mwi (struct pci_dev *dev) | |
715 | { | |
716 | unsigned long desired_linesize, current_linesize; | |
717 | int rc = 0; | |
718 | u8 pci_linesize; | |
719 | ||
720 | desired_linesize = pci_cacheline_size(); | |
721 | ||
722 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &pci_linesize); | |
723 | current_linesize = 4 * pci_linesize; | |
724 | if (desired_linesize != current_linesize) { | |
725 | printk(KERN_WARNING "PCI: slot %s has incorrect PCI cache line size of %lu bytes,", | |
726 | pci_name(dev), current_linesize); | |
727 | if (current_linesize > desired_linesize) { | |
728 | printk(" expected %lu bytes instead\n", desired_linesize); | |
729 | rc = -EINVAL; | |
730 | } else { | |
731 | printk(" correcting to %lu\n", desired_linesize); | |
732 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, desired_linesize / 4); | |
733 | } | |
734 | } | |
735 | return rc; | |
736 | } | |
737 | ||
738 | int pci_vector_resources(int last, int nr_released) | |
739 | { | |
740 | int count = nr_released; | |
741 | ||
742 | count += (IA64_LAST_DEVICE_VECTOR - last); | |
743 | ||
744 | return count; | |
745 | } |