projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[IA64] cpu hotplug: return offlined cpus to SAL
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / ia64 / kernel / head.S
CommitLineData
1da177e4
LT		 1/*
2 * Here is where the ball gets rolling as far as the kernel is concerned.
3 * When control is transferred to _start, the bootload has already
4 * loaded us to the correct address. All that's left to do here is
5 * to set up the kernel's global pointer and jump to the kernel
6 * entry point.
7 *
8 * Copyright (C) 1998-2001, 2003, 2005 Hewlett-Packard Co
9 * David Mosberger-Tang <davidm@hpl.hp.com>
10 * Stephane Eranian <eranian@hpl.hp.com>
11 * Copyright (C) 1999 VA Linux Systems
12 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
13 * Copyright (C) 1999 Intel Corp.
14 * Copyright (C) 1999 Asit Mallick <Asit.K.Mallick@intel.com>
15 * Copyright (C) 1999 Don Dugger <Don.Dugger@intel.com>
16 * Copyright (C) 2002 Fenghua Yu <fenghua.yu@intel.com>
17 * -Optimize __ia64_save_fpu() and __ia64_load_fpu() for Itanium 2.
b8d8b883
AR		 18 * Copyright (C) 2004 Ashok Raj <ashok.raj@intel.com>
19 * Support for CPU Hotplug
1da177e4
LT		 20 */
21
22#include <linux/config.h>
23
24#include <asm/asmmacro.h>
25#include <asm/fpu.h>
26#include <asm/kregs.h>
27#include <asm/mmu_context.h>
28#include <asm/offsets.h>
29#include <asm/pal.h>
30#include <asm/pgtable.h>
31#include <asm/processor.h>
32#include <asm/ptrace.h>
33#include <asm/system.h>
b8d8b883
AR		 34#include <asm/mca_asm.h>
35
36#ifdef CONFIG_HOTPLUG_CPU
37#define SAL_PSR_BITS_TO_SET \
38 (IA64_PSR_AC | IA64_PSR_BN | IA64_PSR_MFH | IA64_PSR_MFL)
39
40#define SAVE_FROM_REG(src, ptr, dest) \
41 mov dest=src;; \
42 st8 [ptr]=dest,0x08
43
44#define RESTORE_REG(reg, ptr, _tmp) \
45 ld8 _tmp=[ptr],0x08;; \
46 mov reg=_tmp
47
48#define SAVE_BREAK_REGS(ptr, _idx, _breg, _dest)\
49 mov ar.lc=IA64_NUM_DBG_REGS-1;; \
50 mov _idx=0;; \
511: \
52 SAVE_FROM_REG(_breg[_idx], ptr, _dest);; \
53 add _idx=1,_idx;; \
54 br.cloop.sptk.many 1b
55
56#define RESTORE_BREAK_REGS(ptr, _idx, _breg, _tmp, _lbl)\
57 mov ar.lc=IA64_NUM_DBG_REGS-1;; \
58 mov _idx=0;; \
59_lbl: RESTORE_REG(_breg[_idx], ptr, _tmp);; \
60 add _idx=1, _idx;; \
61 br.cloop.sptk.many _lbl
62
63#define SAVE_ONE_RR(num, _reg, _tmp) \
64 movl _tmp=(num<<61);; \
65 mov _reg=rr[_tmp]
66
67#define SAVE_REGION_REGS(_tmp, _r0, _r1, _r2, _r3, _r4, _r5, _r6, _r7) \
68 SAVE_ONE_RR(0,_r0, _tmp);; \
69 SAVE_ONE_RR(1,_r1, _tmp);; \
70 SAVE_ONE_RR(2,_r2, _tmp);; \
71 SAVE_ONE_RR(3,_r3, _tmp);; \
72 SAVE_ONE_RR(4,_r4, _tmp);; \
73 SAVE_ONE_RR(5,_r5, _tmp);; \
74 SAVE_ONE_RR(6,_r6, _tmp);; \
75 SAVE_ONE_RR(7,_r7, _tmp);;
76
77#define STORE_REGION_REGS(ptr, _r0, _r1, _r2, _r3, _r4, _r5, _r6, _r7) \
78 st8 [ptr]=_r0, 8;; \
79 st8 [ptr]=_r1, 8;; \
80 st8 [ptr]=_r2, 8;; \
81 st8 [ptr]=_r3, 8;; \
82 st8 [ptr]=_r4, 8;; \
83 st8 [ptr]=_r5, 8;; \
84 st8 [ptr]=_r6, 8;; \
85 st8 [ptr]=_r7, 8;;
86
87#define RESTORE_REGION_REGS(ptr, _idx1, _idx2, _tmp) \
88 mov ar.lc=0x08-1;; \
89 movl _idx1=0x00;; \
90RestRR: \
91 dep.z _idx2=_idx1,61,3;; \
92 ld8 _tmp=[ptr],8;; \
93 mov rr[_idx2]=_tmp;; \
94 srlz.d;; \
95 add _idx1=1,_idx1;; \
96 br.cloop.sptk.few RestRR
97
98/*
99 * Adjust region registers saved before starting to save
100 * break regs and rest of the states that need to be preserved.
101 */
102#define SAL_TO_OS_BOOT_HANDOFF_STATE_SAVE(_reg1,_reg2,_pred) \
103 SAVE_FROM_REG(b0,_reg1,_reg2);; \
104 SAVE_FROM_REG(b1,_reg1,_reg2);; \
105 SAVE_FROM_REG(b2,_reg1,_reg2);; \
106 SAVE_FROM_REG(b3,_reg1,_reg2);; \
107 SAVE_FROM_REG(b4,_reg1,_reg2);; \
108 SAVE_FROM_REG(b5,_reg1,_reg2);; \
109 st8 [_reg1]=r1,0x08;; \
110 st8 [_reg1]=r12,0x08;; \
111 st8 [_reg1]=r13,0x08;; \
112 SAVE_FROM_REG(ar.fpsr,_reg1,_reg2);; \
113 SAVE_FROM_REG(ar.pfs,_reg1,_reg2);; \
114 SAVE_FROM_REG(ar.rnat,_reg1,_reg2);; \
115 SAVE_FROM_REG(ar.unat,_reg1,_reg2);; \
116 SAVE_FROM_REG(ar.bspstore,_reg1,_reg2);; \
117 SAVE_FROM_REG(cr.dcr,_reg1,_reg2);; \
118 SAVE_FROM_REG(cr.iva,_reg1,_reg2);; \
119 SAVE_FROM_REG(cr.pta,_reg1,_reg2);; \
120 SAVE_FROM_REG(cr.itv,_reg1,_reg2);; \
121 SAVE_FROM_REG(cr.pmv,_reg1,_reg2);; \
122 SAVE_FROM_REG(cr.cmcv,_reg1,_reg2);; \
123 SAVE_FROM_REG(cr.lrr0,_reg1,_reg2);; \
124 SAVE_FROM_REG(cr.lrr1,_reg1,_reg2);; \
125 st8 [_reg1]=r4,0x08;; \
126 st8 [_reg1]=r5,0x08;; \
127 st8 [_reg1]=r6,0x08;; \
128 st8 [_reg1]=r7,0x08;; \
129 st8 [_reg1]=_pred,0x08;; \
130 SAVE_FROM_REG(ar.lc, _reg1, _reg2);; \
131 stf.spill.nta [_reg1]=f2,16;; \
132 stf.spill.nta [_reg1]=f3,16;; \
133 stf.spill.nta [_reg1]=f4,16;; \
134 stf.spill.nta [_reg1]=f5,16;; \
135 stf.spill.nta [_reg1]=f16,16;; \
136 stf.spill.nta [_reg1]=f17,16;; \
137 stf.spill.nta [_reg1]=f18,16;; \
138 stf.spill.nta [_reg1]=f19,16;; \
139 stf.spill.nta [_reg1]=f20,16;; \
140 stf.spill.nta [_reg1]=f21,16;; \
141 stf.spill.nta [_reg1]=f22,16;; \
142 stf.spill.nta [_reg1]=f23,16;; \
143 stf.spill.nta [_reg1]=f24,16;; \
144 stf.spill.nta [_reg1]=f25,16;; \
145 stf.spill.nta [_reg1]=f26,16;; \
146 stf.spill.nta [_reg1]=f27,16;; \
147 stf.spill.nta [_reg1]=f28,16;; \
148 stf.spill.nta [_reg1]=f29,16;; \
149 stf.spill.nta [_reg1]=f30,16;; \
150 stf.spill.nta [_reg1]=f31,16;;
151
152#else
153#define SAL_TO_OS_BOOT_HANDOFF_STATE_SAVE(a1,a2)
154#define SAVE_REGION_REGS(_tmp, _r0, _r1, _r2, _r3, _r4, _r5, _r6, _r7)
155#define STORE_REGION_REGS(ptr, _r0, _r1, _r2, _r3, _r4, _r5, _r6, _r7)
156#endif
157
158#define SET_ONE_RR(num, pgsize, _tmp1, _tmp2, vhpt) \
159 movl _tmp1=(num << 61);; \
160 mov _tmp2=((ia64_rid(IA64_REGION_ID_KERNEL, (num<<61)) << 8) | (pgsize << 2) | vhpt);; \
161 mov rr[_tmp1]=_tmp2
1da177e4
LT		 162
163 .section __special_page_section,"ax"
164
165 .global empty_zero_page
166empty_zero_page:
167 .skip PAGE_SIZE
168
169 .global swapper_pg_dir
170swapper_pg_dir:
171 .skip PAGE_SIZE
172
173 .rodata
174halt_msg:
175 stringz "Halting kernel\n"
176
177 .text
178
179 .global start_ap
180
181 /*
182 * Start the kernel. When the bootloader passes control to _start(), r28
183 * points to the address of the boot parameter area. Execution reaches
184 * here in physical mode.
185 */
186GLOBAL_ENTRY(_start)
187start_ap:
188 .prologue
189 .save rp, r0 // terminate unwind chain with a NULL rp
190 .body
191
192 rsm psr.i | psr.ic
193 ;;
194 srlz.i
195 ;;
b8d8b883
AR		 196 /*
197 * Save the region registers, predicate before they get clobbered
198 */
199 SAVE_REGION_REGS(r2, r8,r9,r10,r11,r12,r13,r14,r15);
200 mov r25=pr;;
201
1da177e4
LT		 202 /*
203 * Initialize kernel region registers:
204 * rr[0]: VHPT enabled, page size = PAGE_SHIFT
205 * rr[1]: VHPT enabled, page size = PAGE_SHIFT
206 * rr[2]: VHPT enabled, page size = PAGE_SHIFT
207 * rr[3]: VHPT enabled, page size = PAGE_SHIFT
208 * rr[4]: VHPT enabled, page size = PAGE_SHIFT
209 * rr[5]: VHPT enabled, page size = PAGE_SHIFT
210 * rr[6]: VHPT disabled, page size = IA64_GRANULE_SHIFT
211 * rr[7]: VHPT disabled, page size = IA64_GRANULE_SHIFT
212 * We initialize all of them to prevent inadvertently assuming
213 * something about the state of address translation early in boot.
214 */
b8d8b883
AR		 215 SET_ONE_RR(0, PAGE_SHIFT, r2, r16, 1);;
216 SET_ONE_RR(1, PAGE_SHIFT, r2, r16, 1);;
217 SET_ONE_RR(2, PAGE_SHIFT, r2, r16, 1);;
218 SET_ONE_RR(3, PAGE_SHIFT, r2, r16, 1);;
219 SET_ONE_RR(4, PAGE_SHIFT, r2, r16, 1);;
220 SET_ONE_RR(5, PAGE_SHIFT, r2, r16, 1);;
221 SET_ONE_RR(6, IA64_GRANULE_SHIFT, r2, r16, 0);;
222 SET_ONE_RR(7, IA64_GRANULE_SHIFT, r2, r16, 0);;
1da177e4
LT		 223 /*
224 * Now pin mappings into the TLB for kernel text and data
225 */
226 mov r18=KERNEL_TR_PAGE_SHIFT<<2
227 movl r17=KERNEL_START
228 ;;
229 mov cr.itir=r18
230 mov cr.ifa=r17
231 mov r16=IA64_TR_KERNEL
232 mov r3=ip
233 movl r18=PAGE_KERNEL
234 ;;
235 dep r2=0,r3,0,KERNEL_TR_PAGE_SHIFT
236 ;;
237 or r18=r2,r18
238 ;;
239 srlz.i
240 ;;
241 itr.i itr[r16]=r18
242 ;;
243 itr.d dtr[r16]=r18
244 ;;
245 srlz.i
246
247 /*
248 * Switch into virtual mode:
249 */
250 movl r16=(IA64_PSR_IT|IA64_PSR_IC|IA64_PSR_DT|IA64_PSR_RT|IA64_PSR_DFH|IA64_PSR_BN \
251 |IA64_PSR_DI)
252 ;;
253 mov cr.ipsr=r16
254 movl r17=1f
255 ;;
256 mov cr.iip=r17
257 mov cr.ifs=r0
258 ;;
259 rfi
260 ;;
2611: // now we are in virtual mode
262
b8d8b883
AR		 263 movl r2=sal_state_for_booting_cpu;;
264 ld8 r16=[r2];;
265
266 STORE_REGION_REGS(r16, r8,r9,r10,r11,r12,r13,r14,r15);
267 SAL_TO_OS_BOOT_HANDOFF_STATE_SAVE(r16,r17,r25)
268 ;;
269
1da177e4
LT		 270 // set IVT entry point---can't access I/O ports without it
271 movl r3=ia64_ivt
272 ;;
273 mov cr.iva=r3
274 movl r2=FPSR_DEFAULT
275 ;;
276 srlz.i
277 movl gp=__gp
278
279 mov ar.fpsr=r2
280 ;;
281
282#define isAP p2 // are we an Application Processor?
283#define isBP p3 // are we the Bootstrap Processor?
284
285#ifdef CONFIG_SMP
286 /*
287 * Find the init_task for the currently booting CPU. At poweron, and in
288 * UP mode, task_for_booting_cpu is NULL.
289 */
290 movl r3=task_for_booting_cpu
291 ;;
292 ld8 r3=[r3]
293 movl r2=init_task
294 ;;
295 cmp.eq isBP,isAP=r3,r0
296 ;;
297(isAP) mov r2=r3
298#else
299 movl r2=init_task
300 cmp.eq isBP,isAP=r0,r0
301#endif
302 ;;
303 tpa r3=r2 // r3 == phys addr of task struct
304 mov r16=-1
305(isBP) br.cond.dpnt .load_current // BP stack is on region 5 --- no need to map it
306
307 // load mapping for stack (virtaddr in r2, physaddr in r3)
308 rsm psr.ic
309 movl r17=PAGE_KERNEL
310 ;;
311 srlz.d
312 dep r18=0,r3,0,12
313 ;;
314 or r18=r17,r18
315 dep r2=-1,r3,61,3 // IMVA of task
316 ;;
317 mov r17=rr[r2]
318 shr.u r16=r3,IA64_GRANULE_SHIFT
319 ;;
320 dep r17=0,r17,8,24
321 ;;
322 mov cr.itir=r17
323 mov cr.ifa=r2
324
325 mov r19=IA64_TR_CURRENT_STACK
326 ;;
327 itr.d dtr[r19]=r18
328 ;;
329 ssm psr.ic
330 srlz.d
331 ;;
332
333.load_current:
334 // load the "current" pointer (r13) and ar.k6 with the current task
335 mov IA64_KR(CURRENT)=r2 // virtual address
336 mov IA64_KR(CURRENT_STACK)=r16
337 mov r13=r2
338 /*
b8d8b883
AR		 339 * Reserve space at the top of the stack for "struct pt_regs". Kernel
340 * threads don't store interesting values in that structure, but the space
341 * still needs to be there because time-critical stuff such as the context
342 * switching can be implemented more efficiently (for example, __switch_to()
1da177e4
LT		 343 * always sets the psr.dfh bit of the task it is switching to).
344 */
b8d8b883 345
1da177e4
LT		 346 addl r12=IA64_STK_OFFSET-IA64_PT_REGS_SIZE-16,r2
347 addl r2=IA64_RBS_OFFSET,r2 // initialize the RSE
348 mov ar.rsc=0 // place RSE in enforced lazy mode
349 ;;
350 loadrs // clear the dirty partition
351 ;;
352 mov ar.bspstore=r2 // establish the new RSE stack
353 ;;
354 mov ar.rsc=0x3 // place RSE in eager mode
355
356(isBP) dep r28=-1,r28,61,3 // make address virtual
357(isBP) movl r2=ia64_boot_param
358 ;;
359(isBP) st8 [r2]=r28 // save the address of the boot param area passed by the bootloader
360
361#ifdef CONFIG_SMP
362(isAP) br.call.sptk.many rp=start_secondary
363.ret0:
364(isAP) br.cond.sptk self
365#endif
366
367 // This is executed by the bootstrap processor (bsp) only:
368
369#ifdef CONFIG_IA64_FW_EMU
370 // initialize PAL & SAL emulator:
371 br.call.sptk.many rp=sys_fw_init
372.ret1:
373#endif
374 br.call.sptk.many rp=start_kernel
375.ret2: addl r3=@ltoff(halt_msg),gp
376 ;;
377 alloc r2=ar.pfs,8,0,2,0
378 ;;
379 ld8 out0=[r3]
380 br.call.sptk.many b0=console_print
381
382self: hint @pause
383 br.sptk.many self // endless loop
384END(_start)
385
386GLOBAL_ENTRY(ia64_save_debug_regs)
387 alloc r16=ar.pfs,1,0,0,0
388 mov r20=ar.lc // preserve ar.lc
389 mov ar.lc=IA64_NUM_DBG_REGS-1
390 mov r18=0
391 add r19=IA64_NUM_DBG_REGS*8,in0
392 ;;
3931: mov r16=dbr[r18]
394#ifdef CONFIG_ITANIUM
395 ;;
396 srlz.d
397#endif
398 mov r17=ibr[r18]
399 add r18=1,r18
400 ;;
401 st8.nta [in0]=r16,8
402 st8.nta [r19]=r17,8
403 br.cloop.sptk.many 1b
404 ;;
405 mov ar.lc=r20 // restore ar.lc
406 br.ret.sptk.many rp
407END(ia64_save_debug_regs)
408
409GLOBAL_ENTRY(ia64_load_debug_regs)
410 alloc r16=ar.pfs,1,0,0,0
411 lfetch.nta [in0]
412 mov r20=ar.lc // preserve ar.lc
413 add r19=IA64_NUM_DBG_REGS*8,in0
414 mov ar.lc=IA64_NUM_DBG_REGS-1
415 mov r18=-1
416 ;;
4171: ld8.nta r16=[in0],8
418 ld8.nta r17=[r19],8
419 add r18=1,r18
420 ;;
421 mov dbr[r18]=r16
422#ifdef CONFIG_ITANIUM
423 ;;
424 srlz.d // Errata 132 (NoFix status)
425#endif
426 mov ibr[r18]=r17
427 br.cloop.sptk.many 1b
428 ;;
429 mov ar.lc=r20 // restore ar.lc
430 br.ret.sptk.many rp
431END(ia64_load_debug_regs)
432
433GLOBAL_ENTRY(__ia64_save_fpu)
434 alloc r2=ar.pfs,1,4,0,0
435 adds loc0=96*16-16,in0
436 adds loc1=96*16-16-128,in0
437 ;;
438 stf.spill.nta [loc0]=f127,-256
439 stf.spill.nta [loc1]=f119,-256
440 ;;
441 stf.spill.nta [loc0]=f111,-256
442 stf.spill.nta [loc1]=f103,-256
443 ;;
444 stf.spill.nta [loc0]=f95,-256
445 stf.spill.nta [loc1]=f87,-256
446 ;;
447 stf.spill.nta [loc0]=f79,-256
448 stf.spill.nta [loc1]=f71,-256
449 ;;
450 stf.spill.nta [loc0]=f63,-256
451 stf.spill.nta [loc1]=f55,-256
452 adds loc2=96*16-32,in0
453 ;;
454 stf.spill.nta [loc0]=f47,-256
455 stf.spill.nta [loc1]=f39,-256
456 adds loc3=96*16-32-128,in0
457 ;;
458 stf.spill.nta [loc2]=f126,-256
459 stf.spill.nta [loc3]=f118,-256
460 ;;
461 stf.spill.nta [loc2]=f110,-256
462 stf.spill.nta [loc3]=f102,-256
463 ;;
464 stf.spill.nta [loc2]=f94,-256
465 stf.spill.nta [loc3]=f86,-256
466 ;;
467 stf.spill.nta [loc2]=f78,-256
468 stf.spill.nta [loc3]=f70,-256
469 ;;
470 stf.spill.nta [loc2]=f62,-256
471 stf.spill.nta [loc3]=f54,-256
472 adds loc0=96*16-48,in0
473 ;;
474 stf.spill.nta [loc2]=f46,-256
475 stf.spill.nta [loc3]=f38,-256
476 adds loc1=96*16-48-128,in0
477 ;;
478 stf.spill.nta [loc0]=f125,-256
479 stf.spill.nta [loc1]=f117,-256
480 ;;
481 stf.spill.nta [loc0]=f109,-256
482 stf.spill.nta [loc1]=f101,-256
483 ;;
484 stf.spill.nta [loc0]=f93,-256
485 stf.spill.nta [loc1]=f85,-256
486 ;;
487 stf.spill.nta [loc0]=f77,-256
488 stf.spill.nta [loc1]=f69,-256
489 ;;
490 stf.spill.nta [loc0]=f61,-256
491 stf.spill.nta [loc1]=f53,-256
492 adds loc2=96*16-64,in0
493 ;;
494 stf.spill.nta [loc0]=f45,-256
495 stf.spill.nta [loc1]=f37,-256
496 adds loc3=96*16-64-128,in0
497 ;;
498 stf.spill.nta [loc2]=f124,-256
499 stf.spill.nta [loc3]=f116,-256
500 ;;
501 stf.spill.nta [loc2]=f108,-256
502 stf.spill.nta [loc3]=f100,-256
503 ;;
504 stf.spill.nta [loc2]=f92,-256
505 stf.spill.nta [loc3]=f84,-256
506 ;;
507 stf.spill.nta [loc2]=f76,-256
508 stf.spill.nta [loc3]=f68,-256
509 ;;
510 stf.spill.nta [loc2]=f60,-256
511 stf.spill.nta [loc3]=f52,-256
512 adds loc0=96*16-80,in0
513 ;;
514 stf.spill.nta [loc2]=f44,-256
515 stf.spill.nta [loc3]=f36,-256
516 adds loc1=96*16-80-128,in0
517 ;;
518 stf.spill.nta [loc0]=f123,-256
519 stf.spill.nta [loc1]=f115,-256
520 ;;
521 stf.spill.nta [loc0]=f107,-256
522 stf.spill.nta [loc1]=f99,-256
523 ;;
524 stf.spill.nta [loc0]=f91,-256
525 stf.spill.nta [loc1]=f83,-256
526 ;;
527 stf.spill.nta [loc0]=f75,-256
528 stf.spill.nta [loc1]=f67,-256
529 ;;
530 stf.spill.nta [loc0]=f59,-256
531 stf.spill.nta [loc1]=f51,-256
532 adds loc2=96*16-96,in0
533 ;;
534 stf.spill.nta [loc0]=f43,-256
535 stf.spill.nta [loc1]=f35,-256
536 adds loc3=96*16-96-128,in0
537 ;;
538 stf.spill.nta [loc2]=f122,-256
539 stf.spill.nta [loc3]=f114,-256
540 ;;
541 stf.spill.nta [loc2]=f106,-256
542 stf.spill.nta [loc3]=f98,-256
543 ;;
544 stf.spill.nta [loc2]=f90,-256
545 stf.spill.nta [loc3]=f82,-256
546 ;;
547 stf.spill.nta [loc2]=f74,-256
548 stf.spill.nta [loc3]=f66,-256
549 ;;
550 stf.spill.nta [loc2]=f58,-256
551 stf.spill.nta [loc3]=f50,-256
552 adds loc0=96*16-112,in0
553 ;;
554 stf.spill.nta [loc2]=f42,-256
555 stf.spill.nta [loc3]=f34,-256
556 adds loc1=96*16-112-128,in0
557 ;;
558 stf.spill.nta [loc0]=f121,-256
559 stf.spill.nta [loc1]=f113,-256
560 ;;
561 stf.spill.nta [loc0]=f105,-256
562 stf.spill.nta [loc1]=f97,-256
563 ;;
564 stf.spill.nta [loc0]=f89,-256
565 stf.spill.nta [loc1]=f81,-256
566 ;;
567 stf.spill.nta [loc0]=f73,-256
568 stf.spill.nta [loc1]=f65,-256
569 ;;
570 stf.spill.nta [loc0]=f57,-256
571 stf.spill.nta [loc1]=f49,-256
572 adds loc2=96*16-128,in0
573 ;;
574 stf.spill.nta [loc0]=f41,-256
575 stf.spill.nta [loc1]=f33,-256
576 adds loc3=96*16-128-128,in0
577 ;;
578 stf.spill.nta [loc2]=f120,-256
579 stf.spill.nta [loc3]=f112,-256
580 ;;
581 stf.spill.nta [loc2]=f104,-256
582 stf.spill.nta [loc3]=f96,-256
583 ;;
584 stf.spill.nta [loc2]=f88,-256
585 stf.spill.nta [loc3]=f80,-256
586 ;;
587 stf.spill.nta [loc2]=f72,-256
588 stf.spill.nta [loc3]=f64,-256
589 ;;
590 stf.spill.nta [loc2]=f56,-256
591 stf.spill.nta [loc3]=f48,-256
592 ;;
593 stf.spill.nta [loc2]=f40
594 stf.spill.nta [loc3]=f32
595 br.ret.sptk.many rp
596END(__ia64_save_fpu)
597
598GLOBAL_ENTRY(__ia64_load_fpu)
599 alloc r2=ar.pfs,1,2,0,0
600 adds r3=128,in0
601 adds r14=256,in0
602 adds r15=384,in0
603 mov loc0=512
604 mov loc1=-1024+16
605 ;;
606 ldf.fill.nta f32=[in0],loc0
607 ldf.fill.nta f40=[ r3],loc0
608 ldf.fill.nta f48=[r14],loc0
609 ldf.fill.nta f56=[r15],loc0
610 ;;
611 ldf.fill.nta f64=[in0],loc0
612 ldf.fill.nta f72=[ r3],loc0
613 ldf.fill.nta f80=[r14],loc0
614 ldf.fill.nta f88=[r15],loc0
615 ;;
616 ldf.fill.nta f96=[in0],loc1
617 ldf.fill.nta f104=[ r3],loc1
618 ldf.fill.nta f112=[r14],loc1
619 ldf.fill.nta f120=[r15],loc1
620 ;;
621 ldf.fill.nta f33=[in0],loc0
622 ldf.fill.nta f41=[ r3],loc0
623 ldf.fill.nta f49=[r14],loc0
624 ldf.fill.nta f57=[r15],loc0
625 ;;
626 ldf.fill.nta f65=[in0],loc0
627 ldf.fill.nta f73=[ r3],loc0
628 ldf.fill.nta f81=[r14],loc0
629 ldf.fill.nta f89=[r15],loc0
630 ;;
631 ldf.fill.nta f97=[in0],loc1
632 ldf.fill.nta f105=[ r3],loc1
633 ldf.fill.nta f113=[r14],loc1
634 ldf.fill.nta f121=[r15],loc1
635 ;;
636 ldf.fill.nta f34=[in0],loc0
637 ldf.fill.nta f42=[ r3],loc0
638 ldf.fill.nta f50=[r14],loc0
639 ldf.fill.nta f58=[r15],loc0
640 ;;
641 ldf.fill.nta f66=[in0],loc0
642 ldf.fill.nta f74=[ r3],loc0
643 ldf.fill.nta f82=[r14],loc0
644 ldf.fill.nta f90=[r15],loc0
645 ;;
646 ldf.fill.nta f98=[in0],loc1
647 ldf.fill.nta f106=[ r3],loc1
648 ldf.fill.nta f114=[r14],loc1
649 ldf.fill.nta f122=[r15],loc1
650 ;;
651 ldf.fill.nta f35=[in0],loc0
652 ldf.fill.nta f43=[ r3],loc0
653 ldf.fill.nta f51=[r14],loc0
654 ldf.fill.nta f59=[r15],loc0
655 ;;
656 ldf.fill.nta f67=[in0],loc0
657 ldf.fill.nta f75=[ r3],loc0
658 ldf.fill.nta f83=[r14],loc0
659 ldf.fill.nta f91=[r15],loc0
660 ;;
661 ldf.fill.nta f99=[in0],loc1
662 ldf.fill.nta f107=[ r3],loc1
663 ldf.fill.nta f115=[r14],loc1
664 ldf.fill.nta f123=[r15],loc1
665 ;;
666 ldf.fill.nta f36=[in0],loc0
667 ldf.fill.nta f44=[ r3],loc0
668 ldf.fill.nta f52=[r14],loc0
669 ldf.fill.nta f60=[r15],loc0
670 ;;
671 ldf.fill.nta f68=[in0],loc0
672 ldf.fill.nta f76=[ r3],loc0
673 ldf.fill.nta f84=[r14],loc0
674 ldf.fill.nta f92=[r15],loc0
675 ;;
676 ldf.fill.nta f100=[in0],loc1
677 ldf.fill.nta f108=[ r3],loc1
678 ldf.fill.nta f116=[r14],loc1
679 ldf.fill.nta f124=[r15],loc1
680 ;;
681 ldf.fill.nta f37=[in0],loc0
682 ldf.fill.nta f45=[ r3],loc0
683 ldf.fill.nta f53=[r14],loc0
684 ldf.fill.nta f61=[r15],loc0
685 ;;
686 ldf.fill.nta f69=[in0],loc0
687 ldf.fill.nta f77=[ r3],loc0
688 ldf.fill.nta f85=[r14],loc0
689 ldf.fill.nta f93=[r15],loc0
690 ;;
691 ldf.fill.nta f101=[in0],loc1
692 ldf.fill.nta f109=[ r3],loc1
693 ldf.fill.nta f117=[r14],loc1
694 ldf.fill.nta f125=[r15],loc1
695 ;;
696 ldf.fill.nta f38 =[in0],loc0
697 ldf.fill.nta f46 =[ r3],loc0
698 ldf.fill.nta f54 =[r14],loc0
699 ldf.fill.nta f62 =[r15],loc0
700 ;;
701 ldf.fill.nta f70 =[in0],loc0
702 ldf.fill.nta f78 =[ r3],loc0
703 ldf.fill.nta f86 =[r14],loc0
704 ldf.fill.nta f94 =[r15],loc0
705 ;;
706 ldf.fill.nta f102=[in0],loc1
707 ldf.fill.nta f110=[ r3],loc1
708 ldf.fill.nta f118=[r14],loc1
709 ldf.fill.nta f126=[r15],loc1
710 ;;
711 ldf.fill.nta f39 =[in0],loc0
712 ldf.fill.nta f47 =[ r3],loc0
713 ldf.fill.nta f55 =[r14],loc0
714 ldf.fill.nta f63 =[r15],loc0
715 ;;
716 ldf.fill.nta f71 =[in0],loc0
717 ldf.fill.nta f79 =[ r3],loc0
718 ldf.fill.nta f87 =[r14],loc0
719 ldf.fill.nta f95 =[r15],loc0
720 ;;
721 ldf.fill.nta f103=[in0]
722 ldf.fill.nta f111=[ r3]
723 ldf.fill.nta f119=[r14]
724 ldf.fill.nta f127=[r15]
725 br.ret.sptk.many rp
726END(__ia64_load_fpu)
727
728GLOBAL_ENTRY(__ia64_init_fpu)
729 stf.spill [sp]=f0 // M3
730 mov f32=f0 // F
731 nop.b 0
732
733 ldfps f33,f34=[sp] // M0
734 ldfps f35,f36=[sp] // M1
735 mov f37=f0 // F
736 ;;
737
738 setf.s f38=r0 // M2
739 setf.s f39=r0 // M3
740 mov f40=f0 // F
741
742 ldfps f41,f42=[sp] // M0
743 ldfps f43,f44=[sp] // M1
744 mov f45=f0 // F
745
746 setf.s f46=r0 // M2
747 setf.s f47=r0 // M3
748 mov f48=f0 // F
749
750 ldfps f49,f50=[sp] // M0
751 ldfps f51,f52=[sp] // M1
752 mov f53=f0 // F
753
754 setf.s f54=r0 // M2
755 setf.s f55=r0 // M3
756 mov f56=f0 // F
757
758 ldfps f57,f58=[sp] // M0
759 ldfps f59,f60=[sp] // M1
760 mov f61=f0 // F
761
762 setf.s f62=r0 // M2
763 setf.s f63=r0 // M3
764 mov f64=f0 // F
765
766 ldfps f65,f66=[sp] // M0
767 ldfps f67,f68=[sp] // M1
768 mov f69=f0 // F
769
770 setf.s f70=r0 // M2
771 setf.s f71=r0 // M3
772 mov f72=f0 // F
773
774 ldfps f73,f74=[sp] // M0
775 ldfps f75,f76=[sp] // M1
776 mov f77=f0 // F
777
778 setf.s f78=r0 // M2
779 setf.s f79=r0 // M3
780 mov f80=f0 // F
781
782 ldfps f81,f82=[sp] // M0
783 ldfps f83,f84=[sp] // M1
784 mov f85=f0 // F
785
786 setf.s f86=r0 // M2
787 setf.s f87=r0 // M3
788 mov f88=f0 // F
789
790 /*
791 * When the instructions are cached, it would be faster to initialize
792 * the remaining registers with simply mov instructions (F-unit).
793 * This gets the time down to ~29 cycles. However, this would use up
794 * 33 bundles, whereas continuing with the above pattern yields
795 * 10 bundles and ~30 cycles.
796 */
797
798 ldfps f89,f90=[sp] // M0
799 ldfps f91,f92=[sp] // M1
800 mov f93=f0 // F
801
802 setf.s f94=r0 // M2
803 setf.s f95=r0 // M3
804 mov f96=f0 // F
805
806 ldfps f97,f98=[sp] // M0
807 ldfps f99,f100=[sp] // M1
808 mov f101=f0 // F
809
810 setf.s f102=r0 // M2
811 setf.s f103=r0 // M3
812 mov f104=f0 // F
813
814 ldfps f105,f106=[sp] // M0
815 ldfps f107,f108=[sp] // M1
816 mov f109=f0 // F
817
818 setf.s f110=r0 // M2
819 setf.s f111=r0 // M3
820 mov f112=f0 // F
821
822 ldfps f113,f114=[sp] // M0
823 ldfps f115,f116=[sp] // M1
824 mov f117=f0 // F
825
826 setf.s f118=r0 // M2
827 setf.s f119=r0 // M3
828 mov f120=f0 // F
829
830 ldfps f121,f122=[sp] // M0
831 ldfps f123,f124=[sp] // M1
832 mov f125=f0 // F
833
834 setf.s f126=r0 // M2
835 setf.s f127=r0 // M3
836 br.ret.sptk.many rp // F
837END(__ia64_init_fpu)
838
839/*
840 * Switch execution mode from virtual to physical
841 *
842 * Inputs:
843 * r16 = new psr to establish
844 * Output:
845 * r19 = old virtual address of ar.bsp
846 * r20 = old virtual address of sp
847 *
848 * Note: RSE must already be in enforced lazy mode
849 */
850GLOBAL_ENTRY(ia64_switch_mode_phys)
851 {
852 alloc r2=ar.pfs,0,0,0,0
853 rsm psr.i | psr.ic // disable interrupts and interrupt collection
854 mov r15=ip
855 }
856 ;;
857 {
858 flushrs // must be first insn in group
859 srlz.i
860 }
861 ;;
862 mov cr.ipsr=r16 // set new PSR
863 add r3=1f-ia64_switch_mode_phys,r15
864
865 mov r19=ar.bsp
866 mov r20=sp
867 mov r14=rp // get return address into a general register
868 ;;
869
870 // going to physical mode, use tpa to translate virt->phys
871 tpa r17=r19
872 tpa r3=r3
873 tpa sp=sp
874 tpa r14=r14
875 ;;
876
877 mov r18=ar.rnat // save ar.rnat
878 mov ar.bspstore=r17 // this steps on ar.rnat
879 mov cr.iip=r3
880 mov cr.ifs=r0
881 ;;
882 mov ar.rnat=r18 // restore ar.rnat
883 rfi // must be last insn in group
884 ;;
8851: mov rp=r14
886 br.ret.sptk.many rp
887END(ia64_switch_mode_phys)
888
889/*
890 * Switch execution mode from physical to virtual
891 *
892 * Inputs:
893 * r16 = new psr to establish
894 * r19 = new bspstore to establish
895 * r20 = new sp to establish
896 *
897 * Note: RSE must already be in enforced lazy mode
898 */
899GLOBAL_ENTRY(ia64_switch_mode_virt)
900 {
901 alloc r2=ar.pfs,0,0,0,0
902 rsm psr.i | psr.ic // disable interrupts and interrupt collection
903 mov r15=ip
904 }
905 ;;
906 {
907 flushrs // must be first insn in group
908 srlz.i
909 }
910 ;;
911 mov cr.ipsr=r16 // set new PSR
912 add r3=1f-ia64_switch_mode_virt,r15
913
914 mov r14=rp // get return address into a general register
915 ;;
916
917 // going to virtual
918 // - for code addresses, set upper bits of addr to KERNEL_START
919 // - for stack addresses, copy from input argument
920 movl r18=KERNEL_START
921 dep r3=0,r3,KERNEL_TR_PAGE_SHIFT,64-KERNEL_TR_PAGE_SHIFT
922 dep r14=0,r14,KERNEL_TR_PAGE_SHIFT,64-KERNEL_TR_PAGE_SHIFT
923 mov sp=r20
924 ;;
925 or r3=r3,r18
926 or r14=r14,r18
927 ;;
928
929 mov r18=ar.rnat // save ar.rnat
930 mov ar.bspstore=r19 // this steps on ar.rnat
931 mov cr.iip=r3
932 mov cr.ifs=r0
933 ;;
934 mov ar.rnat=r18 // restore ar.rnat
935 rfi // must be last insn in group
936 ;;
9371: mov rp=r14
938 br.ret.sptk.many rp
939END(ia64_switch_mode_virt)
940
941GLOBAL_ENTRY(ia64_delay_loop)
942 .prologue
943{ nop 0 // work around GAS unwind info generation bug...
944 .save ar.lc,r2
945 mov r2=ar.lc
946 .body
947 ;;
948 mov ar.lc=r32
949}
950 ;;
951 // force loop to be 32-byte aligned (GAS bug means we cannot use .align
952 // inside function body without corrupting unwind info).
953{ nop 0 }
9541: br.cloop.sptk.few 1b
955 ;;
956 mov ar.lc=r2
957 br.ret.sptk.many rp
958END(ia64_delay_loop)
959
960/*
961 * Return a CPU-local timestamp in nano-seconds. This timestamp is
962 * NOT synchronized across CPUs its return value must never be
963 * compared against the values returned on another CPU. The usage in
964 * kernel/sched.c ensures that.
965 *
966 * The return-value of sched_clock() is NOT supposed to wrap-around.
967 * If it did, it would cause some scheduling hiccups (at the worst).
968 * Fortunately, with a 64-bit cycle-counter ticking at 100GHz, even
969 * that would happen only once every 5+ years.
970 *
971 * The code below basically calculates:
972 *
973 * (ia64_get_itc() * local_cpu_data->nsec_per_cyc) >> IA64_NSEC_PER_CYC_SHIFT
974 *
975 * except that the multiplication and the shift are done with 128-bit
976 * intermediate precision so that we can produce a full 64-bit result.
977 */
978GLOBAL_ENTRY(sched_clock)
979 addl r8=THIS_CPU(cpu_info) + IA64_CPUINFO_NSEC_PER_CYC_OFFSET,r0
980 mov.m r9=ar.itc // fetch cycle-counter (35 cyc)
981 ;;
982 ldf8 f8=[r8]
983 ;;
984 setf.sig f9=r9 // certain to stall, so issue it _after_ ldf8...
985 ;;
986 xmpy.lu f10=f9,f8 // calculate low 64 bits of 128-bit product (4 cyc)
987 xmpy.hu f11=f9,f8 // calculate high 64 bits of 128-bit product
988 ;;
989 getf.sig r8=f10 // (5 cyc)
990 getf.sig r9=f11
991 ;;
992 shrp r8=r9,r8,IA64_NSEC_PER_CYC_SHIFT
993 br.ret.sptk.many rp
994END(sched_clock)
995
996GLOBAL_ENTRY(start_kernel_thread)
997 .prologue
998 .save rp, r0 // this is the end of the call-chain
999 .body
1000 alloc r2 = ar.pfs, 0, 0, 2, 0
1001 mov out0 = r9
1002 mov out1 = r11;;
1003 br.call.sptk.many rp = kernel_thread_helper;;
1004 mov out0 = r8
1005 br.call.sptk.many rp = sys_exit;;
10061: br.sptk.few 1b // not reached
1007END(start_kernel_thread)
1008
1009#ifdef CONFIG_IA64_BRL_EMU
1010
1011/*
1012 * Assembly routines used by brl_emu.c to set preserved register state.
1013 */
1014
1015#define SET_REG(reg) \
1016 GLOBAL_ENTRY(ia64_set_##reg); \
1017 alloc r16=ar.pfs,1,0,0,0; \
1018 mov reg=r32; \
1019 ;; \
1020 br.ret.sptk.many rp; \
1021 END(ia64_set_##reg)
1022
1023SET_REG(b1);
1024SET_REG(b2);
1025SET_REG(b3);
1026SET_REG(b4);
1027SET_REG(b5);
1028
1029#endif /* CONFIG_IA64_BRL_EMU */
1030
1031#ifdef CONFIG_SMP
1032 /*
1033 * This routine handles spinlock contention. It uses a non-standard calling
1034 * convention to avoid converting leaf routines into interior routines. Because
1035 * of this special convention, there are several restrictions:
1036 *
1037 * - do not use gp relative variables, this code is called from the kernel
1038 * and from modules, r1 is undefined.
1039 * - do not use stacked registers, the caller owns them.
1040 * - do not use the scratch stack space, the caller owns it.
1041 * - do not use any registers other than the ones listed below
1042 *
1043 * Inputs:
1044 * ar.pfs - saved CFM of caller
1045 * ar.ccv - 0 (and available for use)
1046 * r27 - flags from spin_lock_irqsave or 0. Must be preserved.
1047 * r28 - available for use.
1048 * r29 - available for use.
1049 * r30 - available for use.
1050 * r31 - address of lock, available for use.
1051 * b6 - return address
1052 * p14 - available for use.
1053 * p15 - used to track flag status.
1054 *
1055 * If you patch this code to use more registers, do not forget to update
1056 * the clobber lists for spin_lock() in include/asm-ia64/spinlock.h.
1057 */
1058
1059#if __GNUC__ < 3 || (__GNUC__ == 3 && __GNUC_MINOR__ < 3)
1060
1061GLOBAL_ENTRY(ia64_spinlock_contention_pre3_4)
1062 .prologue
1063 .save ar.pfs, r0 // this code effectively has a zero frame size
1064 .save rp, r28
1065 .body
1066 nop 0
1067 tbit.nz p15,p0=r27,IA64_PSR_I_BIT
1068 .restore sp // pop existing prologue after next insn
1069 mov b6 = r28
1070 .prologue
1071 .save ar.pfs, r0
1072 .altrp b6
1073 .body
1074 ;;
1075(p15) ssm psr.i // reenable interrupts if they were on
1076 // DavidM says that srlz.d is slow and is not required in this case
1077.wait:
1078 // exponential backoff, kdb, lockmeter etc. go in here
1079 hint @pause
1080 ld4 r30=[r31] // don't use ld4.bias; if it's contended, we won't write the word
1081 nop 0
1082 ;;
1083 cmp4.ne p14,p0=r30,r0
1084(p14) br.cond.sptk.few .wait
1085(p15) rsm psr.i // disable interrupts if we reenabled them
1086 br.cond.sptk.few b6 // lock is now free, try to acquire
1087 .global ia64_spinlock_contention_pre3_4_end // for kernprof
1088ia64_spinlock_contention_pre3_4_end:
1089END(ia64_spinlock_contention_pre3_4)
1090
1091#else
1092
1093GLOBAL_ENTRY(ia64_spinlock_contention)
1094 .prologue
1095 .altrp b6
1096 .body
1097 tbit.nz p15,p0=r27,IA64_PSR_I_BIT
1098 ;;
1099.wait:
1100(p15) ssm psr.i // reenable interrupts if they were on
1101 // DavidM says that srlz.d is slow and is not required in this case
1102.wait2:
1103 // exponential backoff, kdb, lockmeter etc. go in here
1104 hint @pause
1105 ld4 r30=[r31] // don't use ld4.bias; if it's contended, we won't write the word
1106 ;;
1107 cmp4.ne p14,p0=r30,r0
1108 mov r30 = 1
1109(p14) br.cond.sptk.few .wait2
1110(p15) rsm psr.i // disable interrupts if we reenabled them
1111 ;;
1112 cmpxchg4.acq r30=[r31], r30, ar.ccv
1113 ;;
1114 cmp4.ne p14,p0=r0,r30
1115(p14) br.cond.sptk.few .wait
1116
1117 br.ret.sptk.many b6 // lock is now taken
1118END(ia64_spinlock_contention)
1119
1120#endif
1121
b8d8b883
AR		 1122#ifdef CONFIG_HOTPLUG_CPU
1123GLOBAL_ENTRY(ia64_jump_to_sal)
1124 alloc r16=ar.pfs,1,0,0,0;;
1125 rsm psr.i | psr.ic
1126{
1127 flushrs
1128 srlz.i
1129}
1130 tpa r25=in0
1131 movl r18=tlb_purge_done;;
1132 DATA_VA_TO_PA(r18);;
1133 mov b1=r18 // Return location
1134 movl r18=ia64_do_tlb_purge;;
1135 DATA_VA_TO_PA(r18);;
1136 mov b2=r18 // doing tlb_flush work
1137 mov ar.rsc=0 // Put RSE in enforced lazy, LE mode
1138 movl r17=1f;;
1139 DATA_VA_TO_PA(r17);;
1140 mov cr.iip=r17
1141 movl r16=SAL_PSR_BITS_TO_SET;;
1142 mov cr.ipsr=r16
1143 mov cr.ifs=r0;;
1144 rfi;;
11451:
1146 /*
1147 * Invalidate all TLB data/inst
1148 */
1149 br.sptk.many b2;; // jump to tlb purge code
1150
1151tlb_purge_done:
1152 RESTORE_REGION_REGS(r25, r17,r18,r19);;
1153 RESTORE_REG(b0, r25, r17);;
1154 RESTORE_REG(b1, r25, r17);;
1155 RESTORE_REG(b2, r25, r17);;
1156 RESTORE_REG(b3, r25, r17);;
1157 RESTORE_REG(b4, r25, r17);;
1158 RESTORE_REG(b5, r25, r17);;
1159 ld8 r1=[r25],0x08;;
1160 ld8 r12=[r25],0x08;;
1161 ld8 r13=[r25],0x08;;
1162 RESTORE_REG(ar.fpsr, r25, r17);;
1163 RESTORE_REG(ar.pfs, r25, r17);;
1164 RESTORE_REG(ar.rnat, r25, r17);;
1165 RESTORE_REG(ar.unat, r25, r17);;
1166 RESTORE_REG(ar.bspstore, r25, r17);;
1167 RESTORE_REG(cr.dcr, r25, r17);;
1168 RESTORE_REG(cr.iva, r25, r17);;
1169 RESTORE_REG(cr.pta, r25, r17);;
1170 RESTORE_REG(cr.itv, r25, r17);;
1171 RESTORE_REG(cr.pmv, r25, r17);;
1172 RESTORE_REG(cr.cmcv, r25, r17);;
1173 RESTORE_REG(cr.lrr0, r25, r17);;
1174 RESTORE_REG(cr.lrr1, r25, r17);;
1175 ld8 r4=[r25],0x08;;
1176 ld8 r5=[r25],0x08;;
1177 ld8 r6=[r25],0x08;;
1178 ld8 r7=[r25],0x08;;
1179 ld8 r17=[r25],0x08;;
1180 mov pr=r17,-1;;
1181 RESTORE_REG(ar.lc, r25, r17);;
1182 /*
1183 * Now Restore floating point regs
1184 */
1185 ldf.fill.nta f2=[r25],16;;
1186 ldf.fill.nta f3=[r25],16;;
1187 ldf.fill.nta f4=[r25],16;;
1188 ldf.fill.nta f5=[r25],16;;
1189 ldf.fill.nta f16=[r25],16;;
1190 ldf.fill.nta f17=[r25],16;;
1191 ldf.fill.nta f18=[r25],16;;
1192 ldf.fill.nta f19=[r25],16;;
1193 ldf.fill.nta f20=[r25],16;;
1194 ldf.fill.nta f21=[r25],16;;
1195 ldf.fill.nta f22=[r25],16;;
1196 ldf.fill.nta f23=[r25],16;;
1197 ldf.fill.nta f24=[r25],16;;
1198 ldf.fill.nta f25=[r25],16;;
1199 ldf.fill.nta f26=[r25],16;;
1200 ldf.fill.nta f27=[r25],16;;
1201 ldf.fill.nta f28=[r25],16;;
1202 ldf.fill.nta f29=[r25],16;;
1203 ldf.fill.nta f30=[r25],16;;
1204 ldf.fill.nta f31=[r25],16;;
1205
1206 /*
1207 * Now that we have done all the register restores
1208 * we are now ready for the big DIVE to SAL Land
1209 */
1210 ssm psr.ic;;
1211 srlz.d;;
1212 br.ret.sptk.many b0;;
1213END(ia64_jump_to_sal)
1214#endif /* CONFIG_HOTPLUG_CPU */
1215
1da177e4 1216#endif /* CONFIG_SMP */
kernel source for telekom puls (alcatel/mediatek)