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[IA64] Unwire set/get_robust_list
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / ia64 / kernel / head.S
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1da177e4
LT		 1/*
2 * Here is where the ball gets rolling as far as the kernel is concerned.
3 * When control is transferred to _start, the bootload has already
4 * loaded us to the correct address. All that's left to do here is
5 * to set up the kernel's global pointer and jump to the kernel
6 * entry point.
7 *
8 * Copyright (C) 1998-2001, 2003, 2005 Hewlett-Packard Co
9 * David Mosberger-Tang <davidm@hpl.hp.com>
10 * Stephane Eranian <eranian@hpl.hp.com>
11 * Copyright (C) 1999 VA Linux Systems
12 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
13 * Copyright (C) 1999 Intel Corp.
14 * Copyright (C) 1999 Asit Mallick <Asit.K.Mallick@intel.com>
15 * Copyright (C) 1999 Don Dugger <Don.Dugger@intel.com>
16 * Copyright (C) 2002 Fenghua Yu <fenghua.yu@intel.com>
17 * -Optimize __ia64_save_fpu() and __ia64_load_fpu() for Itanium 2.
b8d8b883
AR		 18 * Copyright (C) 2004 Ashok Raj <ashok.raj@intel.com>
19 * Support for CPU Hotplug
1da177e4
LT		 20 */
21
1da177e4
LT		 22
23#include <asm/asmmacro.h>
24#include <asm/fpu.h>
25#include <asm/kregs.h>
26#include <asm/mmu_context.h>
39e01cb8 27#include <asm/asm-offsets.h>
1da177e4
LT		 28#include <asm/pal.h>
29#include <asm/pgtable.h>
30#include <asm/processor.h>
31#include <asm/ptrace.h>
32#include <asm/system.h>
b8d8b883
AR		 33#include <asm/mca_asm.h>
34
35#ifdef CONFIG_HOTPLUG_CPU
36#define SAL_PSR_BITS_TO_SET \
37 (IA64_PSR_AC | IA64_PSR_BN | IA64_PSR_MFH | IA64_PSR_MFL)
38
39#define SAVE_FROM_REG(src, ptr, dest) \
40 mov dest=src;; \
41 st8 [ptr]=dest,0x08
42
43#define RESTORE_REG(reg, ptr, _tmp) \
44 ld8 _tmp=[ptr],0x08;; \
45 mov reg=_tmp
46
47#define SAVE_BREAK_REGS(ptr, _idx, _breg, _dest)\
48 mov ar.lc=IA64_NUM_DBG_REGS-1;; \
49 mov _idx=0;; \
501: \
51 SAVE_FROM_REG(_breg[_idx], ptr, _dest);; \
52 add _idx=1,_idx;; \
53 br.cloop.sptk.many 1b
54
55#define RESTORE_BREAK_REGS(ptr, _idx, _breg, _tmp, _lbl)\
56 mov ar.lc=IA64_NUM_DBG_REGS-1;; \
57 mov _idx=0;; \
58_lbl: RESTORE_REG(_breg[_idx], ptr, _tmp);; \
59 add _idx=1, _idx;; \
60 br.cloop.sptk.many _lbl
61
62#define SAVE_ONE_RR(num, _reg, _tmp) \
63 movl _tmp=(num<<61);; \
64 mov _reg=rr[_tmp]
65
66#define SAVE_REGION_REGS(_tmp, _r0, _r1, _r2, _r3, _r4, _r5, _r6, _r7) \
67 SAVE_ONE_RR(0,_r0, _tmp);; \
68 SAVE_ONE_RR(1,_r1, _tmp);; \
69 SAVE_ONE_RR(2,_r2, _tmp);; \
70 SAVE_ONE_RR(3,_r3, _tmp);; \
71 SAVE_ONE_RR(4,_r4, _tmp);; \
72 SAVE_ONE_RR(5,_r5, _tmp);; \
73 SAVE_ONE_RR(6,_r6, _tmp);; \
74 SAVE_ONE_RR(7,_r7, _tmp);;
75
76#define STORE_REGION_REGS(ptr, _r0, _r1, _r2, _r3, _r4, _r5, _r6, _r7) \
77 st8 [ptr]=_r0, 8;; \
78 st8 [ptr]=_r1, 8;; \
79 st8 [ptr]=_r2, 8;; \
80 st8 [ptr]=_r3, 8;; \
81 st8 [ptr]=_r4, 8;; \
82 st8 [ptr]=_r5, 8;; \
83 st8 [ptr]=_r6, 8;; \
84 st8 [ptr]=_r7, 8;;
85
86#define RESTORE_REGION_REGS(ptr, _idx1, _idx2, _tmp) \
87 mov ar.lc=0x08-1;; \
88 movl _idx1=0x00;; \
89RestRR: \
90 dep.z _idx2=_idx1,61,3;; \
91 ld8 _tmp=[ptr],8;; \
92 mov rr[_idx2]=_tmp;; \
93 srlz.d;; \
94 add _idx1=1,_idx1;; \
95 br.cloop.sptk.few RestRR
96
df6c6804
AR		 97#define SET_AREA_FOR_BOOTING_CPU(reg1, reg2) \
98 movl reg1=sal_state_for_booting_cpu;; \
99 ld8 reg2=[reg1];;
100
b8d8b883
AR		 101/*
102 * Adjust region registers saved before starting to save
103 * break regs and rest of the states that need to be preserved.
104 */
105#define SAL_TO_OS_BOOT_HANDOFF_STATE_SAVE(_reg1,_reg2,_pred) \
106 SAVE_FROM_REG(b0,_reg1,_reg2);; \
107 SAVE_FROM_REG(b1,_reg1,_reg2);; \
108 SAVE_FROM_REG(b2,_reg1,_reg2);; \
109 SAVE_FROM_REG(b3,_reg1,_reg2);; \
110 SAVE_FROM_REG(b4,_reg1,_reg2);; \
111 SAVE_FROM_REG(b5,_reg1,_reg2);; \
112 st8 [_reg1]=r1,0x08;; \
113 st8 [_reg1]=r12,0x08;; \
114 st8 [_reg1]=r13,0x08;; \
115 SAVE_FROM_REG(ar.fpsr,_reg1,_reg2);; \
116 SAVE_FROM_REG(ar.pfs,_reg1,_reg2);; \
117 SAVE_FROM_REG(ar.rnat,_reg1,_reg2);; \
118 SAVE_FROM_REG(ar.unat,_reg1,_reg2);; \
119 SAVE_FROM_REG(ar.bspstore,_reg1,_reg2);; \
120 SAVE_FROM_REG(cr.dcr,_reg1,_reg2);; \
121 SAVE_FROM_REG(cr.iva,_reg1,_reg2);; \
122 SAVE_FROM_REG(cr.pta,_reg1,_reg2);; \
123 SAVE_FROM_REG(cr.itv,_reg1,_reg2);; \
124 SAVE_FROM_REG(cr.pmv,_reg1,_reg2);; \
125 SAVE_FROM_REG(cr.cmcv,_reg1,_reg2);; \
126 SAVE_FROM_REG(cr.lrr0,_reg1,_reg2);; \
127 SAVE_FROM_REG(cr.lrr1,_reg1,_reg2);; \
128 st8 [_reg1]=r4,0x08;; \
129 st8 [_reg1]=r5,0x08;; \
130 st8 [_reg1]=r6,0x08;; \
131 st8 [_reg1]=r7,0x08;; \
132 st8 [_reg1]=_pred,0x08;; \
133 SAVE_FROM_REG(ar.lc, _reg1, _reg2);; \
134 stf.spill.nta [_reg1]=f2,16;; \
135 stf.spill.nta [_reg1]=f3,16;; \
136 stf.spill.nta [_reg1]=f4,16;; \
137 stf.spill.nta [_reg1]=f5,16;; \
138 stf.spill.nta [_reg1]=f16,16;; \
139 stf.spill.nta [_reg1]=f17,16;; \
140 stf.spill.nta [_reg1]=f18,16;; \
141 stf.spill.nta [_reg1]=f19,16;; \
142 stf.spill.nta [_reg1]=f20,16;; \
143 stf.spill.nta [_reg1]=f21,16;; \
144 stf.spill.nta [_reg1]=f22,16;; \
145 stf.spill.nta [_reg1]=f23,16;; \
146 stf.spill.nta [_reg1]=f24,16;; \
147 stf.spill.nta [_reg1]=f25,16;; \
148 stf.spill.nta [_reg1]=f26,16;; \
149 stf.spill.nta [_reg1]=f27,16;; \
150 stf.spill.nta [_reg1]=f28,16;; \
151 stf.spill.nta [_reg1]=f29,16;; \
152 stf.spill.nta [_reg1]=f30,16;; \
153 stf.spill.nta [_reg1]=f31,16;;
154
155#else
df6c6804
AR		 156#define SET_AREA_FOR_BOOTING_CPU(a1, a2)
157#define SAL_TO_OS_BOOT_HANDOFF_STATE_SAVE(a1,a2, a3)
b8d8b883
AR		 158#define SAVE_REGION_REGS(_tmp, _r0, _r1, _r2, _r3, _r4, _r5, _r6, _r7)
159#define STORE_REGION_REGS(ptr, _r0, _r1, _r2, _r3, _r4, _r5, _r6, _r7)
160#endif
161
162#define SET_ONE_RR(num, pgsize, _tmp1, _tmp2, vhpt) \
163 movl _tmp1=(num << 61);; \
164 mov _tmp2=((ia64_rid(IA64_REGION_ID_KERNEL, (num<<61)) << 8) | (pgsize << 2) | vhpt);; \
165 mov rr[_tmp1]=_tmp2
1da177e4
LT		 166
167 .section __special_page_section,"ax"
168
169 .global empty_zero_page
170empty_zero_page:
171 .skip PAGE_SIZE
172
173 .global swapper_pg_dir
174swapper_pg_dir:
175 .skip PAGE_SIZE
176
177 .rodata
178halt_msg:
179 stringz "Halting kernel\n"
180
181 .text
182
183 .global start_ap
184
185 /*
186 * Start the kernel. When the bootloader passes control to _start(), r28
187 * points to the address of the boot parameter area. Execution reaches
188 * here in physical mode.
189 */
190GLOBAL_ENTRY(_start)
191start_ap:
192 .prologue
193 .save rp, r0 // terminate unwind chain with a NULL rp
194 .body
195
196 rsm psr.i | psr.ic
197 ;;
198 srlz.i
199 ;;
b8d8b883
AR		 200 /*
201 * Save the region registers, predicate before they get clobbered
202 */
203 SAVE_REGION_REGS(r2, r8,r9,r10,r11,r12,r13,r14,r15);
204 mov r25=pr;;
205
1da177e4
LT		 206 /*
207 * Initialize kernel region registers:
208 * rr[0]: VHPT enabled, page size = PAGE_SHIFT
209 * rr[1]: VHPT enabled, page size = PAGE_SHIFT
210 * rr[2]: VHPT enabled, page size = PAGE_SHIFT
211 * rr[3]: VHPT enabled, page size = PAGE_SHIFT
212 * rr[4]: VHPT enabled, page size = PAGE_SHIFT
213 * rr[5]: VHPT enabled, page size = PAGE_SHIFT
214 * rr[6]: VHPT disabled, page size = IA64_GRANULE_SHIFT
215 * rr[7]: VHPT disabled, page size = IA64_GRANULE_SHIFT
216 * We initialize all of them to prevent inadvertently assuming
217 * something about the state of address translation early in boot.
218 */
b8d8b883
AR		 219 SET_ONE_RR(0, PAGE_SHIFT, r2, r16, 1);;
220 SET_ONE_RR(1, PAGE_SHIFT, r2, r16, 1);;
221 SET_ONE_RR(2, PAGE_SHIFT, r2, r16, 1);;
222 SET_ONE_RR(3, PAGE_SHIFT, r2, r16, 1);;
223 SET_ONE_RR(4, PAGE_SHIFT, r2, r16, 1);;
224 SET_ONE_RR(5, PAGE_SHIFT, r2, r16, 1);;
225 SET_ONE_RR(6, IA64_GRANULE_SHIFT, r2, r16, 0);;
226 SET_ONE_RR(7, IA64_GRANULE_SHIFT, r2, r16, 0);;
1da177e4
LT		 227 /*
228 * Now pin mappings into the TLB for kernel text and data
229 */
230 mov r18=KERNEL_TR_PAGE_SHIFT<<2
231 movl r17=KERNEL_START
232 ;;
233 mov cr.itir=r18
234 mov cr.ifa=r17
235 mov r16=IA64_TR_KERNEL
236 mov r3=ip
237 movl r18=PAGE_KERNEL
238 ;;
239 dep r2=0,r3,0,KERNEL_TR_PAGE_SHIFT
240 ;;
241 or r18=r2,r18
242 ;;
243 srlz.i
244 ;;
245 itr.i itr[r16]=r18
246 ;;
247 itr.d dtr[r16]=r18
248 ;;
249 srlz.i
250
251 /*
252 * Switch into virtual mode:
253 */
254 movl r16=(IA64_PSR_IT|IA64_PSR_IC|IA64_PSR_DT|IA64_PSR_RT|IA64_PSR_DFH|IA64_PSR_BN \
255 |IA64_PSR_DI)
256 ;;
257 mov cr.ipsr=r16
258 movl r17=1f
259 ;;
260 mov cr.iip=r17
261 mov cr.ifs=r0
262 ;;
263 rfi
264 ;;
2651: // now we are in virtual mode
266
df6c6804 267 SET_AREA_FOR_BOOTING_CPU(r2, r16);
b8d8b883
AR		 268
269 STORE_REGION_REGS(r16, r8,r9,r10,r11,r12,r13,r14,r15);
270 SAL_TO_OS_BOOT_HANDOFF_STATE_SAVE(r16,r17,r25)
271 ;;
272
1da177e4
LT		 273 // set IVT entry point---can't access I/O ports without it
274 movl r3=ia64_ivt
275 ;;
276 mov cr.iva=r3
277 movl r2=FPSR_DEFAULT
278 ;;
279 srlz.i
280 movl gp=__gp
281
282 mov ar.fpsr=r2
283 ;;
284
285#define isAP p2 // are we an Application Processor?
286#define isBP p3 // are we the Bootstrap Processor?
287
288#ifdef CONFIG_SMP
289 /*
290 * Find the init_task for the currently booting CPU. At poweron, and in
291 * UP mode, task_for_booting_cpu is NULL.
292 */
293 movl r3=task_for_booting_cpu
294 ;;
295 ld8 r3=[r3]
296 movl r2=init_task
297 ;;
298 cmp.eq isBP,isAP=r3,r0
299 ;;
300(isAP) mov r2=r3
301#else
302 movl r2=init_task
303 cmp.eq isBP,isAP=r0,r0
304#endif
305 ;;
306 tpa r3=r2 // r3 == phys addr of task struct
307 mov r16=-1
308(isBP) br.cond.dpnt .load_current // BP stack is on region 5 --- no need to map it
309
310 // load mapping for stack (virtaddr in r2, physaddr in r3)
311 rsm psr.ic
312 movl r17=PAGE_KERNEL
313 ;;
314 srlz.d
315 dep r18=0,r3,0,12
316 ;;
317 or r18=r17,r18
318 dep r2=-1,r3,61,3 // IMVA of task
319 ;;
320 mov r17=rr[r2]
321 shr.u r16=r3,IA64_GRANULE_SHIFT
322 ;;
323 dep r17=0,r17,8,24
324 ;;
325 mov cr.itir=r17
326 mov cr.ifa=r2
327
328 mov r19=IA64_TR_CURRENT_STACK
329 ;;
330 itr.d dtr[r19]=r18
331 ;;
332 ssm psr.ic
333 srlz.d
334 ;;
335
336.load_current:
337 // load the "current" pointer (r13) and ar.k6 with the current task
338 mov IA64_KR(CURRENT)=r2 // virtual address
339 mov IA64_KR(CURRENT_STACK)=r16
340 mov r13=r2
341 /*
b8d8b883
AR		 342 * Reserve space at the top of the stack for "struct pt_regs". Kernel
343 * threads don't store interesting values in that structure, but the space
344 * still needs to be there because time-critical stuff such as the context
345 * switching can be implemented more efficiently (for example, __switch_to()
1da177e4
LT		 346 * always sets the psr.dfh bit of the task it is switching to).
347 */
b8d8b883 348
1da177e4
LT		 349 addl r12=IA64_STK_OFFSET-IA64_PT_REGS_SIZE-16,r2
350 addl r2=IA64_RBS_OFFSET,r2 // initialize the RSE
351 mov ar.rsc=0 // place RSE in enforced lazy mode
352 ;;
353 loadrs // clear the dirty partition
d6e56a2a 354 mov IA64_KR(PER_CPU_DATA)=r0 // clear physical per-CPU base
1da177e4
LT		 355 ;;
356 mov ar.bspstore=r2 // establish the new RSE stack
357 ;;
358 mov ar.rsc=0x3 // place RSE in eager mode
359
360(isBP) dep r28=-1,r28,61,3 // make address virtual
361(isBP) movl r2=ia64_boot_param
362 ;;
363(isBP) st8 [r2]=r28 // save the address of the boot param area passed by the bootloader
364
365#ifdef CONFIG_SMP
366(isAP) br.call.sptk.many rp=start_secondary
367.ret0:
368(isAP) br.cond.sptk self
369#endif
370
371 // This is executed by the bootstrap processor (bsp) only:
372
373#ifdef CONFIG_IA64_FW_EMU
374 // initialize PAL & SAL emulator:
375 br.call.sptk.many rp=sys_fw_init
376.ret1:
377#endif
378 br.call.sptk.many rp=start_kernel
379.ret2: addl r3=@ltoff(halt_msg),gp
380 ;;
381 alloc r2=ar.pfs,8,0,2,0
382 ;;
383 ld8 out0=[r3]
384 br.call.sptk.many b0=console_print
385
386self: hint @pause
387 br.sptk.many self // endless loop
388END(_start)
389
390GLOBAL_ENTRY(ia64_save_debug_regs)
391 alloc r16=ar.pfs,1,0,0,0
392 mov r20=ar.lc // preserve ar.lc
393 mov ar.lc=IA64_NUM_DBG_REGS-1
394 mov r18=0
395 add r19=IA64_NUM_DBG_REGS*8,in0
396 ;;
3971: mov r16=dbr[r18]
398#ifdef CONFIG_ITANIUM
399 ;;
400 srlz.d
401#endif
402 mov r17=ibr[r18]
403 add r18=1,r18
404 ;;
405 st8.nta [in0]=r16,8
406 st8.nta [r19]=r17,8
407 br.cloop.sptk.many 1b
408 ;;
409 mov ar.lc=r20 // restore ar.lc
410 br.ret.sptk.many rp
411END(ia64_save_debug_regs)
412
413GLOBAL_ENTRY(ia64_load_debug_regs)
414 alloc r16=ar.pfs,1,0,0,0
415 lfetch.nta [in0]
416 mov r20=ar.lc // preserve ar.lc
417 add r19=IA64_NUM_DBG_REGS*8,in0
418 mov ar.lc=IA64_NUM_DBG_REGS-1
419 mov r18=-1
420 ;;
4211: ld8.nta r16=[in0],8
422 ld8.nta r17=[r19],8
423 add r18=1,r18
424 ;;
425 mov dbr[r18]=r16
426#ifdef CONFIG_ITANIUM
427 ;;
428 srlz.d // Errata 132 (NoFix status)
429#endif
430 mov ibr[r18]=r17
431 br.cloop.sptk.many 1b
432 ;;
433 mov ar.lc=r20 // restore ar.lc
434 br.ret.sptk.many rp
435END(ia64_load_debug_regs)
436
437GLOBAL_ENTRY(__ia64_save_fpu)
438 alloc r2=ar.pfs,1,4,0,0
439 adds loc0=96*16-16,in0
440 adds loc1=96*16-16-128,in0
441 ;;
442 stf.spill.nta [loc0]=f127,-256
443 stf.spill.nta [loc1]=f119,-256
444 ;;
445 stf.spill.nta [loc0]=f111,-256
446 stf.spill.nta [loc1]=f103,-256
447 ;;
448 stf.spill.nta [loc0]=f95,-256
449 stf.spill.nta [loc1]=f87,-256
450 ;;
451 stf.spill.nta [loc0]=f79,-256
452 stf.spill.nta [loc1]=f71,-256
453 ;;
454 stf.spill.nta [loc0]=f63,-256
455 stf.spill.nta [loc1]=f55,-256
456 adds loc2=96*16-32,in0
457 ;;
458 stf.spill.nta [loc0]=f47,-256
459 stf.spill.nta [loc1]=f39,-256
460 adds loc3=96*16-32-128,in0
461 ;;
462 stf.spill.nta [loc2]=f126,-256
463 stf.spill.nta [loc3]=f118,-256
464 ;;
465 stf.spill.nta [loc2]=f110,-256
466 stf.spill.nta [loc3]=f102,-256
467 ;;
468 stf.spill.nta [loc2]=f94,-256
469 stf.spill.nta [loc3]=f86,-256
470 ;;
471 stf.spill.nta [loc2]=f78,-256
472 stf.spill.nta [loc3]=f70,-256
473 ;;
474 stf.spill.nta [loc2]=f62,-256
475 stf.spill.nta [loc3]=f54,-256
476 adds loc0=96*16-48,in0
477 ;;
478 stf.spill.nta [loc2]=f46,-256
479 stf.spill.nta [loc3]=f38,-256
480 adds loc1=96*16-48-128,in0
481 ;;
482 stf.spill.nta [loc0]=f125,-256
483 stf.spill.nta [loc1]=f117,-256
484 ;;
485 stf.spill.nta [loc0]=f109,-256
486 stf.spill.nta [loc1]=f101,-256
487 ;;
488 stf.spill.nta [loc0]=f93,-256
489 stf.spill.nta [loc1]=f85,-256
490 ;;
491 stf.spill.nta [loc0]=f77,-256
492 stf.spill.nta [loc1]=f69,-256
493 ;;
494 stf.spill.nta [loc0]=f61,-256
495 stf.spill.nta [loc1]=f53,-256
496 adds loc2=96*16-64,in0
497 ;;
498 stf.spill.nta [loc0]=f45,-256
499 stf.spill.nta [loc1]=f37,-256
500 adds loc3=96*16-64-128,in0
501 ;;
502 stf.spill.nta [loc2]=f124,-256
503 stf.spill.nta [loc3]=f116,-256
504 ;;
505 stf.spill.nta [loc2]=f108,-256
506 stf.spill.nta [loc3]=f100,-256
507 ;;
508 stf.spill.nta [loc2]=f92,-256
509 stf.spill.nta [loc3]=f84,-256
510 ;;
511 stf.spill.nta [loc2]=f76,-256
512 stf.spill.nta [loc3]=f68,-256
513 ;;
514 stf.spill.nta [loc2]=f60,-256
515 stf.spill.nta [loc3]=f52,-256
516 adds loc0=96*16-80,in0
517 ;;
518 stf.spill.nta [loc2]=f44,-256
519 stf.spill.nta [loc3]=f36,-256
520 adds loc1=96*16-80-128,in0
521 ;;
522 stf.spill.nta [loc0]=f123,-256
523 stf.spill.nta [loc1]=f115,-256
524 ;;
525 stf.spill.nta [loc0]=f107,-256
526 stf.spill.nta [loc1]=f99,-256
527 ;;
528 stf.spill.nta [loc0]=f91,-256
529 stf.spill.nta [loc1]=f83,-256
530 ;;
531 stf.spill.nta [loc0]=f75,-256
532 stf.spill.nta [loc1]=f67,-256
533 ;;
534 stf.spill.nta [loc0]=f59,-256
535 stf.spill.nta [loc1]=f51,-256
536 adds loc2=96*16-96,in0
537 ;;
538 stf.spill.nta [loc0]=f43,-256
539 stf.spill.nta [loc1]=f35,-256
540 adds loc3=96*16-96-128,in0
541 ;;
542 stf.spill.nta [loc2]=f122,-256
543 stf.spill.nta [loc3]=f114,-256
544 ;;
545 stf.spill.nta [loc2]=f106,-256
546 stf.spill.nta [loc3]=f98,-256
547 ;;
548 stf.spill.nta [loc2]=f90,-256
549 stf.spill.nta [loc3]=f82,-256
550 ;;
551 stf.spill.nta [loc2]=f74,-256
552 stf.spill.nta [loc3]=f66,-256
553 ;;
554 stf.spill.nta [loc2]=f58,-256
555 stf.spill.nta [loc3]=f50,-256
556 adds loc0=96*16-112,in0
557 ;;
558 stf.spill.nta [loc2]=f42,-256
559 stf.spill.nta [loc3]=f34,-256
560 adds loc1=96*16-112-128,in0
561 ;;
562 stf.spill.nta [loc0]=f121,-256
563 stf.spill.nta [loc1]=f113,-256
564 ;;
565 stf.spill.nta [loc0]=f105,-256
566 stf.spill.nta [loc1]=f97,-256
567 ;;
568 stf.spill.nta [loc0]=f89,-256
569 stf.spill.nta [loc1]=f81,-256
570 ;;
571 stf.spill.nta [loc0]=f73,-256
572 stf.spill.nta [loc1]=f65,-256
573 ;;
574 stf.spill.nta [loc0]=f57,-256
575 stf.spill.nta [loc1]=f49,-256
576 adds loc2=96*16-128,in0
577 ;;
578 stf.spill.nta [loc0]=f41,-256
579 stf.spill.nta [loc1]=f33,-256
580 adds loc3=96*16-128-128,in0
581 ;;
582 stf.spill.nta [loc2]=f120,-256
583 stf.spill.nta [loc3]=f112,-256
584 ;;
585 stf.spill.nta [loc2]=f104,-256
586 stf.spill.nta [loc3]=f96,-256
587 ;;
588 stf.spill.nta [loc2]=f88,-256
589 stf.spill.nta [loc3]=f80,-256
590 ;;
591 stf.spill.nta [loc2]=f72,-256
592 stf.spill.nta [loc3]=f64,-256
593 ;;
594 stf.spill.nta [loc2]=f56,-256
595 stf.spill.nta [loc3]=f48,-256
596 ;;
597 stf.spill.nta [loc2]=f40
598 stf.spill.nta [loc3]=f32
599 br.ret.sptk.many rp
600END(__ia64_save_fpu)
601
602GLOBAL_ENTRY(__ia64_load_fpu)
603 alloc r2=ar.pfs,1,2,0,0
604 adds r3=128,in0
605 adds r14=256,in0
606 adds r15=384,in0
607 mov loc0=512
608 mov loc1=-1024+16
609 ;;
610 ldf.fill.nta f32=[in0],loc0
611 ldf.fill.nta f40=[ r3],loc0
612 ldf.fill.nta f48=[r14],loc0
613 ldf.fill.nta f56=[r15],loc0
614 ;;
615 ldf.fill.nta f64=[in0],loc0
616 ldf.fill.nta f72=[ r3],loc0
617 ldf.fill.nta f80=[r14],loc0
618 ldf.fill.nta f88=[r15],loc0
619 ;;
620 ldf.fill.nta f96=[in0],loc1
621 ldf.fill.nta f104=[ r3],loc1
622 ldf.fill.nta f112=[r14],loc1
623 ldf.fill.nta f120=[r15],loc1
624 ;;
625 ldf.fill.nta f33=[in0],loc0
626 ldf.fill.nta f41=[ r3],loc0
627 ldf.fill.nta f49=[r14],loc0
628 ldf.fill.nta f57=[r15],loc0
629 ;;
630 ldf.fill.nta f65=[in0],loc0
631 ldf.fill.nta f73=[ r3],loc0
632 ldf.fill.nta f81=[r14],loc0
633 ldf.fill.nta f89=[r15],loc0
634 ;;
635 ldf.fill.nta f97=[in0],loc1
636 ldf.fill.nta f105=[ r3],loc1
637 ldf.fill.nta f113=[r14],loc1
638 ldf.fill.nta f121=[r15],loc1
639 ;;
640 ldf.fill.nta f34=[in0],loc0
641 ldf.fill.nta f42=[ r3],loc0
642 ldf.fill.nta f50=[r14],loc0
643 ldf.fill.nta f58=[r15],loc0
644 ;;
645 ldf.fill.nta f66=[in0],loc0
646 ldf.fill.nta f74=[ r3],loc0
647 ldf.fill.nta f82=[r14],loc0
648 ldf.fill.nta f90=[r15],loc0
649 ;;
650 ldf.fill.nta f98=[in0],loc1
651 ldf.fill.nta f106=[ r3],loc1
652 ldf.fill.nta f114=[r14],loc1
653 ldf.fill.nta f122=[r15],loc1
654 ;;
655 ldf.fill.nta f35=[in0],loc0
656 ldf.fill.nta f43=[ r3],loc0
657 ldf.fill.nta f51=[r14],loc0
658 ldf.fill.nta f59=[r15],loc0
659 ;;
660 ldf.fill.nta f67=[in0],loc0
661 ldf.fill.nta f75=[ r3],loc0
662 ldf.fill.nta f83=[r14],loc0
663 ldf.fill.nta f91=[r15],loc0
664 ;;
665 ldf.fill.nta f99=[in0],loc1
666 ldf.fill.nta f107=[ r3],loc1
667 ldf.fill.nta f115=[r14],loc1
668 ldf.fill.nta f123=[r15],loc1
669 ;;
670 ldf.fill.nta f36=[in0],loc0
671 ldf.fill.nta f44=[ r3],loc0
672 ldf.fill.nta f52=[r14],loc0
673 ldf.fill.nta f60=[r15],loc0
674 ;;
675 ldf.fill.nta f68=[in0],loc0
676 ldf.fill.nta f76=[ r3],loc0
677 ldf.fill.nta f84=[r14],loc0
678 ldf.fill.nta f92=[r15],loc0
679 ;;
680 ldf.fill.nta f100=[in0],loc1
681 ldf.fill.nta f108=[ r3],loc1
682 ldf.fill.nta f116=[r14],loc1
683 ldf.fill.nta f124=[r15],loc1
684 ;;
685 ldf.fill.nta f37=[in0],loc0
686 ldf.fill.nta f45=[ r3],loc0
687 ldf.fill.nta f53=[r14],loc0
688 ldf.fill.nta f61=[r15],loc0
689 ;;
690 ldf.fill.nta f69=[in0],loc0
691 ldf.fill.nta f77=[ r3],loc0
692 ldf.fill.nta f85=[r14],loc0
693 ldf.fill.nta f93=[r15],loc0
694 ;;
695 ldf.fill.nta f101=[in0],loc1
696 ldf.fill.nta f109=[ r3],loc1
697 ldf.fill.nta f117=[r14],loc1
698 ldf.fill.nta f125=[r15],loc1
699 ;;
700 ldf.fill.nta f38 =[in0],loc0
701 ldf.fill.nta f46 =[ r3],loc0
702 ldf.fill.nta f54 =[r14],loc0
703 ldf.fill.nta f62 =[r15],loc0
704 ;;
705 ldf.fill.nta f70 =[in0],loc0
706 ldf.fill.nta f78 =[ r3],loc0
707 ldf.fill.nta f86 =[r14],loc0
708 ldf.fill.nta f94 =[r15],loc0
709 ;;
710 ldf.fill.nta f102=[in0],loc1
711 ldf.fill.nta f110=[ r3],loc1
712 ldf.fill.nta f118=[r14],loc1
713 ldf.fill.nta f126=[r15],loc1
714 ;;
715 ldf.fill.nta f39 =[in0],loc0
716 ldf.fill.nta f47 =[ r3],loc0
717 ldf.fill.nta f55 =[r14],loc0
718 ldf.fill.nta f63 =[r15],loc0
719 ;;
720 ldf.fill.nta f71 =[in0],loc0
721 ldf.fill.nta f79 =[ r3],loc0
722 ldf.fill.nta f87 =[r14],loc0
723 ldf.fill.nta f95 =[r15],loc0
724 ;;
725 ldf.fill.nta f103=[in0]
726 ldf.fill.nta f111=[ r3]
727 ldf.fill.nta f119=[r14]
728 ldf.fill.nta f127=[r15]
729 br.ret.sptk.many rp
730END(__ia64_load_fpu)
731
732GLOBAL_ENTRY(__ia64_init_fpu)
733 stf.spill [sp]=f0 // M3
734 mov f32=f0 // F
735 nop.b 0
736
737 ldfps f33,f34=[sp] // M0
738 ldfps f35,f36=[sp] // M1
739 mov f37=f0 // F
740 ;;
741
742 setf.s f38=r0 // M2
743 setf.s f39=r0 // M3
744 mov f40=f0 // F
745
746 ldfps f41,f42=[sp] // M0
747 ldfps f43,f44=[sp] // M1
748 mov f45=f0 // F
749
750 setf.s f46=r0 // M2
751 setf.s f47=r0 // M3
752 mov f48=f0 // F
753
754 ldfps f49,f50=[sp] // M0
755 ldfps f51,f52=[sp] // M1
756 mov f53=f0 // F
757
758 setf.s f54=r0 // M2
759 setf.s f55=r0 // M3
760 mov f56=f0 // F
761
762 ldfps f57,f58=[sp] // M0
763 ldfps f59,f60=[sp] // M1
764 mov f61=f0 // F
765
766 setf.s f62=r0 // M2
767 setf.s f63=r0 // M3
768 mov f64=f0 // F
769
770 ldfps f65,f66=[sp] // M0
771 ldfps f67,f68=[sp] // M1
772 mov f69=f0 // F
773
774 setf.s f70=r0 // M2
775 setf.s f71=r0 // M3
776 mov f72=f0 // F
777
778 ldfps f73,f74=[sp] // M0
779 ldfps f75,f76=[sp] // M1
780 mov f77=f0 // F
781
782 setf.s f78=r0 // M2
783 setf.s f79=r0 // M3
784 mov f80=f0 // F
785
786 ldfps f81,f82=[sp] // M0
787 ldfps f83,f84=[sp] // M1
788 mov f85=f0 // F
789
790 setf.s f86=r0 // M2
791 setf.s f87=r0 // M3
792 mov f88=f0 // F
793
794 /*
795 * When the instructions are cached, it would be faster to initialize
796 * the remaining registers with simply mov instructions (F-unit).
797 * This gets the time down to ~29 cycles. However, this would use up
798 * 33 bundles, whereas continuing with the above pattern yields
799 * 10 bundles and ~30 cycles.
800 */
801
802 ldfps f89,f90=[sp] // M0
803 ldfps f91,f92=[sp] // M1
804 mov f93=f0 // F
805
806 setf.s f94=r0 // M2
807 setf.s f95=r0 // M3
808 mov f96=f0 // F
809
810 ldfps f97,f98=[sp] // M0
811 ldfps f99,f100=[sp] // M1
812 mov f101=f0 // F
813
814 setf.s f102=r0 // M2
815 setf.s f103=r0 // M3
816 mov f104=f0 // F
817
818 ldfps f105,f106=[sp] // M0
819 ldfps f107,f108=[sp] // M1
820 mov f109=f0 // F
821
822 setf.s f110=r0 // M2
823 setf.s f111=r0 // M3
824 mov f112=f0 // F
825
826 ldfps f113,f114=[sp] // M0
827 ldfps f115,f116=[sp] // M1
828 mov f117=f0 // F
829
830 setf.s f118=r0 // M2
831 setf.s f119=r0 // M3
832 mov f120=f0 // F
833
834 ldfps f121,f122=[sp] // M0
835 ldfps f123,f124=[sp] // M1
836 mov f125=f0 // F
837
838 setf.s f126=r0 // M2
839 setf.s f127=r0 // M3
840 br.ret.sptk.many rp // F
841END(__ia64_init_fpu)
842
843/*
844 * Switch execution mode from virtual to physical
845 *
846 * Inputs:
847 * r16 = new psr to establish
848 * Output:
849 * r19 = old virtual address of ar.bsp
850 * r20 = old virtual address of sp
851 *
852 * Note: RSE must already be in enforced lazy mode
853 */
854GLOBAL_ENTRY(ia64_switch_mode_phys)
855 {
1da177e4
LT		 856 rsm psr.i | psr.ic // disable interrupts and interrupt collection
857 mov r15=ip
858 }
859 ;;
860 {
861 flushrs // must be first insn in group
862 srlz.i
863 }
864 ;;
865 mov cr.ipsr=r16 // set new PSR
866 add r3=1f-ia64_switch_mode_phys,r15
867
868 mov r19=ar.bsp
869 mov r20=sp
870 mov r14=rp // get return address into a general register
871 ;;
872
873 // going to physical mode, use tpa to translate virt->phys
874 tpa r17=r19
875 tpa r3=r3
876 tpa sp=sp
877 tpa r14=r14
878 ;;
879
880 mov r18=ar.rnat // save ar.rnat
881 mov ar.bspstore=r17 // this steps on ar.rnat
882 mov cr.iip=r3
883 mov cr.ifs=r0
884 ;;
885 mov ar.rnat=r18 // restore ar.rnat
886 rfi // must be last insn in group
887 ;;
8881: mov rp=r14
889 br.ret.sptk.many rp
890END(ia64_switch_mode_phys)
891
892/*
893 * Switch execution mode from physical to virtual
894 *
895 * Inputs:
896 * r16 = new psr to establish
897 * r19 = new bspstore to establish
898 * r20 = new sp to establish
899 *
900 * Note: RSE must already be in enforced lazy mode
901 */
902GLOBAL_ENTRY(ia64_switch_mode_virt)
903 {
1da177e4
LT		 904 rsm psr.i | psr.ic // disable interrupts and interrupt collection
905 mov r15=ip
906 }
907 ;;
908 {
909 flushrs // must be first insn in group
910 srlz.i
911 }
912 ;;
913 mov cr.ipsr=r16 // set new PSR
914 add r3=1f-ia64_switch_mode_virt,r15
915
916 mov r14=rp // get return address into a general register
917 ;;
918
919 // going to virtual
920 // - for code addresses, set upper bits of addr to KERNEL_START
921 // - for stack addresses, copy from input argument
922 movl r18=KERNEL_START
923 dep r3=0,r3,KERNEL_TR_PAGE_SHIFT,64-KERNEL_TR_PAGE_SHIFT
924 dep r14=0,r14,KERNEL_TR_PAGE_SHIFT,64-KERNEL_TR_PAGE_SHIFT
925 mov sp=r20
926 ;;
927 or r3=r3,r18
928 or r14=r14,r18
929 ;;
930
931 mov r18=ar.rnat // save ar.rnat
932 mov ar.bspstore=r19 // this steps on ar.rnat
933 mov cr.iip=r3
934 mov cr.ifs=r0
935 ;;
936 mov ar.rnat=r18 // restore ar.rnat
937 rfi // must be last insn in group
938 ;;
9391: mov rp=r14
940 br.ret.sptk.many rp
941END(ia64_switch_mode_virt)
942
943GLOBAL_ENTRY(ia64_delay_loop)
944 .prologue
945{ nop 0 // work around GAS unwind info generation bug...
946 .save ar.lc,r2
947 mov r2=ar.lc
948 .body
949 ;;
950 mov ar.lc=r32
951}
952 ;;
953 // force loop to be 32-byte aligned (GAS bug means we cannot use .align
954 // inside function body without corrupting unwind info).
955{ nop 0 }
9561: br.cloop.sptk.few 1b
957 ;;
958 mov ar.lc=r2
959 br.ret.sptk.many rp
960END(ia64_delay_loop)
961
962/*
963 * Return a CPU-local timestamp in nano-seconds. This timestamp is
964 * NOT synchronized across CPUs its return value must never be
965 * compared against the values returned on another CPU. The usage in
966 * kernel/sched.c ensures that.
967 *
968 * The return-value of sched_clock() is NOT supposed to wrap-around.
969 * If it did, it would cause some scheduling hiccups (at the worst).
970 * Fortunately, with a 64-bit cycle-counter ticking at 100GHz, even
971 * that would happen only once every 5+ years.
972 *
973 * The code below basically calculates:
974 *
975 * (ia64_get_itc() * local_cpu_data->nsec_per_cyc) >> IA64_NSEC_PER_CYC_SHIFT
976 *
977 * except that the multiplication and the shift are done with 128-bit
978 * intermediate precision so that we can produce a full 64-bit result.
979 */
980GLOBAL_ENTRY(sched_clock)
981 addl r8=THIS_CPU(cpu_info) + IA64_CPUINFO_NSEC_PER_CYC_OFFSET,r0
982 mov.m r9=ar.itc // fetch cycle-counter (35 cyc)
983 ;;
984 ldf8 f8=[r8]
985 ;;
986 setf.sig f9=r9 // certain to stall, so issue it _after_ ldf8...
987 ;;
988 xmpy.lu f10=f9,f8 // calculate low 64 bits of 128-bit product (4 cyc)
989 xmpy.hu f11=f9,f8 // calculate high 64 bits of 128-bit product
990 ;;
991 getf.sig r8=f10 // (5 cyc)
992 getf.sig r9=f11
993 ;;
994 shrp r8=r9,r8,IA64_NSEC_PER_CYC_SHIFT
995 br.ret.sptk.many rp
996END(sched_clock)
997
998GLOBAL_ENTRY(start_kernel_thread)
999 .prologue
1000 .save rp, r0 // this is the end of the call-chain
1001 .body
1002 alloc r2 = ar.pfs, 0, 0, 2, 0
1003 mov out0 = r9
1004 mov out1 = r11;;
1005 br.call.sptk.many rp = kernel_thread_helper;;
1006 mov out0 = r8
1007 br.call.sptk.many rp = sys_exit;;
10081: br.sptk.few 1b // not reached
1009END(start_kernel_thread)
1010
1011#ifdef CONFIG_IA64_BRL_EMU
1012
1013/*
1014 * Assembly routines used by brl_emu.c to set preserved register state.
1015 */
1016
1017#define SET_REG(reg) \
1018 GLOBAL_ENTRY(ia64_set_##reg); \
1019 alloc r16=ar.pfs,1,0,0,0; \
1020 mov reg=r32; \
1021 ;; \
1022 br.ret.sptk.many rp; \
1023 END(ia64_set_##reg)
1024
1025SET_REG(b1);
1026SET_REG(b2);
1027SET_REG(b3);
1028SET_REG(b4);
1029SET_REG(b5);
1030
1031#endif /* CONFIG_IA64_BRL_EMU */
1032
1033#ifdef CONFIG_SMP
1034 /*
1035 * This routine handles spinlock contention. It uses a non-standard calling
1036 * convention to avoid converting leaf routines into interior routines. Because
1037 * of this special convention, there are several restrictions:
1038 *
1039 * - do not use gp relative variables, this code is called from the kernel
1040 * and from modules, r1 is undefined.
1041 * - do not use stacked registers, the caller owns them.
1042 * - do not use the scratch stack space, the caller owns it.
1043 * - do not use any registers other than the ones listed below
1044 *
1045 * Inputs:
1046 * ar.pfs - saved CFM of caller
1047 * ar.ccv - 0 (and available for use)
1048 * r27 - flags from spin_lock_irqsave or 0. Must be preserved.
1049 * r28 - available for use.
1050 * r29 - available for use.
1051 * r30 - available for use.
1052 * r31 - address of lock, available for use.
1053 * b6 - return address
1054 * p14 - available for use.
1055 * p15 - used to track flag status.
1056 *
1057 * If you patch this code to use more registers, do not forget to update
1058 * the clobber lists for spin_lock() in include/asm-ia64/spinlock.h.
1059 */
1060
a1365647 1061#if (__GNUC__ == 3 && __GNUC_MINOR__ < 3)
1da177e4
LT		 1062
1063GLOBAL_ENTRY(ia64_spinlock_contention_pre3_4)
1064 .prologue
1065 .save ar.pfs, r0 // this code effectively has a zero frame size
1066 .save rp, r28
1067 .body
1068 nop 0
1069 tbit.nz p15,p0=r27,IA64_PSR_I_BIT
1070 .restore sp // pop existing prologue after next insn
1071 mov b6 = r28
1072 .prologue
1073 .save ar.pfs, r0
1074 .altrp b6
1075 .body
1076 ;;
1077(p15) ssm psr.i // reenable interrupts if they were on
1078 // DavidM says that srlz.d is slow and is not required in this case
1079.wait:
1080 // exponential backoff, kdb, lockmeter etc. go in here
1081 hint @pause
1082 ld4 r30=[r31] // don't use ld4.bias; if it's contended, we won't write the word
1083 nop 0
1084 ;;
1085 cmp4.ne p14,p0=r30,r0
1086(p14) br.cond.sptk.few .wait
1087(p15) rsm psr.i // disable interrupts if we reenabled them
1088 br.cond.sptk.few b6 // lock is now free, try to acquire
1089 .global ia64_spinlock_contention_pre3_4_end // for kernprof
1090ia64_spinlock_contention_pre3_4_end:
1091END(ia64_spinlock_contention_pre3_4)
1092
1093#else
1094
1095GLOBAL_ENTRY(ia64_spinlock_contention)
1096 .prologue
1097 .altrp b6
1098 .body
1099 tbit.nz p15,p0=r27,IA64_PSR_I_BIT
1100 ;;
1101.wait:
1102(p15) ssm psr.i // reenable interrupts if they were on
1103 // DavidM says that srlz.d is slow and is not required in this case
1104.wait2:
1105 // exponential backoff, kdb, lockmeter etc. go in here
1106 hint @pause
1107 ld4 r30=[r31] // don't use ld4.bias; if it's contended, we won't write the word
1108 ;;
1109 cmp4.ne p14,p0=r30,r0
1110 mov r30 = 1
1111(p14) br.cond.sptk.few .wait2
1112(p15) rsm psr.i // disable interrupts if we reenabled them
1113 ;;
1114 cmpxchg4.acq r30=[r31], r30, ar.ccv
1115 ;;
1116 cmp4.ne p14,p0=r0,r30
1117(p14) br.cond.sptk.few .wait
1118
1119 br.ret.sptk.many b6 // lock is now taken
1120END(ia64_spinlock_contention)
1121
1122#endif
1123
b8d8b883
AR		 1124#ifdef CONFIG_HOTPLUG_CPU
1125GLOBAL_ENTRY(ia64_jump_to_sal)
1126 alloc r16=ar.pfs,1,0,0,0;;
1127 rsm psr.i | psr.ic
1128{
1129 flushrs
1130 srlz.i
1131}
1132 tpa r25=in0
1133 movl r18=tlb_purge_done;;
1134 DATA_VA_TO_PA(r18);;
1135 mov b1=r18 // Return location
1136 movl r18=ia64_do_tlb_purge;;
1137 DATA_VA_TO_PA(r18);;
1138 mov b2=r18 // doing tlb_flush work
1139 mov ar.rsc=0 // Put RSE in enforced lazy, LE mode
1140 movl r17=1f;;
1141 DATA_VA_TO_PA(r17);;
1142 mov cr.iip=r17
1143 movl r16=SAL_PSR_BITS_TO_SET;;
1144 mov cr.ipsr=r16
1145 mov cr.ifs=r0;;
1146 rfi;;
11471:
1148 /*
1149 * Invalidate all TLB data/inst
1150 */
1151 br.sptk.many b2;; // jump to tlb purge code
1152
1153tlb_purge_done:
1154 RESTORE_REGION_REGS(r25, r17,r18,r19);;
1155 RESTORE_REG(b0, r25, r17);;
1156 RESTORE_REG(b1, r25, r17);;
1157 RESTORE_REG(b2, r25, r17);;
1158 RESTORE_REG(b3, r25, r17);;
1159 RESTORE_REG(b4, r25, r17);;
1160 RESTORE_REG(b5, r25, r17);;
1161 ld8 r1=[r25],0x08;;
1162 ld8 r12=[r25],0x08;;
1163 ld8 r13=[r25],0x08;;
1164 RESTORE_REG(ar.fpsr, r25, r17);;
1165 RESTORE_REG(ar.pfs, r25, r17);;
1166 RESTORE_REG(ar.rnat, r25, r17);;
1167 RESTORE_REG(ar.unat, r25, r17);;
1168 RESTORE_REG(ar.bspstore, r25, r17);;
1169 RESTORE_REG(cr.dcr, r25, r17);;
1170 RESTORE_REG(cr.iva, r25, r17);;
1171 RESTORE_REG(cr.pta, r25, r17);;
1172 RESTORE_REG(cr.itv, r25, r17);;
1173 RESTORE_REG(cr.pmv, r25, r17);;
1174 RESTORE_REG(cr.cmcv, r25, r17);;
1175 RESTORE_REG(cr.lrr0, r25, r17);;
1176 RESTORE_REG(cr.lrr1, r25, r17);;
1177 ld8 r4=[r25],0x08;;
1178 ld8 r5=[r25],0x08;;
1179 ld8 r6=[r25],0x08;;
1180 ld8 r7=[r25],0x08;;
1181 ld8 r17=[r25],0x08;;
1182 mov pr=r17,-1;;
1183 RESTORE_REG(ar.lc, r25, r17);;
1184 /*
1185 * Now Restore floating point regs
1186 */
1187 ldf.fill.nta f2=[r25],16;;
1188 ldf.fill.nta f3=[r25],16;;
1189 ldf.fill.nta f4=[r25],16;;
1190 ldf.fill.nta f5=[r25],16;;
1191 ldf.fill.nta f16=[r25],16;;
1192 ldf.fill.nta f17=[r25],16;;
1193 ldf.fill.nta f18=[r25],16;;
1194 ldf.fill.nta f19=[r25],16;;
1195 ldf.fill.nta f20=[r25],16;;
1196 ldf.fill.nta f21=[r25],16;;
1197 ldf.fill.nta f22=[r25],16;;
1198 ldf.fill.nta f23=[r25],16;;
1199 ldf.fill.nta f24=[r25],16;;
1200 ldf.fill.nta f25=[r25],16;;
1201 ldf.fill.nta f26=[r25],16;;
1202 ldf.fill.nta f27=[r25],16;;
1203 ldf.fill.nta f28=[r25],16;;
1204 ldf.fill.nta f29=[r25],16;;
1205 ldf.fill.nta f30=[r25],16;;
1206 ldf.fill.nta f31=[r25],16;;
1207
1208 /*
1209 * Now that we have done all the register restores
1210 * we are now ready for the big DIVE to SAL Land
1211 */
1212 ssm psr.ic;;
1213 srlz.d;;
1214 br.ret.sptk.many b0;;
1215END(ia64_jump_to_sal)
1216#endif /* CONFIG_HOTPLUG_CPU */
1217
1da177e4 1218#endif /* CONFIG_SMP */
kernel source for telekom puls (alcatel/mediatek)