projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 LT |
1 | /* |
| 2 | * | |
| 3 | * This file is subject to the terms and conditions of the GNU General Public | |
| 4 | * License. See the file "COPYING" in the main directory of this archive | |
| 5 | * for more details. | |
| 6 | * | |
| 95ff439a | 7 | * Copyright (c) 2001-2005 Silicon Graphics, Inc. All rights reserved. |
| 1da177e4 LT |
8 | */ |
| 9 | ||
| 10 | #ifndef _ASM_IA64_SN_SHUB_MMR_H | |
| 11 | #define _ASM_IA64_SN_SHUB_MMR_H | |
| 12 | ||
| 13 | /* ==================================================================== */ | |
| 14 | /* Register "SH_IPI_INT" */ | |
| 15 | /* SHub Inter-Processor Interrupt Registers */ | |
| 16 | /* ==================================================================== */ | |
| 8e4641b3 PB |
17 | #define SH1_IPI_INT __IA64_UL_CONST(0x0000000110000380) |
| 18 | #define SH2_IPI_INT __IA64_UL_CONST(0x0000000010000380) | |
| 1da177e4 LT |
19 | |
| 20 | /* SH_IPI_INT_TYPE */ | |
| 21 | /* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ | |
| 8e4641b3 PB |
22 | #define SH_IPI_INT_TYPE_SHFT 0 |
| 23 | #define SH_IPI_INT_TYPE_MASK __IA64_UL_CONST(0x0000000000000007) | |
| 1da177e4 LT |
24 | |
| 25 | /* SH_IPI_INT_AGT */ | |
| 26 | /* Description: Agent, must be 0 for SHub */ | |
| 8e4641b3 PB |
27 | #define SH_IPI_INT_AGT_SHFT 3 |
| 28 | #define SH_IPI_INT_AGT_MASK __IA64_UL_CONST(0x0000000000000008) | |
| 1da177e4 LT |
29 | |
| 30 | /* SH_IPI_INT_PID */ | |
| 31 | /* Description: Processor ID, same setting as on targeted McKinley */ | |
| 8e4641b3 PB |
32 | #define SH_IPI_INT_PID_SHFT 4 |
| 33 | #define SH_IPI_INT_PID_MASK __IA64_UL_CONST(0x00000000000ffff0) | |
| 1da177e4 LT |
34 | |
| 35 | /* SH_IPI_INT_BASE */ | |
| 36 | /* Description: Optional interrupt vector area, 2MB aligned */ | |
| 8e4641b3 PB |
37 | #define SH_IPI_INT_BASE_SHFT 21 |
| 38 | #define SH_IPI_INT_BASE_MASK __IA64_UL_CONST(0x0003ffffffe00000) | |
| 1da177e4 LT |
39 | |
| 40 | /* SH_IPI_INT_IDX */ | |
| 41 | /* Description: Targeted McKinley interrupt vector */ | |
| 8e4641b3 PB |
42 | #define SH_IPI_INT_IDX_SHFT 52 |
| 43 | #define SH_IPI_INT_IDX_MASK __IA64_UL_CONST(0x0ff0000000000000) | |
| 1da177e4 LT |
44 | |
| 45 | /* SH_IPI_INT_SEND */ | |
| 46 | /* Description: Send Interrupt Message to PI, This generates a puls */ | |
| 8e4641b3 PB |
47 | #define SH_IPI_INT_SEND_SHFT 63 |
| 48 | #define SH_IPI_INT_SEND_MASK __IA64_UL_CONST(0x8000000000000000) | |
| 1da177e4 LT |
49 | |
| 50 | /* ==================================================================== */ | |
| 51 | /* Register "SH_EVENT_OCCURRED" */ | |
| 52 | /* SHub Interrupt Event Occurred */ | |
| 53 | /* ==================================================================== */ | |
| 8e4641b3 PB |
54 | #define SH1_EVENT_OCCURRED __IA64_UL_CONST(0x0000000110010000) |
| 55 | #define SH1_EVENT_OCCURRED_ALIAS __IA64_UL_CONST(0x0000000110010008) | |
| 56 | #define SH2_EVENT_OCCURRED __IA64_UL_CONST(0x0000000010010000) | |
| 57 | #define SH2_EVENT_OCCURRED_ALIAS __IA64_UL_CONST(0x0000000010010008) | |
| 1da177e4 LT |
58 | |
| 59 | /* ==================================================================== */ | |
| 60 | /* Register "SH_PI_CAM_CONTROL" */ | |
| 61 | /* CRB CAM MMR Access Control */ | |
| 62 | /* ==================================================================== */ | |
| 8e4641b3 | 63 | #define SH1_PI_CAM_CONTROL __IA64_UL_CONST(0x0000000120050300) |
| 1da177e4 LT |
64 | |
| 65 | /* ==================================================================== */ | |
| 66 | /* Register "SH_SHUB_ID" */ | |
| 67 | /* SHub ID Number */ | |
| 68 | /* ==================================================================== */ | |
| 8e4641b3 PB |
69 | #define SH1_SHUB_ID __IA64_UL_CONST(0x0000000110060580) |
| 70 | #define SH1_SHUB_ID_REVISION_SHFT 28 | |
| 71 | #define SH1_SHUB_ID_REVISION_MASK __IA64_UL_CONST(0x00000000f0000000) | |
| 1da177e4 LT |
72 | |
| 73 | /* ==================================================================== */ | |
| 74 | /* Register "SH_RTC" */ | |
| 75 | /* Real-time Clock */ | |
| 76 | /* ==================================================================== */ | |
| 8e4641b3 PB |
77 | #define SH1_RTC __IA64_UL_CONST(0x00000001101c0000) |
| 78 | #define SH2_RTC __IA64_UL_CONST(0x00000002101c0000) | |
| 79 | #define SH_RTC_MASK __IA64_UL_CONST(0x007fffffffffffff) | |
| 1da177e4 LT |
80 | |
| 81 | /* ==================================================================== */ | |
| 82 | /* Register "SH_PIO_WRITE_STATUS_0|1" */ | |
| 83 | /* PIO Write Status for CPU 0 & 1 */ | |
| 84 | /* ==================================================================== */ | |
| 8e4641b3 PB |
85 | #define SH1_PIO_WRITE_STATUS_0 __IA64_UL_CONST(0x0000000120070200) |
| 86 | #define SH1_PIO_WRITE_STATUS_1 __IA64_UL_CONST(0x0000000120070280) | |
| 87 | #define SH2_PIO_WRITE_STATUS_0 __IA64_UL_CONST(0x0000000020070200) | |
| 88 | #define SH2_PIO_WRITE_STATUS_1 __IA64_UL_CONST(0x0000000020070280) | |
| 89 | #define SH2_PIO_WRITE_STATUS_2 __IA64_UL_CONST(0x0000000020070300) | |
| 90 | #define SH2_PIO_WRITE_STATUS_3 __IA64_UL_CONST(0x0000000020070380) | |
| 1da177e4 LT |
91 | |
| 92 | /* SH_PIO_WRITE_STATUS_0_WRITE_DEADLOCK */ | |
| 93 | /* Description: Deadlock response detected */ | |
| 8e4641b3 PB |
94 | #define SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_SHFT 1 |
| 95 | #define SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_MASK \ | |
| 96 | __IA64_UL_CONST(0x0000000000000002) | |
| 1da177e4 LT |
97 | |
| 98 | /* SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT */ | |
| 99 | /* Description: Count of currently pending PIO writes */ | |
| 8e4641b3 PB |
100 | #define SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_SHFT 56 |
| 101 | #define SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK \ | |
| 102 | __IA64_UL_CONST(0x3f00000000000000) | |
| 1da177e4 LT |
103 | |
| 104 | /* ==================================================================== */ | |
| 105 | /* Register "SH_PIO_WRITE_STATUS_0_ALIAS" */ | |
| 106 | /* ==================================================================== */ | |
| 8e4641b3 PB |
107 | #define SH1_PIO_WRITE_STATUS_0_ALIAS __IA64_UL_CONST(0x0000000120070208) |
| 108 | #define SH2_PIO_WRITE_STATUS_0_ALIAS __IA64_UL_CONST(0x0000000020070208) | |
| 1da177e4 LT |
109 | |
| 110 | /* ==================================================================== */ | |
| 111 | /* Register "SH_EVENT_OCCURRED" */ | |
| 112 | /* SHub Interrupt Event Occurred */ | |
| 113 | /* ==================================================================== */ | |
| 114 | /* SH_EVENT_OCCURRED_UART_INT */ | |
| 115 | /* Description: Pending Junk Bus UART Interrupt */ | |
| 8e4641b3 PB |
116 | #define SH_EVENT_OCCURRED_UART_INT_SHFT 20 |
| 117 | #define SH_EVENT_OCCURRED_UART_INT_MASK __IA64_UL_CONST(0x0000000000100000) | |
| 1da177e4 LT |
118 | |
| 119 | /* SH_EVENT_OCCURRED_IPI_INT */ | |
| 120 | /* Description: Pending IPI Interrupt */ | |
| 8e4641b3 PB |
121 | #define SH_EVENT_OCCURRED_IPI_INT_SHFT 28 |
| 122 | #define SH_EVENT_OCCURRED_IPI_INT_MASK __IA64_UL_CONST(0x0000000010000000) | |
| 1da177e4 LT |
123 | |
| 124 | /* SH_EVENT_OCCURRED_II_INT0 */ | |
| 125 | /* Description: Pending II 0 Interrupt */ | |
| 8e4641b3 PB |
126 | #define SH_EVENT_OCCURRED_II_INT0_SHFT 29 |
| 127 | #define SH_EVENT_OCCURRED_II_INT0_MASK __IA64_UL_CONST(0x0000000020000000) | |
| 1da177e4 LT |
128 | |
| 129 | /* SH_EVENT_OCCURRED_II_INT1 */ | |
| 130 | /* Description: Pending II 1 Interrupt */ | |
| 8e4641b3 PB |
131 | #define SH_EVENT_OCCURRED_II_INT1_SHFT 30 |
| 132 | #define SH_EVENT_OCCURRED_II_INT1_MASK __IA64_UL_CONST(0x0000000040000000) | |
| 1da177e4 | 133 | |
| be539c73 CN |
134 | /* SH2_EVENT_OCCURRED_EXTIO_INT2 */ |
| 135 | /* Description: Pending SHUB 2 EXT IO INT2 */ | |
| 8e4641b3 PB |
136 | #define SH2_EVENT_OCCURRED_EXTIO_INT2_SHFT 33 |
| 137 | #define SH2_EVENT_OCCURRED_EXTIO_INT2_MASK __IA64_UL_CONST(0x0000000200000000) | |
| be539c73 CN |
138 | |
| 139 | /* SH2_EVENT_OCCURRED_EXTIO_INT3 */ | |
| 140 | /* Description: Pending SHUB 2 EXT IO INT3 */ | |
| 8e4641b3 PB |
141 | #define SH2_EVENT_OCCURRED_EXTIO_INT3_SHFT 34 |
| 142 | #define SH2_EVENT_OCCURRED_EXTIO_INT3_MASK __IA64_UL_CONST(0x0000000400000000) | |
| be539c73 CN |
143 | |
| 144 | #define SH_ALL_INT_MASK \ | |
| 145 | (SH_EVENT_OCCURRED_UART_INT_MASK | SH_EVENT_OCCURRED_IPI_INT_MASK | \ | |
| 146 | SH_EVENT_OCCURRED_II_INT0_MASK | SH_EVENT_OCCURRED_II_INT1_MASK | \ | |
| 147 | SH_EVENT_OCCURRED_II_INT1_MASK | SH2_EVENT_OCCURRED_EXTIO_INT2_MASK | \ | |
| 148 | SH2_EVENT_OCCURRED_EXTIO_INT3_MASK) | |
| 149 | ||
| 150 | ||
| 1da177e4 LT |
151 | /* ==================================================================== */ |
| 152 | /* LEDS */ | |
| 153 | /* ==================================================================== */ | |
| 8e4641b3 PB |
154 | #define SH1_REAL_JUNK_BUS_LED0 0x7fed00000UL |
| 155 | #define SH1_REAL_JUNK_BUS_LED1 0x7fed10000UL | |
| 156 | #define SH1_REAL_JUNK_BUS_LED2 0x7fed20000UL | |
| 157 | #define SH1_REAL_JUNK_BUS_LED3 0x7fed30000UL | |
| 1da177e4 | 158 | |
| 8e4641b3 PB |
159 | #define SH2_REAL_JUNK_BUS_LED0 0xf0000000UL |
| 160 | #define SH2_REAL_JUNK_BUS_LED1 0xf0010000UL | |
| 161 | #define SH2_REAL_JUNK_BUS_LED2 0xf0020000UL | |
| 162 | #define SH2_REAL_JUNK_BUS_LED3 0xf0030000UL | |
| 1da177e4 LT |
163 | |
| 164 | /* ==================================================================== */ | |
| 165 | /* Register "SH1_PTC_0" */ | |
| 166 | /* Puge Translation Cache Message Configuration Information */ | |
| 167 | /* ==================================================================== */ | |
| 8e4641b3 | 168 | #define SH1_PTC_0 __IA64_UL_CONST(0x00000001101a0000) |
| 1da177e4 LT |
169 | |
| 170 | /* SH1_PTC_0_A */ | |
| 171 | /* Description: Type */ | |
| 8e4641b3 | 172 | #define SH1_PTC_0_A_SHFT 0 |
| 1da177e4 LT |
173 | |
| 174 | /* SH1_PTC_0_PS */ | |
| 175 | /* Description: Page Size */ | |
| 8e4641b3 | 176 | #define SH1_PTC_0_PS_SHFT 2 |
| 1da177e4 LT |
177 | |
| 178 | /* SH1_PTC_0_RID */ | |
| 179 | /* Description: Region ID */ | |
| 8e4641b3 | 180 | #define SH1_PTC_0_RID_SHFT 8 |
| 1da177e4 LT |
181 | |
| 182 | /* SH1_PTC_0_START */ | |
| 183 | /* Description: Start */ | |
| 8e4641b3 | 184 | #define SH1_PTC_0_START_SHFT 63 |
| 1da177e4 LT |
185 | |
| 186 | /* ==================================================================== */ | |
| 187 | /* Register "SH1_PTC_1" */ | |
| 188 | /* Puge Translation Cache Message Configuration Information */ | |
| 189 | /* ==================================================================== */ | |
| 8e4641b3 | 190 | #define SH1_PTC_1 __IA64_UL_CONST(0x00000001101a0080) |
| 1da177e4 LT |
191 | |
| 192 | /* SH1_PTC_1_START */ | |
| 193 | /* Description: PTC_1 Start */ | |
| 8e4641b3 | 194 | #define SH1_PTC_1_START_SHFT 63 |
| 1da177e4 LT |
195 | |
| 196 | /* ==================================================================== */ | |
| 197 | /* Register "SH2_PTC" */ | |
| 198 | /* Puge Translation Cache Message Configuration Information */ | |
| 199 | /* ==================================================================== */ | |
| 8e4641b3 | 200 | #define SH2_PTC __IA64_UL_CONST(0x0000000170000000) |
| 1da177e4 LT |
201 | |
| 202 | /* SH2_PTC_A */ | |
| 203 | /* Description: Type */ | |
| 8e4641b3 | 204 | #define SH2_PTC_A_SHFT 0 |
| 1da177e4 LT |
205 | |
| 206 | /* SH2_PTC_PS */ | |
| 207 | /* Description: Page Size */ | |
| 8e4641b3 | 208 | #define SH2_PTC_PS_SHFT 2 |
| 1da177e4 LT |
209 | |
| 210 | /* SH2_PTC_RID */ | |
| 211 | /* Description: Region ID */ | |
| 8e4641b3 | 212 | #define SH2_PTC_RID_SHFT 4 |
| 1da177e4 LT |
213 | |
| 214 | /* SH2_PTC_START */ | |
| 215 | /* Description: Start */ | |
| 8e4641b3 | 216 | #define SH2_PTC_START_SHFT 63 |
| 1da177e4 LT |
217 | |
| 218 | /* SH2_PTC_ADDR_RID */ | |
| 219 | /* Description: Region ID */ | |
| 8e4641b3 PB |
220 | #define SH2_PTC_ADDR_SHFT 4 |
| 221 | #define SH2_PTC_ADDR_MASK __IA64_UL_CONST(0x1ffffffffffff000) | |
| 1da177e4 LT |
222 | |
| 223 | /* ==================================================================== */ | |
| 224 | /* Register "SH_RTC1_INT_CONFIG" */ | |
| 225 | /* SHub RTC 1 Interrupt Config Registers */ | |
| 226 | /* ==================================================================== */ | |
| 227 | ||
| 8e4641b3 PB |
228 | #define SH1_RTC1_INT_CONFIG __IA64_UL_CONST(0x0000000110001480) |
| 229 | #define SH2_RTC1_INT_CONFIG __IA64_UL_CONST(0x0000000010001480) | |
| 230 | #define SH_RTC1_INT_CONFIG_MASK __IA64_UL_CONST(0x0ff3ffffffefffff) | |
| 231 | #define SH_RTC1_INT_CONFIG_INIT __IA64_UL_CONST(0x0000000000000000) | |
| 1da177e4 LT |
232 | |
| 233 | /* SH_RTC1_INT_CONFIG_TYPE */ | |
| 234 | /* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ | |
| 8e4641b3 PB |
235 | #define SH_RTC1_INT_CONFIG_TYPE_SHFT 0 |
| 236 | #define SH_RTC1_INT_CONFIG_TYPE_MASK __IA64_UL_CONST(0x0000000000000007) | |
| 1da177e4 LT |
237 | |
| 238 | /* SH_RTC1_INT_CONFIG_AGT */ | |
| 239 | /* Description: Agent, must be 0 for SHub */ | |
| 8e4641b3 PB |
240 | #define SH_RTC1_INT_CONFIG_AGT_SHFT 3 |
| 241 | #define SH_RTC1_INT_CONFIG_AGT_MASK __IA64_UL_CONST(0x0000000000000008) | |
| 1da177e4 LT |
242 | |
| 243 | /* SH_RTC1_INT_CONFIG_PID */ | |
| 244 | /* Description: Processor ID, same setting as on targeted McKinley */ | |
| 8e4641b3 PB |
245 | #define SH_RTC1_INT_CONFIG_PID_SHFT 4 |
| 246 | #define SH_RTC1_INT_CONFIG_PID_MASK __IA64_UL_CONST(0x00000000000ffff0) | |
| 1da177e4 LT |
247 | |
| 248 | /* SH_RTC1_INT_CONFIG_BASE */ | |
| 249 | /* Description: Optional interrupt vector area, 2MB aligned */ | |
| 8e4641b3 PB |
250 | #define SH_RTC1_INT_CONFIG_BASE_SHFT 21 |
| 251 | #define SH_RTC1_INT_CONFIG_BASE_MASK __IA64_UL_CONST(0x0003ffffffe00000) | |
| 1da177e4 LT |
252 | |
| 253 | /* SH_RTC1_INT_CONFIG_IDX */ | |
| 254 | /* Description: Targeted McKinley interrupt vector */ | |
| 8e4641b3 PB |
255 | #define SH_RTC1_INT_CONFIG_IDX_SHFT 52 |
| 256 | #define SH_RTC1_INT_CONFIG_IDX_MASK __IA64_UL_CONST(0x0ff0000000000000) | |
| 1da177e4 LT |
257 | |
| 258 | /* ==================================================================== */ | |
| 259 | /* Register "SH_RTC1_INT_ENABLE" */ | |
| 260 | /* SHub RTC 1 Interrupt Enable Registers */ | |
| 261 | /* ==================================================================== */ | |
| 262 | ||
| 8e4641b3 PB |
263 | #define SH1_RTC1_INT_ENABLE __IA64_UL_CONST(0x0000000110001500) |
| 264 | #define SH2_RTC1_INT_ENABLE __IA64_UL_CONST(0x0000000010001500) | |
| 265 | #define SH_RTC1_INT_ENABLE_MASK __IA64_UL_CONST(0x0000000000000001) | |
| 266 | #define SH_RTC1_INT_ENABLE_INIT __IA64_UL_CONST(0x0000000000000000) | |
| 1da177e4 LT |
267 | |
| 268 | /* SH_RTC1_INT_ENABLE_RTC1_ENABLE */ | |
| 269 | /* Description: Enable RTC 1 Interrupt */ | |
| 8e4641b3 PB |
270 | #define SH_RTC1_INT_ENABLE_RTC1_ENABLE_SHFT 0 |
| 271 | #define SH_RTC1_INT_ENABLE_RTC1_ENABLE_MASK \ | |
| 272 | __IA64_UL_CONST(0x0000000000000001) | |
| 1da177e4 LT |
273 | |
| 274 | /* ==================================================================== */ | |
| 275 | /* Register "SH_RTC2_INT_CONFIG" */ | |
| 276 | /* SHub RTC 2 Interrupt Config Registers */ | |
| 277 | /* ==================================================================== */ | |
| 278 | ||
| 8e4641b3 PB |
279 | #define SH1_RTC2_INT_CONFIG __IA64_UL_CONST(0x0000000110001580) |
| 280 | #define SH2_RTC2_INT_CONFIG __IA64_UL_CONST(0x0000000010001580) | |
| 281 | #define SH_RTC2_INT_CONFIG_MASK __IA64_UL_CONST(0x0ff3ffffffefffff) | |
| 282 | #define SH_RTC2_INT_CONFIG_INIT __IA64_UL_CONST(0x0000000000000000) | |
| 1da177e4 LT |
283 | |
| 284 | /* SH_RTC2_INT_CONFIG_TYPE */ | |
| 285 | /* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ | |
| 8e4641b3 PB |
286 | #define SH_RTC2_INT_CONFIG_TYPE_SHFT 0 |
| 287 | #define SH_RTC2_INT_CONFIG_TYPE_MASK __IA64_UL_CONST(0x0000000000000007) | |
| 1da177e4 LT |
288 | |
| 289 | /* SH_RTC2_INT_CONFIG_AGT */ | |
| 290 | /* Description: Agent, must be 0 for SHub */ | |
| 8e4641b3 PB |
291 | #define SH_RTC2_INT_CONFIG_AGT_SHFT 3 |
| 292 | #define SH_RTC2_INT_CONFIG_AGT_MASK __IA64_UL_CONST(0x0000000000000008) | |
| 1da177e4 LT |
293 | |
| 294 | /* SH_RTC2_INT_CONFIG_PID */ | |
| 295 | /* Description: Processor ID, same setting as on targeted McKinley */ | |
| 8e4641b3 PB |
296 | #define SH_RTC2_INT_CONFIG_PID_SHFT 4 |
| 297 | #define SH_RTC2_INT_CONFIG_PID_MASK __IA64_UL_CONST(0x00000000000ffff0) | |
| 1da177e4 LT |
298 | |
| 299 | /* SH_RTC2_INT_CONFIG_BASE */ | |
| 300 | /* Description: Optional interrupt vector area, 2MB aligned */ | |
| 8e4641b3 PB |
301 | #define SH_RTC2_INT_CONFIG_BASE_SHFT 21 |
| 302 | #define SH_RTC2_INT_CONFIG_BASE_MASK __IA64_UL_CONST(0x0003ffffffe00000) | |
| 1da177e4 LT |
303 | |
| 304 | /* SH_RTC2_INT_CONFIG_IDX */ | |
| 305 | /* Description: Targeted McKinley interrupt vector */ | |
| 8e4641b3 PB |
306 | #define SH_RTC2_INT_CONFIG_IDX_SHFT 52 |
| 307 | #define SH_RTC2_INT_CONFIG_IDX_MASK __IA64_UL_CONST(0x0ff0000000000000) | |
| 1da177e4 LT |
308 | |
| 309 | /* ==================================================================== */ | |
| 310 | /* Register "SH_RTC2_INT_ENABLE" */ | |
| 311 | /* SHub RTC 2 Interrupt Enable Registers */ | |
| 312 | /* ==================================================================== */ | |
| 313 | ||
| 8e4641b3 PB |
314 | #define SH1_RTC2_INT_ENABLE __IA64_UL_CONST(0x0000000110001600) |
| 315 | #define SH2_RTC2_INT_ENABLE __IA64_UL_CONST(0x0000000010001600) | |
| 316 | #define SH_RTC2_INT_ENABLE_MASK __IA64_UL_CONST(0x0000000000000001) | |
| 317 | #define SH_RTC2_INT_ENABLE_INIT __IA64_UL_CONST(0x0000000000000000) | |
| 1da177e4 LT |
318 | |
| 319 | /* SH_RTC2_INT_ENABLE_RTC2_ENABLE */ | |
| 320 | /* Description: Enable RTC 2 Interrupt */ | |
| 8e4641b3 PB |
321 | #define SH_RTC2_INT_ENABLE_RTC2_ENABLE_SHFT 0 |
| 322 | #define SH_RTC2_INT_ENABLE_RTC2_ENABLE_MASK \ | |
| 323 | __IA64_UL_CONST(0x0000000000000001) | |
| 1da177e4 LT |
324 | |
| 325 | /* ==================================================================== */ | |
| 326 | /* Register "SH_RTC3_INT_CONFIG" */ | |
| 327 | /* SHub RTC 3 Interrupt Config Registers */ | |
| 328 | /* ==================================================================== */ | |
| 329 | ||
| 8e4641b3 PB |
330 | #define SH1_RTC3_INT_CONFIG __IA64_UL_CONST(0x0000000110001680) |
| 331 | #define SH2_RTC3_INT_CONFIG __IA64_UL_CONST(0x0000000010001680) | |
| 332 | #define SH_RTC3_INT_CONFIG_MASK __IA64_UL_CONST(0x0ff3ffffffefffff) | |
| 333 | #define SH_RTC3_INT_CONFIG_INIT __IA64_UL_CONST(0x0000000000000000) | |
| 1da177e4 LT |
334 | |
| 335 | /* SH_RTC3_INT_CONFIG_TYPE */ | |
| 336 | /* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ | |
| 8e4641b3 PB |
337 | #define SH_RTC3_INT_CONFIG_TYPE_SHFT 0 |
| 338 | #define SH_RTC3_INT_CONFIG_TYPE_MASK __IA64_UL_CONST(0x0000000000000007) | |
| 1da177e4 LT |
339 | |
| 340 | /* SH_RTC3_INT_CONFIG_AGT */ | |
| 341 | /* Description: Agent, must be 0 for SHub */ | |
| 8e4641b3 PB |
342 | #define SH_RTC3_INT_CONFIG_AGT_SHFT 3 |
| 343 | #define SH_RTC3_INT_CONFIG_AGT_MASK __IA64_UL_CONST(0x0000000000000008) | |
| 1da177e4 LT |
344 | |
| 345 | /* SH_RTC3_INT_CONFIG_PID */ | |
| 346 | /* Description: Processor ID, same setting as on targeted McKinley */ | |
| 8e4641b3 PB |
347 | #define SH_RTC3_INT_CONFIG_PID_SHFT 4 |
| 348 | #define SH_RTC3_INT_CONFIG_PID_MASK __IA64_UL_CONST(0x00000000000ffff0) | |
| 1da177e4 LT |
349 | |
| 350 | /* SH_RTC3_INT_CONFIG_BASE */ | |
| 351 | /* Description: Optional interrupt vector area, 2MB aligned */ | |
| 8e4641b3 PB |
352 | #define SH_RTC3_INT_CONFIG_BASE_SHFT 21 |
| 353 | #define SH_RTC3_INT_CONFIG_BASE_MASK __IA64_UL_CONST(0x0003ffffffe00000) | |
| 1da177e4 LT |
354 | |
| 355 | /* SH_RTC3_INT_CONFIG_IDX */ | |
| 356 | /* Description: Targeted McKinley interrupt vector */ | |
| 8e4641b3 PB |
357 | #define SH_RTC3_INT_CONFIG_IDX_SHFT 52 |
| 358 | #define SH_RTC3_INT_CONFIG_IDX_MASK __IA64_UL_CONST(0x0ff0000000000000) | |
| 1da177e4 LT |
359 | |
| 360 | /* ==================================================================== */ | |
| 361 | /* Register "SH_RTC3_INT_ENABLE" */ | |
| 362 | /* SHub RTC 3 Interrupt Enable Registers */ | |
| 363 | /* ==================================================================== */ | |
| 364 | ||
| 8e4641b3 PB |
365 | #define SH1_RTC3_INT_ENABLE __IA64_UL_CONST(0x0000000110001700) |
| 366 | #define SH2_RTC3_INT_ENABLE __IA64_UL_CONST(0x0000000010001700) | |
| 367 | #define SH_RTC3_INT_ENABLE_MASK __IA64_UL_CONST(0x0000000000000001) | |
| 368 | #define SH_RTC3_INT_ENABLE_INIT __IA64_UL_CONST(0x0000000000000000) | |
| 1da177e4 LT |
369 | |
| 370 | /* SH_RTC3_INT_ENABLE_RTC3_ENABLE */ | |
| 371 | /* Description: Enable RTC 3 Interrupt */ | |
| 8e4641b3 PB |
372 | #define SH_RTC3_INT_ENABLE_RTC3_ENABLE_SHFT 0 |
| 373 | #define SH_RTC3_INT_ENABLE_RTC3_ENABLE_MASK \ | |
| 374 | __IA64_UL_CONST(0x0000000000000001) | |
| 1da177e4 LT |
375 | |
| 376 | /* SH_EVENT_OCCURRED_RTC1_INT */ | |
| 377 | /* Description: Pending RTC 1 Interrupt */ | |
| 8e4641b3 PB |
378 | #define SH_EVENT_OCCURRED_RTC1_INT_SHFT 24 |
| 379 | #define SH_EVENT_OCCURRED_RTC1_INT_MASK __IA64_UL_CONST(0x0000000001000000) | |
| 1da177e4 LT |
380 | |
| 381 | /* SH_EVENT_OCCURRED_RTC2_INT */ | |
| 382 | /* Description: Pending RTC 2 Interrupt */ | |
| 8e4641b3 PB |
383 | #define SH_EVENT_OCCURRED_RTC2_INT_SHFT 25 |
| 384 | #define SH_EVENT_OCCURRED_RTC2_INT_MASK __IA64_UL_CONST(0x0000000002000000) | |
| 1da177e4 LT |
385 | |
| 386 | /* SH_EVENT_OCCURRED_RTC3_INT */ | |
| 387 | /* Description: Pending RTC 3 Interrupt */ | |
| 8e4641b3 PB |
388 | #define SH_EVENT_OCCURRED_RTC3_INT_SHFT 26 |
| 389 | #define SH_EVENT_OCCURRED_RTC3_INT_MASK __IA64_UL_CONST(0x0000000004000000) | |
| 1da177e4 | 390 | |
| 21e37283 DN |
391 | /* ==================================================================== */ |
| 392 | /* Register "SH_IPI_ACCESS" */ | |
| 393 | /* CPU interrupt Access Permission Bits */ | |
| 394 | /* ==================================================================== */ | |
| 395 | ||
| 8e4641b3 PB |
396 | #define SH1_IPI_ACCESS __IA64_UL_CONST(0x0000000110060480) |
| 397 | #define SH2_IPI_ACCESS0 __IA64_UL_CONST(0x0000000010060c00) | |
| 398 | #define SH2_IPI_ACCESS1 __IA64_UL_CONST(0x0000000010060c80) | |
| 399 | #define SH2_IPI_ACCESS2 __IA64_UL_CONST(0x0000000010060d00) | |
| 400 | #define SH2_IPI_ACCESS3 __IA64_UL_CONST(0x0000000010060d80) | |
| 21e37283 | 401 | |
| 1da177e4 LT |
402 | /* ==================================================================== */ |
| 403 | /* Register "SH_INT_CMPB" */ | |
| 404 | /* RTC Compare Value for Processor B */ | |
| 405 | /* ==================================================================== */ | |
| 406 | ||
| 8e4641b3 PB |
407 | #define SH1_INT_CMPB __IA64_UL_CONST(0x00000001101b0080) |
| 408 | #define SH2_INT_CMPB __IA64_UL_CONST(0x00000000101b0080) | |
| 409 | #define SH_INT_CMPB_MASK __IA64_UL_CONST(0x007fffffffffffff) | |
| 410 | #define SH_INT_CMPB_INIT __IA64_UL_CONST(0x0000000000000000) | |
| 1da177e4 LT |
411 | |
| 412 | /* SH_INT_CMPB_REAL_TIME_CMPB */ | |
| 413 | /* Description: Real Time Clock Compare */ | |
| 8e4641b3 PB |
414 | #define SH_INT_CMPB_REAL_TIME_CMPB_SHFT 0 |
| 415 | #define SH_INT_CMPB_REAL_TIME_CMPB_MASK __IA64_UL_CONST(0x007fffffffffffff) | |
| 1da177e4 LT |
416 | |
| 417 | /* ==================================================================== */ | |
| 418 | /* Register "SH_INT_CMPC" */ | |
| 419 | /* RTC Compare Value for Processor C */ | |
| 420 | /* ==================================================================== */ | |
| 421 | ||
| 8e4641b3 PB |
422 | #define SH1_INT_CMPC __IA64_UL_CONST(0x00000001101b0100) |
| 423 | #define SH2_INT_CMPC __IA64_UL_CONST(0x00000000101b0100) | |
| 424 | #define SH_INT_CMPC_MASK __IA64_UL_CONST(0x007fffffffffffff) | |
| 425 | #define SH_INT_CMPC_INIT __IA64_UL_CONST(0x0000000000000000) | |
| 1da177e4 LT |
426 | |
| 427 | /* SH_INT_CMPC_REAL_TIME_CMPC */ | |
| 428 | /* Description: Real Time Clock Compare */ | |
| 8e4641b3 PB |
429 | #define SH_INT_CMPC_REAL_TIME_CMPC_SHFT 0 |
| 430 | #define SH_INT_CMPC_REAL_TIME_CMPC_MASK __IA64_UL_CONST(0x007fffffffffffff) | |
| 1da177e4 LT |
431 | |
| 432 | /* ==================================================================== */ | |
| 433 | /* Register "SH_INT_CMPD" */ | |
| 434 | /* RTC Compare Value for Processor D */ | |
| 435 | /* ==================================================================== */ | |
| 436 | ||
| 8e4641b3 PB |
437 | #define SH1_INT_CMPD __IA64_UL_CONST(0x00000001101b0180) |
| 438 | #define SH2_INT_CMPD __IA64_UL_CONST(0x00000000101b0180) | |
| 439 | #define SH_INT_CMPD_MASK __IA64_UL_CONST(0x007fffffffffffff) | |
| 440 | #define SH_INT_CMPD_INIT __IA64_UL_CONST(0x0000000000000000) | |
| 1da177e4 LT |
441 | |
| 442 | /* SH_INT_CMPD_REAL_TIME_CMPD */ | |
| 443 | /* Description: Real Time Clock Compare */ | |
| 8e4641b3 PB |
444 | #define SH_INT_CMPD_REAL_TIME_CMPD_SHFT 0 |
| 445 | #define SH_INT_CMPD_REAL_TIME_CMPD_MASK __IA64_UL_CONST(0x007fffffffffffff) | |
| 1da177e4 | 446 | |
| 21e37283 DN |
447 | /* ==================================================================== */ |
| 448 | /* Register "SH_MD_DQLP_MMR_DIR_PRIVEC0" */ | |
| 449 | /* privilege vector for acc=0 */ | |
| 450 | /* ==================================================================== */ | |
| 8e4641b3 | 451 | #define SH1_MD_DQLP_MMR_DIR_PRIVEC0 __IA64_UL_CONST(0x0000000100030300) |
| 21e37283 DN |
452 | |
| 453 | /* ==================================================================== */ | |
| 454 | /* Register "SH_MD_DQRP_MMR_DIR_PRIVEC0" */ | |
| 455 | /* privilege vector for acc=0 */ | |
| 456 | /* ==================================================================== */ | |
| 8e4641b3 | 457 | #define SH1_MD_DQRP_MMR_DIR_PRIVEC0 __IA64_UL_CONST(0x0000000100050300) |
| 1da177e4 LT |
458 | |
| 459 | /* ==================================================================== */ | |
| 460 | /* Some MMRs are functionally identical (or close enough) on both SHUB1 */ | |
| 461 | /* and SHUB2 that it makes sense to define a geberic name for the MMR. */ | |
| 25985edc | 462 | /* It is acceptable to use (for example) SH_IPI_INT to reference the */ |
| 1da177e4 LT |
463 | /* the IPI MMR. The value of SH_IPI_INT is determined at runtime based */ |
| 464 | /* on the type of the SHUB. Do not use these #defines in performance */ | |
| 465 | /* critical code or loops - there is a small performance penalty. */ | |
| 466 | /* ==================================================================== */ | |
| 467 | #define shubmmr(a,b) (is_shub2() ? a##2_##b : a##1_##b) | |
| 468 | ||
| 469 | #define SH_REAL_JUNK_BUS_LED0 shubmmr(SH, REAL_JUNK_BUS_LED0) | |
| 470 | #define SH_IPI_INT shubmmr(SH, IPI_INT) | |
| 471 | #define SH_EVENT_OCCURRED shubmmr(SH, EVENT_OCCURRED) | |
| 472 | #define SH_EVENT_OCCURRED_ALIAS shubmmr(SH, EVENT_OCCURRED_ALIAS) | |
| 473 | #define SH_RTC shubmmr(SH, RTC) | |
| 474 | #define SH_RTC1_INT_CONFIG shubmmr(SH, RTC1_INT_CONFIG) | |
| 475 | #define SH_RTC1_INT_ENABLE shubmmr(SH, RTC1_INT_ENABLE) | |
| 476 | #define SH_RTC2_INT_CONFIG shubmmr(SH, RTC2_INT_CONFIG) | |
| 477 | #define SH_RTC2_INT_ENABLE shubmmr(SH, RTC2_INT_ENABLE) | |
| 478 | #define SH_RTC3_INT_CONFIG shubmmr(SH, RTC3_INT_CONFIG) | |
| 479 | #define SH_RTC3_INT_ENABLE shubmmr(SH, RTC3_INT_ENABLE) | |
| 480 | #define SH_INT_CMPB shubmmr(SH, INT_CMPB) | |
| 481 | #define SH_INT_CMPC shubmmr(SH, INT_CMPC) | |
| 482 | #define SH_INT_CMPD shubmmr(SH, INT_CMPD) | |
| 483 | ||
| 95ff439a RA |
484 | /* ========================================================================== */ |
| 485 | /* Register "SH2_BT_ENG_CSR_0" */ | |
| 486 | /* Engine 0 Control and Status Register */ | |
| 487 | /* ========================================================================== */ | |
| 488 | ||
| 8e4641b3 PB |
489 | #define SH2_BT_ENG_CSR_0 __IA64_UL_CONST(0x0000000030040000) |
| 490 | #define SH2_BT_ENG_SRC_ADDR_0 __IA64_UL_CONST(0x0000000030040080) | |
| 491 | #define SH2_BT_ENG_DEST_ADDR_0 __IA64_UL_CONST(0x0000000030040100) | |
| 492 | #define SH2_BT_ENG_NOTIF_ADDR_0 __IA64_UL_CONST(0x0000000030040180) | |
| 95ff439a RA |
493 | |
| 494 | /* ========================================================================== */ | |
| 495 | /* BTE interfaces 1-3 */ | |
| 496 | /* ========================================================================== */ | |
| 497 | ||
| 8e4641b3 PB |
498 | #define SH2_BT_ENG_CSR_1 __IA64_UL_CONST(0x0000000030050000) |
| 499 | #define SH2_BT_ENG_CSR_2 __IA64_UL_CONST(0x0000000030060000) | |
| 500 | #define SH2_BT_ENG_CSR_3 __IA64_UL_CONST(0x0000000030070000) | |
| 95ff439a | 501 | |
| 1da177e4 | 502 | #endif /* _ASM_IA64_SN_SHUB_MMR_H */ |