[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / i386 / oprofile / nmi_int.c

/**
 * @file nmi_int.c
 *
 * @remark Copyright 2002 OProfile authors
 * @remark Read the file COPYING
 *
 * @author John Levon <levon@movementarian.org>
 */

#include <linux/init.h>
#include <linux/notifier.h>
#include <linux/smp.h>
#include <linux/oprofile.h>
#include <linux/sysdev.h>
#include <linux/slab.h>
#include <linux/moduleparam.h>
#include <linux/kdebug.h>
#include <asm/nmi.h>
#include <asm/msr.h>
#include <asm/apic.h>
 
#include "op_counter.h"
#include "op_x86_model.h"

static struct op_x86_model_spec const * model;
static struct op_msrs cpu_msrs[NR_CPUS];
static unsigned long saved_lvtpc[NR_CPUS];

static int nmi_start(void);
static void nmi_stop(void);

/* 0 == registered but off, 1 == registered and on */
static int nmi_enabled = 0;

#ifdef CONFIG_PM

static int nmi_suspend(struct sys_device *dev, pm_message_t state)
{
	if (nmi_enabled == 1)
		nmi_stop();
	return 0;
}


static int nmi_resume(struct sys_device *dev)
{
	if (nmi_enabled == 1)
		nmi_start();
	return 0;
}


static struct sysdev_class oprofile_sysclass = {
	set_kset_name("oprofile"),
	.resume		= nmi_resume,
	.suspend	= nmi_suspend,
};


static struct sys_device device_oprofile = {
	.id	= 0,
	.cls	= &oprofile_sysclass,
};


static int __init init_sysfs(void)
{
	int error;
	if (!(error = sysdev_class_register(&oprofile_sysclass)))
		error = sysdev_register(&device_oprofile);
	return error;
}


static void exit_sysfs(void)
{
	sysdev_unregister(&device_oprofile);
	sysdev_class_unregister(&oprofile_sysclass);
}

#else
#define init_sysfs() do { } while (0)
#define exit_sysfs() do { } while (0)
#endif /* CONFIG_PM */

static int profile_exceptions_notify(struct notifier_block *self,
				     unsigned long val, void *data)
{
	struct die_args *args = (struct die_args *)data;
	int ret = NOTIFY_DONE;
	int cpu = smp_processor_id();

	switch(val) {
	case DIE_NMI:
		if (model->check_ctrs(args->regs, &cpu_msrs[cpu]))
			ret = NOTIFY_STOP;
		break;
	default:
		break;
	}
	return ret;
}

static void nmi_cpu_save_registers(struct op_msrs * msrs)
{
	unsigned int const nr_ctrs = model->num_counters;
	unsigned int const nr_ctrls = model->num_controls; 
	struct op_msr * counters = msrs->counters;
	struct op_msr * controls = msrs->controls;
	unsigned int i;

	for (i = 0; i < nr_ctrs; ++i) {
		if (counters[i].addr){
			rdmsr(counters[i].addr,
				counters[i].saved.low,
				counters[i].saved.high);
		}
	}
 
	for (i = 0; i < nr_ctrls; ++i) {
		if (controls[i].addr){
			rdmsr(controls[i].addr,
				controls[i].saved.low,
				controls[i].saved.high);
		}
	}
}


static void nmi_save_registers(void * dummy)
{
	int cpu = smp_processor_id();
	struct op_msrs * msrs = &cpu_msrs[cpu];
	model->fill_in_addresses(msrs);
	nmi_cpu_save_registers(msrs);
}


static void free_msrs(void)
{
	int i;
	for_each_possible_cpu(i) {
		kfree(cpu_msrs[i].counters);
		cpu_msrs[i].counters = NULL;
		kfree(cpu_msrs[i].controls);
		cpu_msrs[i].controls = NULL;
	}
}


static int allocate_msrs(void)
{
	int success = 1;
	size_t controls_size = sizeof(struct op_msr) * model->num_controls;
	size_t counters_size = sizeof(struct op_msr) * model->num_counters;

	int i;
	for_each_online_cpu(i) {
		cpu_msrs[i].counters = kmalloc(counters_size, GFP_KERNEL);
		if (!cpu_msrs[i].counters) {
			success = 0;
			break;
		}
		cpu_msrs[i].controls = kmalloc(controls_size, GFP_KERNEL);
		if (!cpu_msrs[i].controls) {
			success = 0;
			break;
		}
	}

	if (!success)
		free_msrs();

	return success;
}


static void nmi_cpu_setup(void * dummy)
{
	int cpu = smp_processor_id();
	struct op_msrs * msrs = &cpu_msrs[cpu];
	spin_lock(&oprofilefs_lock);
	model->setup_ctrs(msrs);
	spin_unlock(&oprofilefs_lock);
	saved_lvtpc[cpu] = apic_read(APIC_LVTPC);
	apic_write(APIC_LVTPC, APIC_DM_NMI);
}

static struct notifier_block profile_exceptions_nb = {
	.notifier_call = profile_exceptions_notify,
	.next = NULL,
	.priority = 0
};

static int nmi_setup(void)
{
	int err=0;

	if (!allocate_msrs())
		return -ENOMEM;

	if ((err = register_die_notifier(&profile_exceptions_nb))){
		free_msrs();
		return err;
	}

	/* We need to serialize save and setup for HT because the subset
	 * of msrs are distinct for save and setup operations
	 */
	on_each_cpu(nmi_save_registers, NULL, 0, 1);
	on_each_cpu(nmi_cpu_setup, NULL, 0, 1);
	nmi_enabled = 1;
	return 0;
}


static void nmi_restore_registers(struct op_msrs * msrs)
{
	unsigned int const nr_ctrs = model->num_counters;
	unsigned int const nr_ctrls = model->num_controls; 
	struct op_msr * counters = msrs->counters;
	struct op_msr * controls = msrs->controls;
	unsigned int i;

	for (i = 0; i < nr_ctrls; ++i) {
		if (controls[i].addr){
			wrmsr(controls[i].addr,
				controls[i].saved.low,
				controls[i].saved.high);
		}
	}
 
	for (i = 0; i < nr_ctrs; ++i) {
		if (counters[i].addr){
			wrmsr(counters[i].addr,
				counters[i].saved.low,
				counters[i].saved.high);
		}
	}
}
 

static void nmi_cpu_shutdown(void * dummy)
{
	unsigned int v;
	int cpu = smp_processor_id();
	struct op_msrs * msrs = &cpu_msrs[cpu];
 
	/* restoring APIC_LVTPC can trigger an apic error because the delivery
	 * mode and vector nr combination can be illegal. That's by design: on
	 * power on apic lvt contain a zero vector nr which are legal only for
	 * NMI delivery mode. So inhibit apic err before restoring lvtpc
	 */
	v = apic_read(APIC_LVTERR);
	apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
	apic_write(APIC_LVTPC, saved_lvtpc[cpu]);
	apic_write(APIC_LVTERR, v);
	nmi_restore_registers(msrs);
	model->shutdown(msrs);
}

 
static void nmi_shutdown(void)
{
	nmi_enabled = 0;
	on_each_cpu(nmi_cpu_shutdown, NULL, 0, 1);
	unregister_die_notifier(&profile_exceptions_nb);
	free_msrs();
}

 
static void nmi_cpu_start(void * dummy)
{
	struct op_msrs const * msrs = &cpu_msrs[smp_processor_id()];
	model->start(msrs);
}
 

static int nmi_start(void)
{
	on_each_cpu(nmi_cpu_start, NULL, 0, 1);
	return 0;
}
 
 
static void nmi_cpu_stop(void * dummy)
{
	struct op_msrs const * msrs = &cpu_msrs[smp_processor_id()];
	model->stop(msrs);
}
 
 
static void nmi_stop(void)
{
	on_each_cpu(nmi_cpu_stop, NULL, 0, 1);
}


struct op_counter_config counter_config[OP_MAX_COUNTER];

static int nmi_create_files(struct super_block * sb, struct dentry * root)
{
	unsigned int i;

	for (i = 0; i < model->num_counters; ++i) {
		struct dentry * dir;
		char buf[4];
 
 		/* quick little hack to _not_ expose a counter if it is not
		 * available for use.  This should protect userspace app.
		 * NOTE:  assumes 1:1 mapping here (that counters are organized
		 *        sequentially in their struct assignment).
		 */
		if (unlikely(!avail_to_resrv_perfctr_nmi_bit(i)))
			continue;

		snprintf(buf,  sizeof(buf), "%d", i);
		dir = oprofilefs_mkdir(sb, root, buf);
		oprofilefs_create_ulong(sb, dir, "enabled", &counter_config[i].enabled); 
		oprofilefs_create_ulong(sb, dir, "event", &counter_config[i].event); 
		oprofilefs_create_ulong(sb, dir, "count", &counter_config[i].count); 
		oprofilefs_create_ulong(sb, dir, "unit_mask", &counter_config[i].unit_mask); 
		oprofilefs_create_ulong(sb, dir, "kernel", &counter_config[i].kernel); 
		oprofilefs_create_ulong(sb, dir, "user", &counter_config[i].user); 
	}

	return 0;
}
 
static int p4force;
module_param(p4force, int, 0);
 
static int __init p4_init(char ** cpu_type)
{
	__u8 cpu_model = boot_cpu_data.x86_model;

	if (!p4force && (cpu_model > 6 || cpu_model == 5))
		return 0;

#ifndef CONFIG_SMP
	*cpu_type = "i386/p4";
	model = &op_p4_spec;
	return 1;
#else
	switch (smp_num_siblings) {
		case 1:
			*cpu_type = "i386/p4";
			model = &op_p4_spec;
			return 1;

		case 2:
			*cpu_type = "i386/p4-ht";
			model = &op_p4_ht2_spec;
			return 1;
	}
#endif

	printk(KERN_INFO "oprofile: P4 HyperThreading detected with > 2 threads\n");
	printk(KERN_INFO "oprofile: Reverting to timer mode.\n");
	return 0;
}


static int __init ppro_init(char ** cpu_type)
{
	__u8 cpu_model = boot_cpu_data.x86_model;

	if (cpu_model == 14)
		*cpu_type = "i386/core";
	else if (cpu_model == 15)
		*cpu_type = "i386/core_2";
	else if (cpu_model > 0xd)
		return 0;
	else if (cpu_model == 9) {
		*cpu_type = "i386/p6_mobile";
	} else if (cpu_model > 5) {
		*cpu_type = "i386/piii";
	} else if (cpu_model > 2) {
		*cpu_type = "i386/pii";
	} else {
		*cpu_type = "i386/ppro";
	}

	model = &op_ppro_spec;
	return 1;
}

/* in order to get sysfs right */
static int using_nmi;

int __init op_nmi_init(struct oprofile_operations *ops)
{
	__u8 vendor = boot_cpu_data.x86_vendor;
	__u8 family = boot_cpu_data.x86;
	char *cpu_type;

	if (!cpu_has_apic)
		return -ENODEV;
 
	switch (vendor) {
		case X86_VENDOR_AMD:
			/* Needs to be at least an Athlon (or hammer in 32bit mode) */

			switch (family) {
			default:
				return -ENODEV;
			case 6:
				model = &op_athlon_spec;
				cpu_type = "i386/athlon";
				break;
			case 0xf:
				model = &op_athlon_spec;
				/* Actually it could be i386/hammer too, but give
				   user space an consistent name. */
				cpu_type = "x86-64/hammer";
				break;
			case 0x10:
				model = &op_athlon_spec;
				cpu_type = "x86-64/family10";
				break;
			}
			break;
 
		case X86_VENDOR_INTEL:
			switch (family) {
				/* Pentium IV */
				case 0xf:
					if (!p4_init(&cpu_type))
						return -ENODEV;
					break;

				/* A P6-class processor */
				case 6:
					if (!ppro_init(&cpu_type))
						return -ENODEV;
					break;

				default:
					return -ENODEV;
			}
			break;

		default:
			return -ENODEV;
	}

	init_sysfs();
	using_nmi = 1;
	ops->create_files = nmi_create_files;
	ops->setup = nmi_setup;
	ops->shutdown = nmi_shutdown;
	ops->start = nmi_start;
	ops->stop = nmi_stop;
	ops->cpu_type = cpu_type;
	printk(KERN_INFO "oprofile: using NMI interrupt.\n");
	return 0;
}


void op_nmi_exit(void)
{
	if (using_nmi)
		exit_sysfs();
}
Commit	Line	Data
1da177e4 LT	1	/**
	2	* @file nmi_int.c
	3	*
	4	* @remark Copyright 2002 OProfile authors
	5	* @remark Read the file COPYING
	6	*
	7	* @author John Levon <levon@movementarian.org>
	8	*/
	9
	10	#include <linux/init.h>
	11	#include <linux/notifier.h>
	12	#include <linux/smp.h>
	13	#include <linux/oprofile.h>
	14	#include <linux/sysdev.h>
	15	#include <linux/slab.h>
1cfcea1b	16	#include <linux/moduleparam.h>
1eeb66a1	17	#include <linux/kdebug.h>
1da177e4 LT	18	#include <asm/nmi.h>
	19	#include <asm/msr.h>
	20	#include <asm/apic.h>
	21
	22	#include "op_counter.h"
	23	#include "op_x86_model.h"
2fbe7b25	24
1da177e4 LT	25	static struct op_x86_model_spec const * model;
	26	static struct op_msrs cpu_msrs[NR_CPUS];
	27	static unsigned long saved_lvtpc[NR_CPUS];
2fbe7b25	28
1da177e4 LT	29	static int nmi_start(void);
	30	static void nmi_stop(void);
	31
	32	/* 0 == registered but off, 1 == registered and on */
	33	static int nmi_enabled = 0;
	34
	35	#ifdef CONFIG_PM
	36
438510f6	37	static int nmi_suspend(struct sys_device *dev, pm_message_t state)
1da177e4 LT	38	{
	39	if (nmi_enabled == 1)
	40	nmi_stop();
	41	return 0;
	42	}
	43
	44
	45	static int nmi_resume(struct sys_device *dev)
	46	{
	47	if (nmi_enabled == 1)
	48	nmi_start();
	49	return 0;
	50	}
	51
	52
	53	static struct sysdev_class oprofile_sysclass = {
	54	set_kset_name("oprofile"),
	55	.resume = nmi_resume,
	56	.suspend = nmi_suspend,
	57	};
	58
	59
	60	static struct sys_device device_oprofile = {
	61	.id = 0,
	62	.cls = &oprofile_sysclass,
	63	};
	64
	65
405ae7d3	66	static int __init init_sysfs(void)
1da177e4 LT	67	{
	68	int error;
	69	if (!(error = sysdev_class_register(&oprofile_sysclass)))
	70	error = sysdev_register(&device_oprofile);
	71	return error;
	72	}
	73
	74
405ae7d3	75	static void exit_sysfs(void)
1da177e4 LT	76	{
	77	sysdev_unregister(&device_oprofile);
	78	sysdev_class_unregister(&oprofile_sysclass);
	79	}
	80
	81	#else
405ae7d3 RD	82	#define init_sysfs() do { } while (0)
405ae7d3 RD	83	#define exit_sysfs() do { } while (0)
1da177e4 LT	84	#endif /* CONFIG_PM */
1da177e4 LT	85
c7c19f8e AB	86	static int profile_exceptions_notify(struct notifier_block *self,
c7c19f8e AB	87	unsigned long val, void *data)
1da177e4	88	{
2fbe7b25 DZ	89	struct die_args args = (struct die_args )data;
	90	int ret = NOTIFY_DONE;
	91	int cpu = smp_processor_id();
	92
	93	switch(val) {
	94	case DIE_NMI:
	95	if (model->check_ctrs(args->regs, &cpu_msrs[cpu]))
	96	ret = NOTIFY_STOP;
	97	break;
	98	default:
	99	break;
	100	}
	101	return ret;
1da177e4	102	}
2fbe7b25	103
1da177e4 LT	104	static void nmi_cpu_save_registers(struct op_msrs * msrs)
	105	{
	106	unsigned int const nr_ctrs = model->num_counters;
	107	unsigned int const nr_ctrls = model->num_controls;
	108	struct op_msr * counters = msrs->counters;
	109	struct op_msr * controls = msrs->controls;
	110	unsigned int i;
	111
	112	for (i = 0; i < nr_ctrs; ++i) {
cb9c448c DZ	113	if (counters[i].addr){
	114	rdmsr(counters[i].addr,
	115	counters[i].saved.low,
	116	counters[i].saved.high);
	117	}
1da177e4 LT	118	}
	119
	120	for (i = 0; i < nr_ctrls; ++i) {
cb9c448c DZ	121	if (controls[i].addr){
	122	rdmsr(controls[i].addr,
	123	controls[i].saved.low,
	124	controls[i].saved.high);
	125	}
1da177e4 LT	126	}
	127	}
	128
	129
	130	static void nmi_save_registers(void * dummy)
	131	{
	132	int cpu = smp_processor_id();
	133	struct op_msrs * msrs = &cpu_msrs[cpu];
	134	model->fill_in_addresses(msrs);
	135	nmi_cpu_save_registers(msrs);
	136	}
	137
	138
	139	static void free_msrs(void)
	140	{
	141	int i;
c8912599	142	for_each_possible_cpu(i) {
1da177e4 LT	143	kfree(cpu_msrs[i].counters);
	144	cpu_msrs[i].counters = NULL;
	145	kfree(cpu_msrs[i].controls);
	146	cpu_msrs[i].controls = NULL;
	147	}
	148	}
	149
	150
	151	static int allocate_msrs(void)
	152	{
	153	int success = 1;
	154	size_t controls_size = sizeof(struct op_msr) * model->num_controls;
	155	size_t counters_size = sizeof(struct op_msr) * model->num_counters;
	156
	157	int i;
394e3902	158	for_each_online_cpu(i) {
1da177e4 LT	159	cpu_msrs[i].counters = kmalloc(counters_size, GFP_KERNEL);
	160	if (!cpu_msrs[i].counters) {
	161	success = 0;
	162	break;
	163	}
	164	cpu_msrs[i].controls = kmalloc(controls_size, GFP_KERNEL);
	165	if (!cpu_msrs[i].controls) {
	166	success = 0;
	167	break;
	168	}
	169	}
	170
	171	if (!success)
	172	free_msrs();
	173
	174	return success;
	175	}
	176
	177
	178	static void nmi_cpu_setup(void * dummy)
	179	{
	180	int cpu = smp_processor_id();
	181	struct op_msrs * msrs = &cpu_msrs[cpu];
	182	spin_lock(&oprofilefs_lock);
	183	model->setup_ctrs(msrs);
	184	spin_unlock(&oprofilefs_lock);
	185	saved_lvtpc[cpu] = apic_read(APIC_LVTPC);
	186	apic_write(APIC_LVTPC, APIC_DM_NMI);
	187	}
	188
2fbe7b25 DZ	189	static struct notifier_block profile_exceptions_nb = {
	190	.notifier_call = profile_exceptions_notify,
	191	.next = NULL,
	192	.priority = 0
	193	};
1da177e4 LT	194
	195	static int nmi_setup(void)
	196	{
2fbe7b25 DZ	197	int err=0;
2fbe7b25 DZ	198
1da177e4 LT	199	if (!allocate_msrs())
	200	return -ENOMEM;
	201
2fbe7b25	202	if ((err = register_die_notifier(&profile_exceptions_nb))){
1da177e4	203	free_msrs();
2fbe7b25	204	return err;
1da177e4	205	}
2fbe7b25	206
1da177e4 LT	207	/* We need to serialize save and setup for HT because the subset
	208	* of msrs are distinct for save and setup operations
	209	*/
	210	on_each_cpu(nmi_save_registers, NULL, 0, 1);
	211	on_each_cpu(nmi_cpu_setup, NULL, 0, 1);
1da177e4 LT	212	nmi_enabled = 1;
	213	return 0;
	214	}
	215
	216
	217	static void nmi_restore_registers(struct op_msrs * msrs)
	218	{
	219	unsigned int const nr_ctrs = model->num_counters;
	220	unsigned int const nr_ctrls = model->num_controls;
	221	struct op_msr * counters = msrs->counters;
	222	struct op_msr * controls = msrs->controls;
	223	unsigned int i;
	224
	225	for (i = 0; i < nr_ctrls; ++i) {
cb9c448c DZ	226	if (controls[i].addr){
	227	wrmsr(controls[i].addr,
	228	controls[i].saved.low,
	229	controls[i].saved.high);
	230	}
1da177e4 LT	231	}
	232
	233	for (i = 0; i < nr_ctrs; ++i) {
cb9c448c DZ	234	if (counters[i].addr){
	235	wrmsr(counters[i].addr,
	236	counters[i].saved.low,
	237	counters[i].saved.high);
	238	}
1da177e4 LT	239	}
	240	}
	241
	242
	243	static void nmi_cpu_shutdown(void * dummy)
	244	{
	245	unsigned int v;
	246	int cpu = smp_processor_id();
	247	struct op_msrs * msrs = &cpu_msrs[cpu];
	248
	249	/* restoring APIC_LVTPC can trigger an apic error because the delivery
	250	* mode and vector nr combination can be illegal. That's by design: on
	251	* power on apic lvt contain a zero vector nr which are legal only for
	252	* NMI delivery mode. So inhibit apic err before restoring lvtpc
	253	*/
	254	v = apic_read(APIC_LVTERR);
	255	apic_write(APIC_LVTERR, v \| APIC_LVT_MASKED);
	256	apic_write(APIC_LVTPC, saved_lvtpc[cpu]);
	257	apic_write(APIC_LVTERR, v);
	258	nmi_restore_registers(msrs);
cb9c448c	259	model->shutdown(msrs);
1da177e4 LT	260	}
	261
	262
	263	static void nmi_shutdown(void)
	264	{
	265	nmi_enabled = 0;
	266	on_each_cpu(nmi_cpu_shutdown, NULL, 0, 1);
2fbe7b25	267	unregister_die_notifier(&profile_exceptions_nb);
1da177e4 LT	268	free_msrs();
	269	}
	270
	271
	272	static void nmi_cpu_start(void * dummy)
	273	{
	274	struct op_msrs const * msrs = &cpu_msrs[smp_processor_id()];
	275	model->start(msrs);
	276	}
	277
	278
	279	static int nmi_start(void)
	280	{
	281	on_each_cpu(nmi_cpu_start, NULL, 0, 1);
	282	return 0;
	283	}
	284
	285
	286	static void nmi_cpu_stop(void * dummy)
	287	{
	288	struct op_msrs const * msrs = &cpu_msrs[smp_processor_id()];
	289	model->stop(msrs);
	290	}
	291
	292
	293	static void nmi_stop(void)
	294	{
	295	on_each_cpu(nmi_cpu_stop, NULL, 0, 1);
	296	}
	297
	298
	299	struct op_counter_config counter_config[OP_MAX_COUNTER];
	300
	301	static int nmi_create_files(struct super_block * sb, struct dentry * root)
	302	{
	303	unsigned int i;
	304
	305	for (i = 0; i < model->num_counters; ++i) {
	306	struct dentry * dir;
0c6856f7	307	char buf[4];
1da177e4	308
cb9c448c DZ	309	/* quick little hack to _not_ expose a counter if it is not
	310	* available for use. This should protect userspace app.
	311	* NOTE: assumes 1:1 mapping here (that counters are organized
	312	* sequentially in their struct assignment).
	313	*/
	314	if (unlikely(!avail_to_resrv_perfctr_nmi_bit(i)))
	315	continue;
	316
0c6856f7	317	snprintf(buf, sizeof(buf), "%d", i);
1da177e4 LT	318	dir = oprofilefs_mkdir(sb, root, buf);
	319	oprofilefs_create_ulong(sb, dir, "enabled", &counter_config[i].enabled);
	320	oprofilefs_create_ulong(sb, dir, "event", &counter_config[i].event);
	321	oprofilefs_create_ulong(sb, dir, "count", &counter_config[i].count);
	322	oprofilefs_create_ulong(sb, dir, "unit_mask", &counter_config[i].unit_mask);
	323	oprofilefs_create_ulong(sb, dir, "kernel", &counter_config[i].kernel);
	324	oprofilefs_create_ulong(sb, dir, "user", &counter_config[i].user);
	325	}
	326
	327	return 0;
	328	}
	329
1cfcea1b AK	330	static int p4force;
1cfcea1b AK	331	module_param(p4force, int, 0);
1da177e4 LT	332
	333	static int __init p4_init(char ** cpu_type)
	334	{
	335	__u8 cpu_model = boot_cpu_data.x86_model;
	336
1cfcea1b	337	if (!p4force && (cpu_model > 6 \|\| cpu_model == 5))
1da177e4 LT	338	return 0;
	339
	340	#ifndef CONFIG_SMP
	341	*cpu_type = "i386/p4";
	342	model = &op_p4_spec;
	343	return 1;
	344	#else
	345	switch (smp_num_siblings) {
	346	case 1:
	347	*cpu_type = "i386/p4";
	348	model = &op_p4_spec;
	349	return 1;
	350
	351	case 2:
	352	*cpu_type = "i386/p4-ht";
	353	model = &op_p4_ht2_spec;
	354	return 1;
	355	}
	356	#endif
	357
	358	printk(KERN_INFO "oprofile: P4 HyperThreading detected with > 2 threads\n");
	359	printk(KERN_INFO "oprofile: Reverting to timer mode.\n");
	360	return 0;
	361	}
	362
	363
	364	static int __init ppro_init(char ** cpu_type)
	365	{
	366	__u8 cpu_model = boot_cpu_data.x86_model;
	367
64471ebe BL	368	if (cpu_model == 14)
64471ebe BL	369	*cpu_type = "i386/core";
f04b92e9 BL	370	else if (cpu_model == 15)
f04b92e9 BL	371	*cpu_type = "i386/core_2";
64471ebe	372	else if (cpu_model > 0xd)
1da177e4	373	return 0;
64471ebe	374	else if (cpu_model == 9) {
1da177e4 LT	375	*cpu_type = "i386/p6_mobile";
	376	} else if (cpu_model > 5) {
	377	*cpu_type = "i386/piii";
	378	} else if (cpu_model > 2) {
	379	*cpu_type = "i386/pii";
	380	} else {
	381	*cpu_type = "i386/ppro";
	382	}
	383
	384	model = &op_ppro_spec;
	385	return 1;
	386	}
	387
405ae7d3	388	/* in order to get sysfs right */
1da177e4 LT	389	static int using_nmi;
1da177e4 LT	390
96d0821c	391	int __init op_nmi_init(struct oprofile_operations *ops)
1da177e4 LT	392	{
	393	__u8 vendor = boot_cpu_data.x86_vendor;
	394	__u8 family = boot_cpu_data.x86;
	395	char *cpu_type;
	396
	397	if (!cpu_has_apic)
	398	return -ENODEV;
	399
	400	switch (vendor) {
	401	case X86_VENDOR_AMD:
	402	/* Needs to be at least an Athlon (or hammer in 32bit mode) */
	403
	404	switch (family) {
	405	default:
	406	return -ENODEV;
	407	case 6:
	408	model = &op_athlon_spec;
	409	cpu_type = "i386/athlon";
	410	break;
	411	case 0xf:
	412	model = &op_athlon_spec;
	413	/* Actually it could be i386/hammer too, but give
	414	user space an consistent name. */
	415	cpu_type = "x86-64/hammer";
	416	break;
2a12652c AK	417	case 0x10:
	418	model = &op_athlon_spec;
	419	cpu_type = "x86-64/family10";
	420	break;
1da177e4 LT	421	}
	422	break;
	423
	424	case X86_VENDOR_INTEL:
	425	switch (family) {
	426	/* Pentium IV */
	427	case 0xf:
	428	if (!p4_init(&cpu_type))
	429	return -ENODEV;
	430	break;
	431
	432	/* A P6-class processor */
	433	case 6:
	434	if (!ppro_init(&cpu_type))
	435	return -ENODEV;
	436	break;
	437
	438	default:
	439	return -ENODEV;
	440	}
	441	break;
	442
	443	default:
	444	return -ENODEV;
	445	}
	446
405ae7d3	447	init_sysfs();
1da177e4 LT	448	using_nmi = 1;
	449	ops->create_files = nmi_create_files;
	450	ops->setup = nmi_setup;
	451	ops->shutdown = nmi_shutdown;
	452	ops->start = nmi_start;
	453	ops->stop = nmi_stop;
	454	ops->cpu_type = cpu_type;
	455	printk(KERN_INFO "oprofile: using NMI interrupt.\n");
	456	return 0;
	457	}
	458
	459
96d0821c	460	void op_nmi_exit(void)
1da177e4 LT	461	{
1da177e4 LT	462	if (using_nmi)
405ae7d3	463	exit_sysfs();
1da177e4	464	}