[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / i386 / kernel / time_hpet.c

/*
 *  linux/arch/i386/kernel/time_hpet.c
 *  This code largely copied from arch/x86_64/kernel/time.c
 *  See that file for credits.
 *
 *  2003-06-30    Venkatesh Pallipadi - Additional changes for HPET support
 */

#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/string.h>
#include <linux/init.h>
#include <linux/smp.h>

#include <asm/timer.h>
#include <asm/fixmap.h>
#include <asm/apic.h>

#include <linux/timex.h>

#include <asm/hpet.h>
#include <linux/hpet.h>

static unsigned long hpet_period;	/* fsecs / HPET clock */
unsigned long hpet_tick;		/* hpet clks count per tick */
unsigned long hpet_address;		/* hpet memory map physical address */
int hpet_use_timer;

static int use_hpet; 		/* can be used for runtime check of hpet */
static int boot_hpet_disable; 	/* boottime override for HPET timer */
static void __iomem * hpet_virt_address;	/* hpet kernel virtual address */

#define FSEC_TO_USEC (1000000000UL)

int hpet_readl(unsigned long a)
{
	return readl(hpet_virt_address + a);
}

static void hpet_writel(unsigned long d, unsigned long a)
{
	writel(d, hpet_virt_address + a);
}

#ifdef CONFIG_X86_LOCAL_APIC
/*
 * HPET counters dont wrap around on every tick. They just change the
 * comparator value and continue. Next tick can be caught by checking
 * for a change in the comparator value. Used in apic.c.
 */
static void __devinit wait_hpet_tick(void)
{
	unsigned int start_cmp_val, end_cmp_val;

	start_cmp_val = hpet_readl(HPET_T0_CMP);
	do {
		end_cmp_val = hpet_readl(HPET_T0_CMP);
	} while (start_cmp_val == end_cmp_val);
}
#endif

static int hpet_timer_stop_set_go(unsigned long tick)
{
	unsigned int cfg;

	/*
	 * Stop the timers and reset the main counter.
	 */
	cfg = hpet_readl(HPET_CFG);
	cfg &= ~HPET_CFG_ENABLE;
	hpet_writel(cfg, HPET_CFG);
	hpet_writel(0, HPET_COUNTER);
	hpet_writel(0, HPET_COUNTER + 4);

	if (hpet_use_timer) {
		/*
		 * Set up timer 0, as periodic with first interrupt to happen at
		 * hpet_tick, and period also hpet_tick.
		 */
		cfg = hpet_readl(HPET_T0_CFG);
		cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC |
		       HPET_TN_SETVAL | HPET_TN_32BIT;
		hpet_writel(cfg, HPET_T0_CFG);

		/*
		 * The first write after writing TN_SETVAL to the config register sets
		 * the counter value, the second write sets the threshold.
		 */
		hpet_writel(tick, HPET_T0_CMP);
		hpet_writel(tick, HPET_T0_CMP);
	}
	/*
 	 * Go!
 	 */
	cfg = hpet_readl(HPET_CFG);
	if (hpet_use_timer)
		cfg |= HPET_CFG_LEGACY;
	cfg |= HPET_CFG_ENABLE;
	hpet_writel(cfg, HPET_CFG);

	return 0;
}

/*
 * Check whether HPET was found by ACPI boot parse. If yes setup HPET
 * counter 0 for kernel base timer.
 */
int __init hpet_enable(void)
{
	unsigned int id;
	unsigned long tick_fsec_low, tick_fsec_high; /* tick in femto sec */
	unsigned long hpet_tick_rem;

	if (boot_hpet_disable)
		return -1;

	if (!hpet_address) {
		return -1;
	}
	hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE);
	/*
	 * Read the period, compute tick and quotient.
	 */
	id = hpet_readl(HPET_ID);

	/*
	 * We are checking for value '1' or more in number field if
	 * CONFIG_HPET_EMULATE_RTC is set because we will need an
	 * additional timer for RTC emulation.
	 * However, we can do with one timer otherwise using the
	 * the single HPET timer for system time.
	 */
#ifdef CONFIG_HPET_EMULATE_RTC
	if (!(id & HPET_ID_NUMBER))
		return -1;
#endif


	hpet_period = hpet_readl(HPET_PERIOD);
	if ((hpet_period < HPET_MIN_PERIOD) || (hpet_period > HPET_MAX_PERIOD))
		return -1;

	/*
	 * 64 bit math
	 * First changing tick into fsec
	 * Then 64 bit div to find number of hpet clk per tick
	 */
	ASM_MUL64_REG(tick_fsec_low, tick_fsec_high,
			KERNEL_TICK_USEC, FSEC_TO_USEC);
	ASM_DIV64_REG(hpet_tick, hpet_tick_rem,
			hpet_period, tick_fsec_low, tick_fsec_high);

	if (hpet_tick_rem > (hpet_period >> 1))
		hpet_tick++; /* rounding the result */

	hpet_use_timer = id & HPET_ID_LEGSUP;

	if (hpet_timer_stop_set_go(hpet_tick))
		return -1;

	use_hpet = 1;

#ifdef	CONFIG_HPET
	{
		struct hpet_data	hd;
		unsigned int 		ntimer;

		memset(&hd, 0, sizeof (hd));

		ntimer = hpet_readl(HPET_ID);
		ntimer = (ntimer & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT;
		ntimer++;

		/*
		 * Register with driver.
		 * Timer0 and Timer1 is used by platform.
		 */
		hd.hd_phys_address = hpet_address;
		hd.hd_address = hpet_virt_address;
		hd.hd_nirqs = ntimer;
		hd.hd_flags = HPET_DATA_PLATFORM;
		hpet_reserve_timer(&hd, 0);
#ifdef	CONFIG_HPET_EMULATE_RTC
		hpet_reserve_timer(&hd, 1);
#endif
		hd.hd_irq[0] = HPET_LEGACY_8254;
		hd.hd_irq[1] = HPET_LEGACY_RTC;
		if (ntimer > 2) {
			struct hpet __iomem	*hpet;
			struct hpet_timer __iomem *timer;
			int			i;

			hpet = hpet_virt_address;

			for (i = 2, timer = &hpet->hpet_timers[2]; i < ntimer;
				timer++, i++)
				hd.hd_irq[i] = (timer->hpet_config &
					Tn_INT_ROUTE_CNF_MASK) >>
					Tn_INT_ROUTE_CNF_SHIFT;

		}

		hpet_alloc(&hd);
	}
#endif

#ifdef CONFIG_X86_LOCAL_APIC
	if (hpet_use_timer)
		wait_timer_tick = wait_hpet_tick;
#endif
	return 0;
}

int hpet_reenable(void)
{
	return hpet_timer_stop_set_go(hpet_tick);
}

int is_hpet_enabled(void)
{
	return use_hpet;
}

int is_hpet_capable(void)
{
	if (!boot_hpet_disable && hpet_address)
		return 1;
	return 0;
}

static int __init hpet_setup(char* str)
{
	if (str) {
		if (!strncmp("disable", str, 7))
			boot_hpet_disable = 1;
	}
	return 1;
}

__setup("hpet=", hpet_setup);

#ifdef CONFIG_HPET_EMULATE_RTC
/* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET
 * is enabled, we support RTC interrupt functionality in software.
 * RTC has 3 kinds of interrupts:
 * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock
 *    is updated
 * 2) Alarm Interrupt - generate an interrupt at a specific time of day
 * 3) Periodic Interrupt - generate periodic interrupt, with frequencies
 *    2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2)
 * (1) and (2) above are implemented using polling at a frequency of
 * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt
 * overhead. (DEFAULT_RTC_INT_FREQ)
 * For (3), we use interrupts at 64Hz or user specified periodic
 * frequency, whichever is higher.
 */
#include <linux/mc146818rtc.h>
#include <linux/rtc.h>

#define DEFAULT_RTC_INT_FREQ 	64
#define RTC_NUM_INTS 		1

static unsigned long UIE_on;
static unsigned long prev_update_sec;

static unsigned long AIE_on;
static struct rtc_time alarm_time;

static unsigned long PIE_on;
static unsigned long PIE_freq = DEFAULT_RTC_INT_FREQ;
static unsigned long PIE_count;

static unsigned long hpet_rtc_int_freq; /* RTC interrupt frequency */
static unsigned int hpet_t1_cmp; /* cached comparator register */

/*
 * Timer 1 for RTC, we do not use periodic interrupt feature,
 * even if HPET supports periodic interrupts on Timer 1.
 * The reason being, to set up a periodic interrupt in HPET, we need to
 * stop the main counter. And if we do that everytime someone diables/enables
 * RTC, we will have adverse effect on main kernel timer running on Timer 0.
 * So, for the time being, simulate the periodic interrupt in software.
 *
 * hpet_rtc_timer_init() is called for the first time and during subsequent
 * interuppts reinit happens through hpet_rtc_timer_reinit().
 */
int hpet_rtc_timer_init(void)
{
	unsigned int cfg, cnt;
	unsigned long flags;

	if (!is_hpet_enabled())
		return 0;
	/*
	 * Set the counter 1 and enable the interrupts.
	 */
	if (PIE_on && (PIE_freq > DEFAULT_RTC_INT_FREQ))
		hpet_rtc_int_freq = PIE_freq;
	else
		hpet_rtc_int_freq = DEFAULT_RTC_INT_FREQ;

	local_irq_save(flags);

	cnt = hpet_readl(HPET_COUNTER);
	cnt += ((hpet_tick*HZ)/hpet_rtc_int_freq);
	hpet_writel(cnt, HPET_T1_CMP);
	hpet_t1_cmp = cnt;

	cfg = hpet_readl(HPET_T1_CFG);
	cfg &= ~HPET_TN_PERIODIC;
	cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
	hpet_writel(cfg, HPET_T1_CFG);

	local_irq_restore(flags);

	return 1;
}

static void hpet_rtc_timer_reinit(void)
{
	unsigned int cfg, cnt, ticks_per_int, lost_ints;

	if (unlikely(!(PIE_on | AIE_on | UIE_on))) {
		cfg = hpet_readl(HPET_T1_CFG);
		cfg &= ~HPET_TN_ENABLE;
		hpet_writel(cfg, HPET_T1_CFG);
		return;
	}

	if (PIE_on && (PIE_freq > DEFAULT_RTC_INT_FREQ))
		hpet_rtc_int_freq = PIE_freq;
	else
		hpet_rtc_int_freq = DEFAULT_RTC_INT_FREQ;

	/* It is more accurate to use the comparator value than current count.*/
	ticks_per_int = hpet_tick * HZ / hpet_rtc_int_freq;
	hpet_t1_cmp += ticks_per_int;
	hpet_writel(hpet_t1_cmp, HPET_T1_CMP);

	/*
	 * If the interrupt handler was delayed too long, the write above tries
	 * to schedule the next interrupt in the past and the hardware would
	 * not interrupt until the counter had wrapped around.
	 * So we have to check that the comparator wasn't set to a past time.
	 */
	cnt = hpet_readl(HPET_COUNTER);
	if (unlikely((int)(cnt - hpet_t1_cmp) > 0)) {
		lost_ints = (cnt - hpet_t1_cmp) / ticks_per_int + 1;
		/* Make sure that, even with the time needed to execute
		 * this code, the next scheduled interrupt has been moved
		 * back to the future: */
		lost_ints++;

		hpet_t1_cmp += lost_ints * ticks_per_int;
		hpet_writel(hpet_t1_cmp, HPET_T1_CMP);

		if (PIE_on)
			PIE_count += lost_ints;

		printk(KERN_WARNING "rtc: lost some interrupts at %ldHz.\n",
		       hpet_rtc_int_freq);
	}
}

/*
 * The functions below are called from rtc driver.
 * Return 0 if HPET is not being used.
 * Otherwise do the necessary changes and return 1.
 */
int hpet_mask_rtc_irq_bit(unsigned long bit_mask)
{
	if (!is_hpet_enabled())
		return 0;

	if (bit_mask & RTC_UIE)
		UIE_on = 0;
	if (bit_mask & RTC_PIE)
		PIE_on = 0;
	if (bit_mask & RTC_AIE)
		AIE_on = 0;

	return 1;
}

int hpet_set_rtc_irq_bit(unsigned long bit_mask)
{
	int timer_init_reqd = 0;

	if (!is_hpet_enabled())
		return 0;

	if (!(PIE_on | AIE_on | UIE_on))
		timer_init_reqd = 1;

	if (bit_mask & RTC_UIE) {
		UIE_on = 1;
	}
	if (bit_mask & RTC_PIE) {
		PIE_on = 1;
		PIE_count = 0;
	}
	if (bit_mask & RTC_AIE) {
		AIE_on = 1;
	}

	if (timer_init_reqd)
		hpet_rtc_timer_init();

	return 1;
}

int hpet_set_alarm_time(unsigned char hrs, unsigned char min, unsigned char sec)
{
	if (!is_hpet_enabled())
		return 0;

	alarm_time.tm_hour = hrs;
	alarm_time.tm_min = min;
	alarm_time.tm_sec = sec;

	return 1;
}

int hpet_set_periodic_freq(unsigned long freq)
{
	if (!is_hpet_enabled())
		return 0;

	PIE_freq = freq;
	PIE_count = 0;

	return 1;
}

int hpet_rtc_dropped_irq(void)
{
	if (!is_hpet_enabled())
		return 0;

	return 1;
}

irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id)
{
	struct rtc_time curr_time;
	unsigned long rtc_int_flag = 0;
	int call_rtc_interrupt = 0;

	hpet_rtc_timer_reinit();

	if (UIE_on | AIE_on) {
		rtc_get_rtc_time(&curr_time);
	}
	if (UIE_on) {
		if (curr_time.tm_sec != prev_update_sec) {
			/* Set update int info, call real rtc int routine */
			call_rtc_interrupt = 1;
			rtc_int_flag = RTC_UF;
			prev_update_sec = curr_time.tm_sec;
		}
	}
	if (PIE_on) {
		PIE_count++;
		if (PIE_count >= hpet_rtc_int_freq/PIE_freq) {
			/* Set periodic int info, call real rtc int routine */
			call_rtc_interrupt = 1;
			rtc_int_flag |= RTC_PF;
			PIE_count = 0;
		}
	}
	if (AIE_on) {
		if ((curr_time.tm_sec == alarm_time.tm_sec) &&
		    (curr_time.tm_min == alarm_time.tm_min) &&
		    (curr_time.tm_hour == alarm_time.tm_hour)) {
			/* Set alarm int info, call real rtc int routine */
			call_rtc_interrupt = 1;
			rtc_int_flag |= RTC_AF;
		}
	}
	if (call_rtc_interrupt) {
		rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8));
		rtc_interrupt(rtc_int_flag, dev_id);
	}
	return IRQ_HANDLED;
}
#endif
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/i386/kernel/time_hpet.c
	3	* This code largely copied from arch/x86_64/kernel/time.c
	4	* See that file for credits.
	5	*
	6	* 2003-06-30 Venkatesh Pallipadi - Additional changes for HPET support
	7	*/
	8
	9	#include <linux/errno.h>
	10	#include <linux/kernel.h>
	11	#include <linux/param.h>
	12	#include <linux/string.h>
	13	#include <linux/init.h>
	14	#include <linux/smp.h>
	15
	16	#include <asm/timer.h>
	17	#include <asm/fixmap.h>
	18	#include <asm/apic.h>
	19
	20	#include <linux/timex.h>
1da177e4 LT	21
	22	#include <asm/hpet.h>
	23	#include <linux/hpet.h>
	24
	25	static unsigned long hpet_period; /* fsecs / HPET clock */
	26	unsigned long hpet_tick; /* hpet clks count per tick */
	27	unsigned long hpet_address; /* hpet memory map physical address */
35492df5	28	int hpet_use_timer;
1da177e4 LT	29
	30	static int use_hpet; /* can be used for runtime check of hpet */
	31	static int boot_hpet_disable; /* boottime override for HPET timer */
	32	static void __iomem * hpet_virt_address; /* hpet kernel virtual address */
	33
	34	#define FSEC_TO_USEC (1000000000UL)
	35
	36	int hpet_readl(unsigned long a)
	37	{
	38	return readl(hpet_virt_address + a);
	39	}
	40
	41	static void hpet_writel(unsigned long d, unsigned long a)
	42	{
	43	writel(d, hpet_virt_address + a);
	44	}
	45
	46	#ifdef CONFIG_X86_LOCAL_APIC
	47	/*
	48	* HPET counters dont wrap around on every tick. They just change the
	49	* comparator value and continue. Next tick can be caught by checking
	50	* for a change in the comparator value. Used in apic.c.
	51	*/
a13db566	52	static void __devinit wait_hpet_tick(void)
1da177e4 LT	53	{
	54	unsigned int start_cmp_val, end_cmp_val;
	55
	56	start_cmp_val = hpet_readl(HPET_T0_CMP);
	57	do {
	58	end_cmp_val = hpet_readl(HPET_T0_CMP);
	59	} while (start_cmp_val == end_cmp_val);
	60	}
	61	#endif
	62
	63	static int hpet_timer_stop_set_go(unsigned long tick)
	64	{
	65	unsigned int cfg;
	66
	67	/*
	68	* Stop the timers and reset the main counter.
	69	*/
	70	cfg = hpet_readl(HPET_CFG);
	71	cfg &= ~HPET_CFG_ENABLE;
	72	hpet_writel(cfg, HPET_CFG);
	73	hpet_writel(0, HPET_COUNTER);
	74	hpet_writel(0, HPET_COUNTER + 4);
	75
35492df5 JS	76	if (hpet_use_timer) {
	77	/*
	78	* Set up timer 0, as periodic with first interrupt to happen at
	79	* hpet_tick, and period also hpet_tick.
	80	*/
	81	cfg = hpet_readl(HPET_T0_CFG);
	82	cfg \|= HPET_TN_ENABLE \| HPET_TN_PERIODIC \|
	83	HPET_TN_SETVAL \| HPET_TN_32BIT;
	84	hpet_writel(cfg, HPET_T0_CFG);
1da177e4	85
35492df5 JS	86	/*
	87	* The first write after writing TN_SETVAL to the config register sets
	88	* the counter value, the second write sets the threshold.
	89	*/
	90	hpet_writel(tick, HPET_T0_CMP);
	91	hpet_writel(tick, HPET_T0_CMP);
	92	}
1da177e4 LT	93	/*
	94	* Go!
	95	*/
	96	cfg = hpet_readl(HPET_CFG);
35492df5 JS	97	if (hpet_use_timer)
	98	cfg \|= HPET_CFG_LEGACY;
	99	cfg \|= HPET_CFG_ENABLE;
1da177e4 LT	100	hpet_writel(cfg, HPET_CFG);
	101
	102	return 0;
	103	}
	104
	105	/*
	106	* Check whether HPET was found by ACPI boot parse. If yes setup HPET
	107	* counter 0 for kernel base timer.
	108	*/
	109	int __init hpet_enable(void)
	110	{
	111	unsigned int id;
	112	unsigned long tick_fsec_low, tick_fsec_high; /* tick in femto sec */
	113	unsigned long hpet_tick_rem;
	114
	115	if (boot_hpet_disable)
	116	return -1;
	117
	118	if (!hpet_address) {
	119	return -1;
	120	}
	121	hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE);
	122	/*
	123	* Read the period, compute tick and quotient.
	124	*/
	125	id = hpet_readl(HPET_ID);
	126
	127	/*
	128	* We are checking for value '1' or more in number field if
	129	* CONFIG_HPET_EMULATE_RTC is set because we will need an
	130	* additional timer for RTC emulation.
	131	* However, we can do with one timer otherwise using the
	132	* the single HPET timer for system time.
	133	*/
1da177e4	134	#ifdef CONFIG_HPET_EMULATE_RTC
35492df5	135	if (!(id & HPET_ID_NUMBER))
1da177e4	136	return -1;
35492df5 JS	137	#endif
35492df5 JS	138
1da177e4 LT	139
	140	hpet_period = hpet_readl(HPET_PERIOD);
	141	if ((hpet_period < HPET_MIN_PERIOD) \|\| (hpet_period > HPET_MAX_PERIOD))
	142	return -1;
	143
	144	/*
	145	* 64 bit math
	146	* First changing tick into fsec
	147	* Then 64 bit div to find number of hpet clk per tick
	148	*/
	149	ASM_MUL64_REG(tick_fsec_low, tick_fsec_high,
	150	KERNEL_TICK_USEC, FSEC_TO_USEC);
	151	ASM_DIV64_REG(hpet_tick, hpet_tick_rem,
	152	hpet_period, tick_fsec_low, tick_fsec_high);
	153
	154	if (hpet_tick_rem > (hpet_period >> 1))
	155	hpet_tick++; /* rounding the result */
	156
35492df5 JS	157	hpet_use_timer = id & HPET_ID_LEGSUP;
35492df5 JS	158
1da177e4 LT	159	if (hpet_timer_stop_set_go(hpet_tick))
	160	return -1;
	161
	162	use_hpet = 1;
	163
	164	#ifdef CONFIG_HPET
	165	{
	166	struct hpet_data hd;
	167	unsigned int ntimer;
	168
	169	memset(&hd, 0, sizeof (hd));
	170
	171	ntimer = hpet_readl(HPET_ID);
	172	ntimer = (ntimer & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT;
	173	ntimer++;
	174
	175	/*
	176	* Register with driver.
	177	* Timer0 and Timer1 is used by platform.
	178	*/
	179	hd.hd_phys_address = hpet_address;
	180	hd.hd_address = hpet_virt_address;
	181	hd.hd_nirqs = ntimer;
	182	hd.hd_flags = HPET_DATA_PLATFORM;
	183	hpet_reserve_timer(&hd, 0);
	184	#ifdef CONFIG_HPET_EMULATE_RTC
	185	hpet_reserve_timer(&hd, 1);
	186	#endif
	187	hd.hd_irq[0] = HPET_LEGACY_8254;
	188	hd.hd_irq[1] = HPET_LEGACY_RTC;
	189	if (ntimer > 2) {
	190	struct hpet __iomem *hpet;
	191	struct hpet_timer __iomem *timer;
	192	int i;
	193
	194	hpet = hpet_virt_address;
	195
	196	for (i = 2, timer = &hpet->hpet_timers[2]; i < ntimer;
	197	timer++, i++)
	198	hd.hd_irq[i] = (timer->hpet_config &
	199	Tn_INT_ROUTE_CNF_MASK) >>
	200	Tn_INT_ROUTE_CNF_SHIFT;
	201
	202	}
	203
	204	hpet_alloc(&hd);
	205	}
	206	#endif
	207
	208	#ifdef CONFIG_X86_LOCAL_APIC
35492df5 JS	209	if (hpet_use_timer)
35492df5 JS	210	wait_timer_tick = wait_hpet_tick;
1da177e4 LT	211	#endif
	212	return 0;
	213	}
	214
	215	int hpet_reenable(void)
	216	{
	217	return hpet_timer_stop_set_go(hpet_tick);
	218	}
	219
	220	int is_hpet_enabled(void)
	221	{
	222	return use_hpet;
	223	}
	224
	225	int is_hpet_capable(void)
	226	{
	227	if (!boot_hpet_disable && hpet_address)
	228	return 1;
	229	return 0;
	230	}
	231
	232	static int __init hpet_setup(char* str)
	233	{
	234	if (str) {
	235	if (!strncmp("disable", str, 7))
	236	boot_hpet_disable = 1;
	237	}
	238	return 1;
	239	}
	240
	241	__setup("hpet=", hpet_setup);
	242
	243	#ifdef CONFIG_HPET_EMULATE_RTC
	244	/* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET
	245	* is enabled, we support RTC interrupt functionality in software.
	246	* RTC has 3 kinds of interrupts:
	247	* 1) Update Interrupt - generate an interrupt, every sec, when RTC clock
	248	* is updated
	249	* 2) Alarm Interrupt - generate an interrupt at a specific time of day
	250	* 3) Periodic Interrupt - generate periodic interrupt, with frequencies
	251	* 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2)
	252	* (1) and (2) above are implemented using polling at a frequency of
	253	* 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt
	254	* overhead. (DEFAULT_RTC_INT_FREQ)
	255	* For (3), we use interrupts at 64Hz or user specified periodic
	256	* frequency, whichever is higher.
	257	*/
	258	#include <linux/mc146818rtc.h>
	259	#include <linux/rtc.h>
	260
1da177e4 LT	261	#define DEFAULT_RTC_INT_FREQ 64
	262	#define RTC_NUM_INTS 1
	263
	264	static unsigned long UIE_on;
	265	static unsigned long prev_update_sec;
	266
	267	static unsigned long AIE_on;
	268	static struct rtc_time alarm_time;
	269
	270	static unsigned long PIE_on;
	271	static unsigned long PIE_freq = DEFAULT_RTC_INT_FREQ;
	272	static unsigned long PIE_count;
	273
	274	static unsigned long hpet_rtc_int_freq; /* RTC interrupt frequency */
7811fb8f	275	static unsigned int hpet_t1_cmp; /* cached comparator register */
1da177e4 LT	276
	277	/*
	278	* Timer 1 for RTC, we do not use periodic interrupt feature,
	279	* even if HPET supports periodic interrupts on Timer 1.
	280	* The reason being, to set up a periodic interrupt in HPET, we need to
	281	* stop the main counter. And if we do that everytime someone diables/enables
	282	* RTC, we will have adverse effect on main kernel timer running on Timer 0.
	283	* So, for the time being, simulate the periodic interrupt in software.
	284	*
	285	* hpet_rtc_timer_init() is called for the first time and during subsequent
	286	* interuppts reinit happens through hpet_rtc_timer_reinit().
	287	*/
	288	int hpet_rtc_timer_init(void)
	289	{
	290	unsigned int cfg, cnt;
	291	unsigned long flags;
	292
	293	if (!is_hpet_enabled())
	294	return 0;
	295	/*
	296	* Set the counter 1 and enable the interrupts.
	297	*/
	298	if (PIE_on && (PIE_freq > DEFAULT_RTC_INT_FREQ))
	299	hpet_rtc_int_freq = PIE_freq;
	300	else
	301	hpet_rtc_int_freq = DEFAULT_RTC_INT_FREQ;
	302
	303	local_irq_save(flags);
1447c27d	304
1da177e4 LT	305	cnt = hpet_readl(HPET_COUNTER);
	306	cnt += ((hpet_tick*HZ)/hpet_rtc_int_freq);
	307	hpet_writel(cnt, HPET_T1_CMP);
7811fb8f	308	hpet_t1_cmp = cnt;
1da177e4 LT	309
1da177e4 LT	310	cfg = hpet_readl(HPET_T1_CFG);
5f819949 CL	311	cfg &= ~HPET_TN_PERIODIC;
5f819949 CL	312	cfg \|= HPET_TN_ENABLE \| HPET_TN_32BIT;
1da177e4 LT	313	hpet_writel(cfg, HPET_T1_CFG);
1da177e4 LT	314
1447c27d CL	315	local_irq_restore(flags);
1447c27d CL	316
1da177e4 LT	317	return 1;
	318	}
	319
	320	static void hpet_rtc_timer_reinit(void)
	321	{
1447c27d	322	unsigned int cfg, cnt, ticks_per_int, lost_ints;
1da177e4	323
f00c96f3 CL	324	if (unlikely(!(PIE_on \| AIE_on \| UIE_on))) {
	325	cfg = hpet_readl(HPET_T1_CFG);
	326	cfg &= ~HPET_TN_ENABLE;
	327	hpet_writel(cfg, HPET_T1_CFG);
1da177e4	328	return;
f00c96f3	329	}
1da177e4 LT	330
	331	if (PIE_on && (PIE_freq > DEFAULT_RTC_INT_FREQ))
	332	hpet_rtc_int_freq = PIE_freq;
	333	else
	334	hpet_rtc_int_freq = DEFAULT_RTC_INT_FREQ;
	335
	336	/* It is more accurate to use the comparator value than current count.*/
1447c27d CL	337	ticks_per_int = hpet_tick * HZ / hpet_rtc_int_freq;
	338	hpet_t1_cmp += ticks_per_int;
	339	hpet_writel(hpet_t1_cmp, HPET_T1_CMP);
	340
	341	/*
	342	* If the interrupt handler was delayed too long, the write above tries
	343	* to schedule the next interrupt in the past and the hardware would
	344	* not interrupt until the counter had wrapped around.
	345	* So we have to check that the comparator wasn't set to a past time.
	346	*/
	347	cnt = hpet_readl(HPET_COUNTER);
	348	if (unlikely((int)(cnt - hpet_t1_cmp) > 0)) {
	349	lost_ints = (cnt - hpet_t1_cmp) / ticks_per_int + 1;
	350	/* Make sure that, even with the time needed to execute
	351	* this code, the next scheduled interrupt has been moved
	352	* back to the future: */
	353	lost_ints++;
	354
	355	hpet_t1_cmp += lost_ints * ticks_per_int;
	356	hpet_writel(hpet_t1_cmp, HPET_T1_CMP);
	357
	358	if (PIE_on)
	359	PIE_count += lost_ints;
	360
	361	printk(KERN_WARNING "rtc: lost some interrupts at %ldHz.\n",
	362	hpet_rtc_int_freq);
	363	}
1da177e4 LT	364	}
	365
	366	/*
	367	* The functions below are called from rtc driver.
	368	* Return 0 if HPET is not being used.
	369	* Otherwise do the necessary changes and return 1.
	370	*/
	371	int hpet_mask_rtc_irq_bit(unsigned long bit_mask)
	372	{
	373	if (!is_hpet_enabled())
	374	return 0;
	375
	376	if (bit_mask & RTC_UIE)
	377	UIE_on = 0;
	378	if (bit_mask & RTC_PIE)
	379	PIE_on = 0;
	380	if (bit_mask & RTC_AIE)
	381	AIE_on = 0;
	382
	383	return 1;
	384	}
	385
	386	int hpet_set_rtc_irq_bit(unsigned long bit_mask)
	387	{
	388	int timer_init_reqd = 0;
	389
	390	if (!is_hpet_enabled())
	391	return 0;
	392
	393	if (!(PIE_on \| AIE_on \| UIE_on))
	394	timer_init_reqd = 1;
	395
	396	if (bit_mask & RTC_UIE) {
	397	UIE_on = 1;
	398	}
	399	if (bit_mask & RTC_PIE) {
	400	PIE_on = 1;
	401	PIE_count = 0;
	402	}
	403	if (bit_mask & RTC_AIE) {
	404	AIE_on = 1;
	405	}
	406
	407	if (timer_init_reqd)
	408	hpet_rtc_timer_init();
	409
	410	return 1;
	411	}
	412
	413	int hpet_set_alarm_time(unsigned char hrs, unsigned char min, unsigned char sec)
	414	{
	415	if (!is_hpet_enabled())
	416	return 0;
	417
	418	alarm_time.tm_hour = hrs;
	419	alarm_time.tm_min = min;
	420	alarm_time.tm_sec = sec;
	421
	422	return 1;
	423	}
	424
	425	int hpet_set_periodic_freq(unsigned long freq)
	426	{
	427	if (!is_hpet_enabled())
428	return 0;
429
430	PIE_freq = freq;
431	PIE_count = 0;
432
433	return 1;
434	}
435
436	int hpet_rtc_dropped_irq(void)
437	{
438	if (!is_hpet_enabled())
439	return 0;
440
441	return 1;
442	}
443
7d12e780	444	irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id)
1da177e4 LT	445	{
	446	struct rtc_time curr_time;
	447	unsigned long rtc_int_flag = 0;
	448	int call_rtc_interrupt = 0;
	449
	450	hpet_rtc_timer_reinit();
	451
	452	if (UIE_on \| AIE_on) {
	453	rtc_get_rtc_time(&curr_time);
	454	}
	455	if (UIE_on) {
	456	if (curr_time.tm_sec != prev_update_sec) {
	457	/* Set update int info, call real rtc int routine */
	458	call_rtc_interrupt = 1;
	459	rtc_int_flag = RTC_UF;
	460	prev_update_sec = curr_time.tm_sec;
	461	}
	462	}
	463	if (PIE_on) {
	464	PIE_count++;
	465	if (PIE_count >= hpet_rtc_int_freq/PIE_freq) {
	466	/* Set periodic int info, call real rtc int routine */
	467	call_rtc_interrupt = 1;
	468	rtc_int_flag \|= RTC_PF;
	469	PIE_count = 0;
	470	}
	471	}
	472	if (AIE_on) {
	473	if ((curr_time.tm_sec == alarm_time.tm_sec) &&
	474	(curr_time.tm_min == alarm_time.tm_min) &&
	475	(curr_time.tm_hour == alarm_time.tm_hour)) {
	476	/* Set alarm int info, call real rtc int routine */
	477	call_rtc_interrupt = 1;
	478	rtc_int_flag \|= RTC_AF;
	479	}
	480	}
	481	if (call_rtc_interrupt) {
	482	rtc_int_flag \|= (RTC_IRQF \| (RTC_NUM_INTS << 8));
7d12e780	483	rtc_interrupt(rtc_int_flag, dev_id);
1da177e4 LT	484	}
	485	return IRQ_HANDLED;
	486	}
	487	#endif
	488